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Do a Taylor expansion around the DC operating point (also called the quiescent
point or Q point) defined by the DC voltages Q(VGS, VDS, VBS):
2
∂i D 1∂ iD 2
iD = I D + ( v gs ) + --- ( v gs ) + …
∂ v GS 2 ∂ v2
Q GS
Q
If the small-signal voltage is really Òsmall,Ó then we can neglect all everything past
the linear term --
∂i D
iD = I D + ( v gs ) = I D + g m v gs
∂ v GS
Q
where the partial derivative is deÞned as the transconductance, gm.
id = gm vgs.
D iD = ID + id
G
+
+ B VDS = 4 V
vgs _
_
+ S
VGS = 3 V_
600
500
id vGS = VGS + vgs
iD 400
Q vGS = VGS = 3 V
(µA) 300
gm = id / vgs
200
100
1 2 3 4 5 6
VDS (V)
D iD = ID + id
G
+
+ B VDS = 4 V
vgs _
_
+ S
VGS = 3 V_
iD(vGS, VDS = 4 V)
600
500
id
gm = id / vgs
iD 400 Q
(µA) 300
200
100
1 2 3 4 5 6 vGS (V)
vGS = VGS = 3 V vGS = VGS + vgs
g m = µ n C ox ----- ( V GS Ð V Tn ) ( 1 + λ n V DS )
W
L
Note that the transconductance is a function of the operating point, through its
dependence on VGS and VDS -- and also the dependence of the threshold voltage on
the backgate bias VBS.
■ In order to Þnd a simple expression that highlights the dependence of gm on the
DC drain current, we neglect the (usually) small error in writing:
2I D
2µ n C ox ----- I D = --------------------------
W
gm =
L V GS Ð V Tn
For typical values (W/L) = 10, ID = 100 µA, and µnCox = 50 µAV-2 we Þnd that
gm = 320 µAV-1 = 0.32 mS
■ How do we make a circuit which expresses id = gm vgs ? Since the current is not
across the controlling voltage, we need a voltage-controlled current source:
gate id
+ drain
vgs gmvgs
_ source
_
■ We can also Þnd the change in drain current due to an increment in the drain-
source voltage:
∂i D
g o = ------------ = µ n C ox ------ ( V GS Ð V Tn ) λ n ≅ λ n I D
W 2
∂v 2L
DS
Q
id = gm vgs + (1/ro)vds
gate drain
+ +
id
gmvgs ro vds
vgs
_ source _
■ We can Þnd the small-signal drain current due to a change in the backgate bias
by the same technique. The chain rule comes in handy to make use of our
previous result for gm:
∂i D ∂i D ∂V Tn
g mb = ------------ = ------------ ------------
∂v BS ∂V Tn ∂v BS
Q Q Q
∂V Tn Ðγ n γ n gm
g mb = ( Ð g m ) ------------ = ( Ð g m ) ------------------------------------ = ------------------------------------ .
∂v BS 2 Ð 2 φ p Ð V BS 2 Ð 2 φ p Ð V BS
Q
g mb 2qε s N 1 qε s N a C b(y=0)
a
--------- = ---------------------------------------------- = --------- ------------------------------------- = --------------------
gm 2C ox Ð 2 φ p Ð V BS C ox 2 ( Ð 2 φ p Ð V BS ) C ox
where Cb(y=0) is the depletion capacitance at the source end of the channel --
gate
source channel
Cb(0) depletion
region
bulk
,,,
,
n+ n+
Csb qN (vGS) depletion
Cdb
overlap LD overlap LD region
In saturation, the gate-source capacitance contains two terms, one due to the
channel chargeÕs dependence on vGS [(2/3)WLCox] and one due to the overlap of
gate and source (WCov, where Cov is the overlap capacitance in fF per µm of gate
width)
2
C gs = --- WLC ox + W C ov
3
In addition, there are depletion capacitances between the drain and bulk (Cdb) and
between source and bulk (Csb). Finally, the extension of the gate over the Þeld oxide
leads to a small gate-bulk capacitance Cgb.
Cgd id
gate
+ drain
_ source
_
vbs Csb
Cdb
+
bulk
source
+
Cgb Csb
Cdb
_ bulk
■ Objectives:
¥ fabricating an IC costs $1000 ... $100,000 per run
---> nice to get it ÒrightÓ the Þrst time
¥ check results from hand-analysis
(e.g. validity of assumptions)
¥ evaluate functionality, speed, accuracy, ... of large circuit blocks or entire chips
■ Simulators:
¥ SPICE: invented at UC Berkeley circa 1970-1975
commercial versions: HSPICE, PSPICE, I-SPICE, ... (same core as Berkeley
SPICE, but add functionality, improved user interface, ...)
EE 105: student version of PSPICE on PC, limited to 10 transistors
¥ other simulators for higher speed, special needs (e.g. SPLICE, RSIM)
■ Limitations:
¥ simulation results provide no insight (e.g. how to increase speed of circuit)
¥ results sometimes wrong (errors in input, effect not modeled in SPICE)
===> always do hand-analysis Þrst and COMPARE RESULTS
■ Statement for MOSFET ... D,G,S,B are node numbers for drain, gate, source,
and bulk terminals
,,
Mname D G S B MODname L= _ W=_ AD= _ AS=_ PD=_ PS=_
,
L
W
AS = W × Ldiff (source) AD = W × Ldiff (drain)
lateral diffusion/ LD LD m
gate-source overlap
I DS = 0 ( V GS ≤ Ð V TH )
KP
I DS = -------- ( W ⁄ L eff )V DS [ 2 ( V GS Ð V TH ) Ð V DS ] ( 1 + LAMBDA ⋅ V DS ) ( 0 ≤ V DS ≤ V GS Ð V TH )
2
KP 2
I DS = -------- ( W ⁄ L eff ) ( V GS Ð V TH ) ( 1 + LAMBDA ⋅ V DS ) ( 0 ≤ V GS Ð V TH ≤ V DS )
2
SPICE includes the ÒsidewallÓ capacitance due to the perimeter of the source and
drain junctions --
n+ drain
(area) (perimeter)
CJ ⋅ AD CJSW ⋅ PD
C BD(V BD) = -------------------------------------------- + ----------------------------------------------------
MJ MJSW
( 1 Ð V BD ⁄ PB ) ( 1 Ð V BD ⁄ PB )
Gate-source and gate-bulk overlap capacitance are speciÞed by CGDO and CGSO
(units: F/m).
The Level 1 model is adequate for channel lengths longer than about 1.5 µm