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The Energy Efficient Photonics

Revolution
John Bowers
Director, Institute for Energy Efficiency

Collaborators
UCSB: Dan Blumenthal, Larry Coldren, Martijn Heck, Jock Bovington, Molly Piels, Yongbo Tang,
Daoxin Dai, Sid Jain, Jon Peters
Intel : Richard Jones, Mike Morse, Yimin Kang, Mario Paniccia, Brian Koch
Aurrion: Eric Hall, Alex Fang, Greg Fish
Hewlett Packard: Di Liang, Marco Fiorentino, Raymond G. Beausoleil

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Institute
Focused of Energy- Research
Solutions Efficiency

Lighting
  A $1 LED light bulb 20x more efficient than an incandescent bulb

Electronics and Photonics


  Wireless and optical technologies for super-high-performance communications

Computing
  A new Moore’s Law for more energy-efficient computing

Buildings and Design


  Economically viable zero net-energy building systems

Production and Storage


  Solar cells with double efficiency at one-tenth the cost

Economics and Policy


  Worldwide energy efficiency policy direction, measurements and standards

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Outline

•  The Problem: Fast growing Internet and increasing


power requirements. Power hungry interconnects
•  The Solution: Highly integrated photonics
•  The low cost solution: Highly integrated photonics
on silicon
•  The Impact: Lower power, higher capacity data
centers, supercomputers, microprocessors.

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Global Data Timeline
Slide Courtesy Intel

A Zetabyte of
2
ZB
 data is
generated in
one year
1.5
ZB
 126 million blogs
234 million websites
1.73 billion web users
1
ZB
 Generated data
90 trillion emails sent
exceeds global Twice as much
storage data generated
than can be
500
EB
 capacity
stored

2007 2008 2009 2010 2011

A Flood of Data is being created at a


60% growth rate – may become more than we can handle!
That Date Needs to be Accessed:
IP Traffic Growth
Internet traffic (exabit/ps 1 Million Tbps)

Internet video to pc

Internet traffic
Cisco forecast
2 dB/year

File sharing
Minnesota
Traffic Study

R. W. Tkach, Bell Labs Tech. J., 2009.

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Source: Cisco VNI June, 2009
Transmission Research records
Space Division Multiplexing
Phase diversity (SDM) starting
started
WDM started PDM started
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Capacity on a single fiber

10
Tb/s

100
Gb/s

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1986 1990 1994 1998 2002 2006 2010

1980: 50 Mbit/s
Plot courtesy of P. Winzer and Chris Doerr
How do we get to Terabit Optical Ethernet?
100G standards being commercialized – 200G and 400G are
next – then onto Terabit

Complex, highly integrated


circuits are needed
Value of Photonic Integration: Size,
Weight and Power Reduction
100 Gb/s Transmit

100 Gb/s Receive

Infinera 100 Gb/s 100 Gb/s


Solution Receive Transmit
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R. Nagarajan, Infinera ECOC 2007
Photonic Integration for Coherent Optics
(PICO)
Coldren, Bowers, Rodwell, Johansson (UCSB),
Goal: Yariv (Caltech), Koch (Lehigh), Campbell (UVA), Ram (MIT)
Create a new generation of photonic integration engines that provide
unprecedented and practical control of optical frequency and phase, driving a
level of sophistication that is routine today for RF into the optical domain.

Ultra-Narrow Δν and
Tunable InP/Si Lasers
& Laser Arrays
Capability

THz-Bandwidth Chirped
Lidar & mmW Sources 256 QAM
1Tb/s Integrated Coherent PICs
Tx/Rx Capacity Epitaxial InP on Si
PICs
st
1 Gen Hybrid InP/Si
Laser Technology 100Gb/s All-Optical
Coherent Regeneration
100Gb/s Integrated
Tx/Rx Capacity 350 GHz fmax HBT
OPLL ASICs
st
1 Gen Optical
Phase-Locked Loops
QPSK Coherent
PICs

2009 2010 2011 2012 2013 2014


Ethernet Rx
LIDAR
Terabit Optical Ethernet Center
Blumenthal, Bowers, Coldren, Rodwell
•  Mission Statement:
–  To lead the way in a new roadmap for multi Tbps Optical Ethernet
–  Create new energy efficient photonic integrated technologies

2015 2020
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Monolithic Integration
S. C. Nicholes, et al.

Switch + diagnostic elements UCSB


PLSI MOTOR

Switch elements
Why Silicon Photonics?
Utilize advanced fabrication technologies for low cost, high volume integrated photonics.
The Solution: Optical Interconnects
•  3D layer stacking will be
prevalent in the 22nm
timeframe

al I/O
•  Intra-chip optics can take
advantage of this

Optic
BUT: Silicon is reciprocal. How to make an isolator?

affic
technology

ptical tr
•  Photonics layer (with
BUT: SiO2 is thermally
supporting electrical resistive. So, power dissipation of
active circuits)
devices moreis a problem, particularly for rings and DWDM
easily

o
signa ical

On-chip
integrated with high

ip opt
performance logic and

ls
BUT: Silicon is centrosymmetric (not
memory layers electro-optic)!
Photonic
Off-ch Plane
Memory Plane
So, • how to can
Layers integrate modulators?
be separately Logic Plane
optimized for performance
and yield
BUT: Silicon has an indirect gap and is a Kash,
poor absorber
“Photonics (not
in Supercomputing:

1.55 µm)! So, what about photodetectors?


the Road to Exascale,” IPNRA, 2009

BUT: Silicon has an indirect gap and doesn’t emit light!


So, how to integrate sources?
Bringing Si Manufacturing to the Laser

Lasers Si Manufacturing

OPTICAL
ANYWHERE,
INCREDIBLE
Very high High volume, POTENTIAL
bandwidth low cost

Long distances
InP Highly Silicon
Photonic integrated Photonic
Immunity Integrated
to Six Generations
Integrated
electrical noise
circuits Scalability circuits
Year
of
Production 1995 1998 2001 2004 2007 2010 2013 2016
DRAM
1/2
Pitch
(nm) 270 190 130 90 65 43 32 22
Wafer
Size
(mm) 150 200 200 200 300 Courtesy:
300 300
Rattner 450
(Intel)
Hybrid Silicon Photonics

Direct Gap III-V III-V active region


InGaAlAs

Silicon Silicon rib waveguide on


SOI wafer

–  Optical gain from III-V Material


–  Efficient coupling to silicon passive photonic devices
–  No bonding alignment necessary: suitable for high volume CMOS
–  All back end processing low temperature (<350 C)

7 lasers operating c.w.


simultaneously
Alex Fang’s Thesis 15
Silicon Evanescent DFB Lasers

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Arrays of 16 DFBs with Electroabsorption
Modulators and Photodetectors

Laser A EAM
bandgap bandgap

Laser B
bandgap EAM
bandgap
8 Integrated
PD-DFB-EAM
16 DFB/PD
laser array

ISLC 2010, Kyoto , Japan


WA3 9.15 - 9.30 Integrated Broadband Hybrid Silicon DFB Laser Array using Quantum Well Intermixing17
Hybrid Silicon Microring Laser: Path to low
threshold and low power

III-V

Si

10 mA, 1 V =10 mW
0.4 pJ/bit
25 Gbit/s

D. Liang, et al. Optics Express , 17 ( 22 ), 20355-20364 , October 23 , 2009


TW-EAM Structure
 Small Footprint: 240 x 430μm
 Large bandwidth: 42 GHz

240µ
1

m
E/O response [dB]

0
-1
430µm
-2
-3
-4 42GHz
-5
-6
0 10 Frequency
20 [GHz]
30 40 50

Bitrate:50 Gb/s
ER: 9.8 dB
Vpp: 2 V 20ps

Tang et al. OFC 2011


Rattner, IPR Plenary,
Postdeadline (2010) 20
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Rattner, IPR 2010
Next Generation Optical USB
Every computer, SAN, Display,…
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Rattner, IPR 2010
Other Essential Elements

•  Optical amplifiers
•  Photodetectors
•  Modulators
•  Beam splitters
•  Arrayed waveguide routers
8 AMPs 8 detectors
•  Polarization rotators
•  Coherent receivers
have all been demonstrated in the hybrid silicon
platform.

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H. Park et al., PTL, 19(4), 230, February (2007).
State-of-the Art Electronic IP Router
•  Problem: Bandwidth demands scaling faster than both silicon and
cooling technologies
Maximum configuration for CRS-1  92 Tbps (80 racks)

~1 Megawatt!!!

*Courtesy of Steve Nicholes


UCSB LASOR:
a Label Switched Optical Router

D. J. Blumenthal,
Director, LASOR
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LASOR PIC Technologies
MOTOR
Optical Buffers

M. J. R. Heck et al., "Integrated Recirculating Optical


Buffers," in SPIE Photonics West 2010, Proc., CA, 2010.

Packet Forwarding Chip

“An 8x8 InP Monolithic Tunable Optical Router (MOTOR) Packet Forwarding
Chip,” S. C. Nicholes, et. al., IEEE JLT, Special Issue on OFC, (2009)
(Invited).

CAM All-Photonic Wavelength Converter

Vikrant Lal, et. al., "Monolithic Wavelength Converters for High-Speed


Packet-Switched Optical Networks," Selected Topics in Quantum Electronics, Tauke-Pedretti, A., et. al., "Separate Absorption and Modulation Mach-
IEEE Journal of , vol.13, no.1, pp.49-57, Jan.-feb. 2007 Zehnder Wavelength Converter," Lightwave Technology, Journal of , vol.26,
no.1, pp.91-98, Jan.1, 2008
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International Symposium on Ultra-high Capacity Optical Communication and Related Optical
Signal Processing and Devices Technical University of Denmark, Lyngby, Sept. 16 – 17, 2010
iPhoD at UCSB (Blumenthal, Bowers)

iPhod = Fiber Like Losses on Chip -> 10x, 100x, 1000x reduction over today’s losses
Si3N4 waveguides on Si platform

20 meter spiral delay line

3 cm

Q of >10 million. 30 MHz linewidth


Data Centers:
Higher Capacity switching
Smaller size, weight and power

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Network Interface Rate

100 Gbit/s Interfaces


are available.
100 Gbit/s switching
does not exist yet.

*Courtesy of R. W. Tkach,
OIDA Annual Forum 2009
Power Savings
1.E+03
Energy
per
bit
(nJ) 1.E+02
1.E+01
1.E+00
1.E‐01
1.E‐02
1.E‐03
1.E‐04
Fast
Optical
 Fast
 Ethernet
 Core
Router PON
ONU IPTV
Server
Switch Electrical
 Switch
Switch

•  Eliminating the OEO conversion and eliminating the


electronic switch reduces power and scales to higher
capacity.
•  Power dominated by optical amplifiers (to make up for
loss) and FPGA controller
Trends in Switching and HPC

•  Port speeds increasing rapidly


–  1Tb/s coming in near term
•  Fabric radix increasing
–  Fibers connecting more nodes
 At 1Tb/s line speed and 100’s of nodes, 100Tb/s
system needed
  Fibers connecting boards.
  Moving to fibers connecting chips...
  Switching is critical...
Novel Vertical-Cavity Surface-Emitting Lasers (VCSELs)
Coldren

State-of-the-Art diode VCSEL Field-Induced Charge-


•  25 and 35 Gbit/s
Separation Laser
•  50 and 100 Gbit/s?

SiN sidewall gate pad

gate contact
BCB

n-DBR
oxide channel contact
aperture
injector active channel
pad region pad
p-DBR

i-DBR

AR coating semi-insulating GaAs substrate

18 0.7
DC and RF
Frequency response (dB)

0.35 35 Gb/s
12 1.0 5 1
measurement

Diode voltage, Vpn ( V)

Light output ( mW)


0V 20
5 ! m @ 2 0 ⁰C

~ 11GHz
15
f 3 dB ~ 1 1 G H z

1.75 -1V
10

6 3.0

Response (dB)
5

4 -2V
0

-5 0.8
4.4
Ibia s = 4 m A
-1 0

0
-1 5 V ga t e = 0 V

-3V -2 0
0 5 10
F re q ue nc y(G H z )
15

3 -4V 0.6
-6
Vgate
-12 2 0.4
o
-18 3 µm @ 20 C Channel

1 Vgate Vpn
0.2
0 5 10 15 20 Gate
FICSL I bias

Frequency (GHz) Injector

0 0
0 1 2 3 4
Bias current, I bias (mA)
PetaFlop System

3 4 ... 128 die/box


2 5 4 CPU/die
16
1
17
64
ALL-OPTICAL
SWITCH 18
63 ...
...
49 32
48 ... Multi-Die
33 Multi-Processor
47
I/O 46
10 meters= 50 NS Delay LAN/WAN
s.j.wallach.super2000.11.2000
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High Performance Computing Scaling
enabled by Optical Interconnects

10 Peta- OI at ~100 fJ/bit*


FLOPS “Peta-FLOPS in
a rack”

1 Peta-
FLOPS OI at ~1 pJ/bit
Computational Throughput

100
TFLOPS

HPC performance space


10 expanded by Chip-to-Chip
TFLOPS
Optical Interconnects
electrical inter-chip
interconnect barrier
1 overcome by OI
TFLOPS

100
GFLOPS
10 MW 1 MW 100 kW 10 kW 1 kW
Power Consumption *D. A. B. Miller, IEEE Proc., 2009

100 x lower power!


Summary

•  Photonics provides lower power, more efficient ways


to communicate—on a wide area, local area, and
within data centers and supercomputers.
•  Integration is essential for size, weight, power and
cost reduction and improved yield and reliability
•  Hybrid silicon photonics can integrate this
technology with CMOS.

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