Advanced Mixed Signal Design using

CMOS Current Mode Logic Gates

School of Electrical Sciences, VIT University

Lokesh. B
P. Jayakrishnan
S. Chatterjee
Canvas Conversations

Presented at
 Advanced Mixed Signal Design using CMOS Current Mode Logic
Gates
1
Lokesh.B , P. Jayakrishnan, and S. Chatterjee
School of Electrical Sciences, VIT University, 632014, TN, India
1
lokeshb@vit.ac.in

Abstract accurate high-speed mixed signal application [3], [5-8].

CMOS current-mode logic (CCML) circuits have received
intensive attention due to its promising application in mixed-
signal circuits. CCML offers high-speed performance
competitive with CMOS while potentially reducing the supply
switching noise and keeping power consumption acceptably
low. CCML gates are implemented in mixed-signal systems due
to its high precision, Small switching noise for neighboring
analog circuitry, high-speed cross point switches for network
(LAN / WAN) applications, more power efficient than CMOS
at high speed operation, etc.
This session will address the following: The performance of
CCML gates as a function of design parameters such as
comparison with 0.18 to 0.25 µm CMOS technology node and
the applications of CCML in conventional mixed-signal
circuits.
The design is based on TSMC 0.18 and 0.25 µm CMOS
technology node using cadence Virtuoso spectre circuit
simulator. The propagation delay can be improved using the
proposed CCML design with 0.18 µm technology as it reduced
the gate delay to increase the speed over 0.25 µm CMOS
Technology node. As an example, the propagation delay of
conventional NOR is showing 169.84 pS, where as the proposed
CCML NOR is showing 42 pS.
A high speed phase locked loop (PLL) with speed improvement
can be designed using CCML gates. Since the desirable features
come at the cost of static power consumption, the power-delay
trade-off is a crucial design aspect in the CCML logic style.
Compared to conventional CMOS logic, MCML dissipates
constant static power and requires techniques more
analogous to analog design. However, MCML requires
smaller dynamic power than that of the conventional logic
because of the smaller output swings. The reduced output
swing and faster switching makes MCML a promising
candidate for certain mixed-signal applications [9-12]. The
constant supply currents, lower cross talk between the analog
and the digital circuits of MCML improves the accuracy of
mixed-mode systems. Additional efficiency can be obtained
using more than one level of logic.
The aim of the paper is to reduce the Propagation delay of
the proposed new CMOS current mode logic for a high
speed phase locked loop with speed improvement over
conventional CMOS
2. CMOS Current Mode Logic Operation
The operation of an MCML gate is shown in the figure
1[14]. It consists of a load resistor RL . A differential pull-
down network (PDN) with complementary sets of inputs and
outputs and a constant source ICs.

1. Introduction

Conventional pull-up PMOS, pull-down NMOS static logic

is popular because of its convenient availability in standard
library cells, small area usage, low power dissipation, and
high noise margins [1]. Ideally The static power
consumption of the conventional CMOS logic gate is zero,
however dynamically it generates a large current pulse
owing from the power supply to the ground during the state
transition. The coupling of the high switching spike noise
may cause cross talk between the analog and the digital
circuitry. Even worse, the switching noise might induce latch
up, which can possibly destroy devices in a integrated circuit
due to overheating [2-3].
MOS Current mode logic (MCML) is widely used logic
style for high-speed circuits. This type of logic was first
implemented using bipolar transistors [4] and extended for
application with MOS transistors. MOS current mode logic
(MCML) circuits with constant bias currents are intended for
Figure1: Basic structure of CCML Gate
The differential inputs (complementary sets) are applied to
the pull down network (PDN). The PDN has a tree–like
differential structure, similar to differential cascode voltage
switch (DCVS) family [15]. The output and its complement
are available at the two arms as indicated in the figure. The
PDN is grounded through a constant current source ICS,
which is usually an NMOS transistor. The voltage swing at
the output and its complement is V = ICSRL and is
controlled by setting the value of the current source ICS and

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the effective value of RL, which is usually a PMOS
transistor. The voltage swing is in the range of a few
hundred mV and is a crucial leverage factor in high-speed
MCML gate design. Every MCML gate has two bias
voltages, RFP and RFN. The value of RFP is set to achieve
the desired load resistance. The value of the load resistance
can also be controlled by the dimensions of the PMOS
transistor. RFN biases the current source transistor and
helps in fixing the desired current. The width of the current
source transistor is usually large to make the transistor
robust, to decrease the mismatch effects, and to enable a
future reduction in VDD [16].
The equations for the total propagation delay, power
dissipation, and the power delay product of a CCML logic
circuit and its CMOS counter part are shown in Table 1.

Table 1: performance of CCML and its CMOS counterpart

MCML Logic Style Conventional

Parameter CMOS Logic
MCML = CL CMOS=CL DD N
Propagation --------------- ---------------
Delay( ) ISC /2 DD-
Vt)2

Power (b)
Dissipated PDMCML=VDD ISC PDCMOS=N CL Fig 2: Basic logic gates: (a) Conventional NOR (b) CCML
VDD2 f AND/NAND/OR/NOR logic gate

Power Delay PDPMCML=N2 CL PDPCMOS=N L 3.1. Inverter

Product(PDP)
DD
Circuit varies linearly with voltage swing V and is
independent of the supply voltage VDD, in contrast to
conventional CMOS logic circuits. The power dissipation of
a CCML logic circuit varies linearly with the supply VDD
and is independent of the operating frequency, whereas
power dissipation of conventional CMOS circuits depends
linearly on operating frequency and has a square-law
dependence on supply voltage. Since the delay of an CCML
gate depends linearly with V and is independent of Supply
VDD, the delay can be effectively minimized by lowing the
voltage swing V, while maintaining the supply voltage. For
in-depth comparison between CCML and CMOS logic
styles, the reader is referred to [14].
2
The CCML Inverter is made using an NMOS current mirror,
using a PMOS current source connected to the diode-
connected NMOS. For this structure, the presence of current
is logic “1”. When IN is high, the current from the PMOS
transistor will flow through that branch, leaving no current to
go through the mirror. This will effectively turn off the
mirror network and OUT will be low. However, depending
on the current going through the PMOS, the leakage current
of the mirror network, when it is turned off, can become a
factor and produce errors in computation [13].

3. CCML CIRCUITS
The operation of CCML logic circuits is based on the
steering of constant current similar to the “differential pair”
used in the analog circuit’s fig: 2 show the structure of
conventional NOR and a CCML AND/NAND/OR/NOR
gate. Device scaling is typically selected as small as possible
with the constraint that sufficient swing noise and noise
margins are produced by the circuit.
Fig. 3: CCML Inverter

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 4. SIMULATION AND RESULTS frequency detector. Since D-input is logically connected
high, it was possible to remove the input and incorporate the
The design is based on TSMC 0.18 and 0.25µm CMOS logic into the circuit. The resulting flip-flop, initially
technology node using cadence Virtuoso spectre because suggested by Razavi [17], is comprised of a series of
CADENCE tool has been widely used and good cross -coupled OR gates.
experimental correlation for gate delays have been achieved
the confidence level in the simulation is high. The
propagation delay can be improved using the proposed
CCML design with both 0.18 and 0.25 µm technology

TABLE 2: LOGIC GATES PROPAGATION DELAY

COMPARISON

Gates Delay for Delay for

0.18µm 0.25µm
Conventional 39ps 169ps
NOR
Conventional 89ps 190ps
OR
CCML NOR 19ps 42ps
CCML OR 14ps 33ps

5. (A) APPLICAION EXAMPLE

The phase detector is a key element in a Phase Locked

Loop system .The use of CCML gates may be used in the
implementation of Phase/Frequency Detector for use in a
charge pump based phase locked loop such as shown in
figure 4 [5], [9]. An early arriving pulse activates “Pup” that
increases the frequency of the VCO input FVCO while a late
arriving data pulse activates the Pdn that decreases the
frequency of FVCO. Fig 5: Schematic of the Phase/Frequency Detector D-Flip-
flop

5. (B) SIMULATION AND RESULTS

The performance of a PLL system is ultimately determined

Fig 4: Charge pump phase detector for PLL
As shown in the figure 4, the phase /frequency detector
edges in the two input signals by connecting them to the
clock inputs of two flip-flops. These flip flops have their D
inputs high, and require an asynchronous reset signal for the
proper operation of the circuit. Figure5 shows the rising-
edge sensitive, resettable D-Flip-flop used in the phase
by the ability of the phase detector to respond to incoming
data with a short delay time [9]. To compare the behavior of
the phase detector built on the CCML and CMOS AND
gates, the respective results are tabulated in table 3 and table
4. The error term € is defined as € = (tdi-tdo)/tdi. tdi is the
input delay representing the time delay between the two
inputs Fref−FVCO. Tdo is the resolution width representing the
difference between the pulses width of the Pup and Pdn
measured at the midpoint of the input swing. The CMOS
logic implementation provides a phase resolution of 1.2
degrees, while the CCML provides 0.25 degrees of
resolution, both measured at 400 MHz with the error
tolerance about 10%. With a propagation delay
improvement of about 200% using the current mode nor
gate over the CMOS nor gate, the corresponding MCML
phase detector gains the resolution degree improvement of
480% over the CMOS phase detector. Besides the slower

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propagation delay compared to that of CCML the
conventional logic doesn’t have the dynamic symmetry in
AND gate because of one connection is dynamically faster
than the other connection due to the asymmetric circuit
configuration shown in Fig. 2(a). As shown in Table 3, the
resolution widths of the conventional logic phase detector in
the situation when Fr e f is ahead or behind of Fv c o are
Unbalanced. On the other hand, the CCML phase detector has
the dynamic symmetry because of the balanced architecture of
the basic NOR /NAND/AND/OR cell as shown in Fig. 2(b).

Table 3: CONVENTIONAL LOGIC PHASE DETECTOR

RESOLUTION
Fig7; PFD Simulation Results (for different frequencies)
Input Delay (ps) 100 50 25 10
(Fref is earlier than
Fvco resolution IV. Conclusions and Proposals
width ps) 98.815 47.256 21.173 6.078
€% 1.19 5.49 13.15 39.2 Based on our simulation results, if CCML is used in a high
(Fref is later than frequency, high performance task, it has an advantage over
Fvco resolution static CMOS.
width ps) 106.93 55.87 29.53 13.87 In these preliminary tests, we used ideal current sources
€% -6.93 -11.74 -18.12 -38.7 whenever they were drawn that way in the figures. These
will have to later be replaced by MOS current sources. We
Table 4: CCML LOGIC PHASE DETECTOR believe this will actually help, because MOS current sources
RESOLUTION themselves have leakage current, whereas ideal current
sources do not. Biasing is another concern with the circuits.
Input Delay (ps) 100 50 25 10 As lower voltage and currents are applied, the precision of
(Fref is earlier than the bias voltage becomes ever more important. It will clearly
Fvco resolution have a great effect as the smaller transistors are used.
width ps) 103.15 52.5 25.873 10.673 In the future, we plan to run tests with the 90nm models.
€% -3.15 -5.00 -3.492 -6.73 The results in this regime are normally less predictable, but
(Fref is later than we hope that we can develop logic that can be properly
Fvco resolution computable. We will combine the implemented building
width ps) 102.2 51.82 26.23 10.45 blocks into larger modules and chains and eventually into a
€% -2.2 -3.64 -4.92 -4.5 larger structure such as an adder. It will be first made in
layout, with the netlist extracted from it. CCML gates are
implemented in mixed-signal systems due to its high
The schematic indicated in figure 4 was simulated in
precision, Small switching noise for neighboring analog
cadence using spectre simulation tool. Figure 6 shows the
circuitry, high-speed cross point switches for network (LAN
resulting waveforms for the case when the frequencies are
/ WAN) applications, more power efficient than CMOS at
equal, and figure 7 shows the results for different frequinces
high speed operation, etc. The proposed gates may be easily
integrated with conventional CMOS logic with minimal
interface problems

V. References

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Fig.6 PFD Simulation Results (Equal frequencies)
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no. 8, pp. 25.2/1–25.2/4, May 1991.

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