ANALOG & POWER
An introduction to clock
distribution circuits
By Alexander Pakosta, Texas Instruments
This article describes the main
types of clock distribution and
discusses two of the most
important parameters
characterizing their operation,
jitter and skew.
I Consumer electronics, including devices such
as DVD recorders, personal computers, note-
books and HDTV have been the subject of dra-
matic increases in functionality and perform-
ance over the past few years. During the same
time there have been progressive reductions in
cost to the point where most of us now regard
such devices as standard household equipment.
This trend is being replicated in other areas like
mobile communications and the worldwide
web, where bandwidth and speeds are increas-
ing all the time. This is opening up new media
opportunities such as downloading videos
onto a mobile phone or watching HDTV
movies from the internet.
A lot of data processing is necessary to imple-
ment all these modern requirements, resulting
in the use of powerful digital processors and
other similar ICs, and clock distribution circuits
are one of the keys to ensuring that the best per-
formance and cost-effectiveness is achieved.
Since each processor in these applications uti-
lizes synchronized logic, it means that the
speed of every component needs to be dictated
by a central system clock.
This contrasts with the situation in years gone
by when only a few clocks with lower frequen-
cies were necessary. Nowadays, with higher sys-
tem performance and increased processor
speeds, the need to create, distribute and refresh
February 2008
the system clock is becoming ever more critical.
Thankfully, however, a whole family of high-
performance, cost-effective clock distribution
circuits (CDCs) is available today, which main-
tains different tasks and allows complex clock-
ing structures to be established.
CDCs are split into three main groups: clock
synthesizers, which are ICs that generate clocks
in a system; clock buffers, which distribute
clocks; and jitter cleaners, which refresh clocks
where needed in the system. Sometimes the
functionality of CDCs is integrated in more
complex ICs, or partly in the processor itself.
For high performance, or more complex clock-
ing structures, however, there is no way round
using dedicated clocking ICs. Dedicated clock-
ing ICs usually deliver better performance and
more flexibility than integrated solutions. The
following is a brief introduction to the most im-
portant CDCs and their uses.
Typically, the clock synthesizer provides the
starting point for a system clock, especially in
consumer electronics such as gaming consoles,
IP set-top boxes and the like, where general-
purpose clock synthesizers are being used in-
creasingly as the central clock source because
they can provide a more cost-effective solution
than a number of crystals and simple crystal os-
cillators sited around the system. Clock synthe-
sizers basically consist of an external crystal and
36
Figure 1. Block diagram of
a general-purpose clock
synthesizer
an oscillator circuit. The crystal normally pro-
vides the frequency reference point, usually in
the 8-32MHz range (27MHz is the standard for
current video applications for example), and al-
lows stable and accurate oscillation of the os-
cillator circuit. As a rule, additional phase-locked
loops (PLLs) are used to allow easy multiplica-
tion or division of the oscillator frequency. With
this ability, many different frequencies can be
derived from a single low-frequency crystal os-
cillator such as the CDCE949 from Texas In-
struments for example, which generates up to
nine different output frequencies. These fre-
quencies can be chosen virtually freely from val-
ues between a few hundred kHz up to 230MHz,
and in very high resolution. Figure 1 illustrates
a general-purpose clock synthesizer.
Clock buffers distribute and copy a clock signal
from one input to several outputs. The con-
version between different supply voltage levels
(e.g. 3.3V to 1.8V), or between different sig-
naling standards (e.g. single ended to differen-
tial ended) can be handled through this kind of
IC. Important signaling standards are LVCMOS
(single ended), LVPECL and LVDS (differential
ended). Buffers are frequently used in memory
applications like the double data rate (DDR)
RAM memory in PCs, notebooks and servers.
A general-purpose clock buffer is illustrated in
figure 2. Modern clock buffers often have a
built-in PLL that allows the phase of the output

Figure 2. Block diagram of a general-purpose
clock buffer
clocks to be adjusted with reference to the input
clock. It is important that all outputs switch at
the same time, which means that the phase dis-
placement between the outputs (skew) should
be minimized.
Jitter is an unwanted phase displacement of the
real clock in reference to an ideal clock. If a
clock is sent across a printed circuit board
(PCB), noise is added, which creates jitter
compared to the clock at the source that is the
clock synthesizer. Some system components like
analog-to-digital converters (ADCs), serializ-
er/deserializers (SerDes), or digital signal
processors (DSPs) however, require a very ac-
curate clock with almost no jitter. If such sen-
sitive components are located a long way from
the clock synthesizer, or, the clock synthesizer
does not offer a clock that is clean enough, then
a jitter cleaner can be used to remove the phase
displacement with the help of a PLL and high
performance LC or crystal oscillator. A jitter
cleaner is illustrated in figure 3.
There are several important parameters that
allow the performance of a clock distribution
circuit to be judged, jitter being one of the most
Figure 3. Block diagram of a jitter cleaner
important since it effectively illustrates the qual-
ity of the clock. Furthermore, the higher speed
and higher performance of systems nowadays
demand more stringent jitter control for oper-
ation than those from the past. It can be seen
therefore that one of most challenging tasks in
the design of a clock structure is not only to
find a cost-effective solution, but to manage jit-
ter in order that proper system operation is
maintained. There are a number of ways to de-
fine and measure jitter and the following are
most important.
Cycle-to-cycle jitter is the difference between
the periods of two adjacent clock cycles. It is
important for asynchronous data transfer,
where the receiver gets the period time of the
transferred data bits from a start bit. Period jit-
ter is the difference between the current period
of a clock signal and its ideal period. Usually
this parameter is given in picoseconds and
measured over several thousand cycles. Period
jitter is in effect important to maintain setup
and hold times for digital logic. Higher oper-
ating frequencies of digital logic reduce the
margin for setup and hold times and lead to
more and more stringent period jitter require-
ments. Phase jitter is the difference in phase be-
tween a real clock and an ideal clock. It is usu-
ally determined by measuring the difference be-
tween the rising edge of a real clock and the re-
lated rising edge of an ideal clock. Phase jitter
37
ANALOG & POWER
and period jitter are related. If the period jitter
of each cycle is added up, the result is the phase
jitter of the clock signal. Phase jitter is impor-
tant for serial data transfer - if it is too big, bit
failures might occur during data recovery from
the serial data stream.
All outputs from a clock distribution circuit
should ideally switch simultaneously. In reali-
ty, however, this is not possible and there is a
consequent delay in switching between differ-
ent outputs. Skew describes this difference
and is therefore a second important parameter
to characterize the performance of a clock dis-
tribution circuit. Skew is very important for
synchronous applications such as memory, in
which several chips need to get the clock at the
same time in order to capture data properly.
Skew is usually defined as the propagation delay
difference between various outputs. Every ris-
ing or falling edge at the clock distribution cir-
cuit input takes time to get from the input to
the output. This time can vary depending on
the chip, the path of the clock through the chip
and the type of edge (rising or falling). This
variation causes the outputs of a CDC to
switch at slightly different points in time. Skew
should therefore be kept to a minimum if
switching of clock outputs is to be synchro-
nized. The following describes some of the dif-
ferent types of skew.
Output skew is the propagation delay difference
between any two outputs of the same device at
identical transitions (rising or falling edge).
Part-to-part skew describes the propagation
delay difference between two devices of the
same type. Usually part-to-part skew is defined
at specified outputs and under identical con-
ditions like the same input signal, supply volt-
age, ambient temperature, load, package and so
on. The difference between propagation delay
times tPHL and tPLH when one input drives
one or more simultaneously switching outputs
is called pulse skew. Pulse skew quantifies the
duty cycle characteristics of a clock buffer. I
February 2008