NANOWIRE JUNCTIONLESS TRANSISTORS

A Literature review submitted in partial fulfillment of the requirement for the degree of
Master 2 (Research): Micro & Nanoelectronics

By:
PIRZADO Azhar Ali Ayaz

Under the Supervision of:

Dr. Fabien Prégaldiny

University of Strasbourg, Strasbourg, France

FEBRUARY, 2011
ii
 ACKNOWLEDGEMENTS

I wish to express my sincere gratitude to my supervisor Dr. Fabien Prégaldiny for his
invaluable guidance and advice during every stage of this endeavor. I am greatly
indebted to him for his continuing encouragement and support without which, it
would not have been possible for me to complete this undertaking successfully. His
insightful comments and suggestions have continually helped me to improve my
understanding.

I thank Dr. Daniel Mathiot and Dr. Pattrick Leveque (InESS, CNRS) for their
discussion, encouragement and advice in the beginning of this work.

My special thanks to my parents and friends who were always there for me, to
constantly encourage and appreciate for the completion of this task.

To my beloved Jeena Khan, whose love always inspired me and taught me how to live
and strengthen my belief in my abilities.

PIRZADO Azhar Ali Ayaz

University of Strasbourg, France

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 ABSTRACT

This paper attempts to study and review the Nanowire Junctionless transistors
(JNTs). We attempt to increase the predictive understanding of the device structure,
nature, operation characteristics and fabrication process by reviewing the literature.
Some comparisons with Bulk MOSFET and SOI-based Multi-gate FETs (MuGFETS)
are presented in order to analyse the performance of Junctionless transistors.
Finally, its suitability for Short-Channel Nanowire Junctionless Transistor design and
operations is assessed.

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 TABLE OF CONTENTS

ACKNOWLEDGEMENTS..........................................................................................iii
ABSTRACT...............................................................................................................iv
TABLE OF CONTENTS..............................................................................................v
LIST OF ILLUSTRATIONS...................................................................................... ..vi

REVIEW OF SILICON NANOWIRE JUNCTIONLESS TRANSISTORS…........................1

1. INTRODUCTION..............................................................................................1
1.1. Motivation for Present Research ...................... ...........................................1
1.2. From Junctions to no junctions….…………………………………………………….2
1.3. Nature and Structure of Junctionless Nanowire Transistor...........................4
1.4. The Characteristics of Junctionless Nanowire Transistor..….........................7

2. RECENT RESEARCH RELEVANT TO THE JUNCTIONLESS DEVICES:

COMPARISONS AND ISSUES…………………………….…………………………….10

3. SUBTHRESHOLD SLOPE (SS) AND DRAIN-INDUCED BARRIER

LOWERING (DIBL) IN JUNCTIONLESS NANOWIRE TRANSISTOR..……...…….16

4. FABRICATION PROCESS OF THE JUNCTIONLESS NANOWIRE TRANSISTOR

OR GATED-RESISTOR……………………………………………………..……….…………17

5. POTENTIAL FOR SCALING ……………………………………………………..………..19

6. CONCLUSION................................................................................................22

7. Appendix: Permission(S)................................................................................23

8. References.....................................................................................................24

v
 LIST OF ILLUSTRATIONS

No. TITLE OF FIGURE PAGE

Fig.1: The schematic of n-channel Nanowire Junctionless Transistor. 05
Fig.2: Schematic of JNT with Transmission Electron Microscope (TEM) 06
Image of the transistor structure.
Fig.3: Cross section of N-Channel gated-resistor (A) and P-channel gated- 06
resistor (B) of Gated-resistor or JNT.
Fig.4: Conduction under different values of Gate Voltage (VG). 07
Fig.5: Gated-resistor under different values of Drain voltage(V D). 08
Fig.6: Cross section of Nanowire and concept of electrostatic depletion of 08
the channel by squeezing of pipe analogy.
Fig.7: Measured ID versus VG of N-and P-channel Junctionless transistors. 09
Fig.8: Output characteristics. ID as function of VD for different values of V G: 09
n-channel gated resistor (a) and a p-channel gated resistor (b).
Fig.9: Bulk MOSFET with junctions (a) & SOI Junnctionless transistor (b). 10
Fig.10: Evolution of SOI devices . 11
Fig.11: Doping in Short-channel and Ultra-short Channels. MOS doping (a), 11
JNT doping (b).
Fig.12: Comparison of intrinsic delay time in Bulk MOS and Gated- 14
resistors. Comparison of different doping concentrations in gated-
resistors is also shown.
Fig.13: Experimental ID–VG characteristics of (a) GAA inversion-mode 14
transistors and (b) GAA junctionless transistors with various Wsi
values (6, 10, and 13 nm) at VD of 0.05 and 1V. The doping
concentration of each device is shown in the inset of the graph. (c)
Cumulative distribution of VT in GAA inversion-mode and
junctionless transistors.
Fig.14: Schematics of the simulated devices. (a) Inversion-mode transistor. 15
(b) Junctionless transistor. (c) VT fluctuation according to various
Wsi’s in inversion-mode and junctionless transistors as a parameter
of doping concentration.
Fig.15: ID saturation in JNTs with WSi = TSi and L=25 nm, Tox =1nm and a 15
poly+ polygate is used. VDD =1V and Ioff=100nA/um (a), ID saturation
in JNTs with TSi= 2xWSi and L=25 nm, Tox =1nm and a poly+
polygate is used. VDD =1V and Ioff=100nA/um (b).
Fig.16: Transmission electron micrograph of silicon gated resistor 17
nanoribbons. (a) Five parallel devices with a common polysilicon
gate electrode. (b) Magnification of a single nanoribbon device.
Fig.17: Transmission electron micrograph of silicon gated resistor 18
nanoribbons. Five parallel devices with a common polysilicon gate
electrode (a). Magnification of a single nanoribbon device (b).
Individual atomic rows can be seen in the silicon.
Fig.18 The structure, geometry and cross section of short-channel 20
Junctionless transistors. A 3 nm gate device structure (a), cross

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 section of Si NW (b) TEM micrograph of cross-section pi (п) gate
gated-resistor (c).
Fig.19 Different effective gate lengths in: a junctionless transistor in the off 20
state (a), a junctionless transistor in the on state (b), an inversion-
mode transistor(c).
Fig.20 The electrical characteristics of 50nm JNT: Drain Current (ID) as 21
function of Gate voltage (VG) (a), Subthreshold Slope (SS) versus
Gate voltage VG (b).

Fig.21 The out put (ID - VDS) characteristic for SiNW junctionless transistor 22
dimensions shown in fig. 18 (a). n-type JNT doped by As impurity
atoms (a), p-type JNT doped by Ga impurity atoms (b)

vii
REVIEW OF SILICON NANOWIRE JUNCTIONLESS TRANSISTORS

1. INTRODUCTION

1.1. MOTIVATION FOR PRESENT RESEARCH

Silicon (Si) Complementary Metal-Oxide Semiconductor

devices/technology has reached to its intrinsic material and technological
limits. The scaling challenges to Integrated Circuit (IC) technology based
upon the rigid Silicon, have provided the necessary impetus and impulse
to find solutions to miniaturization of Silicon-based devices by both
alternative methods and improving present state-of-the-art. The potential
problems which act as barriers to the to scaling are: 1) Device problems:
short-channel effects, leakage current, MOS capacitance, parasitic
resistance of Source and Drain junctions, doping concentrations and 2)
technological barriers: patterning with conventional optical lithography,
precise control of doping at affordable costs [1,3].

With the ever-increasing demand for scaling MOS devices and increasing
the integration density of MOS devices beyond Very Large Scale Integration
technology has led microelectronics research to cross the boundary from
micro (micrometer= 1 millionth of a meter, 10-6) to nano (nanometer= 1
billionth of a meter, 10-9) dimensions. Latest developments in Nanoscale
technologies and hybrid approaches to solve scientific and engineering
problems based on the Bottom-up and old Top-down have brought to the
attention many novel materials, properties, and devices and hence opened
the doors to solve various existing scientific problems in almost all fields of
science, engineering and technology [2].

The modern trends in electronics and nanotechnology, highlight problems

in better context and provide the impetus and substance for developing
new devices and systems with i) novel properties ii) improving the existing
technologies and sciences. Although new materials are continually being
developed, much progress is being made by combining materials in devices
through a “systems approach”. In such an approach, materials are chosen
to function in concert to achieve maximal device performance. In this
context, tuning the electronic and chemical properties of the interfaces,
both organic–organic and organic–inorganic, has turned out to be a key
ingredient in device performance optimisation [2].

Future miniaturization of electronic devices to keep the Moore’s law

relevant to microelectronics industry mainly relying upon silicon, are
expected to bring about new, ingenious methods to implement precisely
controlled and highly functional nanoscale components synthesized by
inexpensive chemistry as opposed to conventional lithography techniques.
Integrated Chip design technology is researched extensively to take

1
alternate routes based on self-assembly and molecular transport. New
architectures would enhance performance and packing density by orders
of magnitude, improve the functional complexity of Integrated Circuits
(ICs), and operate at higher switching speeds. Nanometer scale devices and
organic molecules are investigated for unique possibilities such as
extremely low power dissipation, quantum effects, surface sensitivity and
low synthesis cost. The building blocks for future electronics, rooted in
nanoscale science, would aid in the continued advancement of integrated
circuit technology [2].

Planner architecture of conventional CMOS lacks the capacity to further

shrink the dimensions of device without sacrificing the performance. Non-
conventional architectures with performance comparable to the planner
devices have been demonstrated by various research groups and silicon
industry leaders in recent years. The devices are based upon double and
triple-gate structures and are designed to provide solution to scaling limits
of bulk CMOS [3,4,5].

Double-Gate, Thin-film Transistors, Single Electron Transistors, have been

reported in the literature with device functionality matching that of best
CMOS devices. Carbon Nanotubes and Nanowires of different elements
such as; Silicon, Carbon, Gallium Arsenide, Indium are being investigated
to replace conventional devices. Different materials and techniques to
presently used to solve scaling problems in parallel with new architectures
such as: alternate materials for Gate and dielectrics. Strained Silicon,
Germanium (Ge), SiGe, Arsenic Indium, Gallium Arsenide are being used
and investigated for improving the channel mobility in conventional
devices [2,6,7,8].

1.2. FROM “JUNCTIONS TO NO JUNCTIONS”

P-N junctions have played pivotal role in electronics for many years. These
pn junctions serve the most important part of functionality of
semiconductor electronic devices from diodes to transistors. Almost all
transistors and diodes rely on pn junctions for their operation by
exploiting various modes and types of junctions. Dependence of electronic
devices upon pn junctions for their operation (desired operation) over
decades has been so much compulsory that it seemed almost impossible
to realize the functionality of diodes or transistors without junctions. The
fact, that current-voltage characteristics of devices are controlled by the
presence, absence, magnitude and polarity of applied voltage and/or
electric field to pn junction electronic industry has spent considerable
amount of energy, effort, time and human resources to exploit the junction
phenomenon to optimum level. While this approach coupled with
improvements in Integrated circuit (IC) technology has given us greater
understanding of junctions and hence played its role, in helping to
continue, the progress in Integrated Circuits (ICs). The ever increasing

2
demand for high switching speed, computing power and huge storage
capacity have led electronics industry to scaling the geometry of
transistors. The continued scaling of geometry and parameters has
resulted in emergence of some problems like Short-Channel Effects (SCE),
tunneling of Gate oxide, Drain-Induced-Barrier-Lowering (DIBL) and
leakage effects which pose threat to further reduce the transistor
dimensions without sacrificing the performance or increasing the cost per
unit device in an IC. Thus, need for improving the present technology and
finding alternate device architectures was felt around two decades ago and
some unconventional devices like Double and triple gate Metal-Oxide-
semiconductor Field-effect Transistors (MOSFETS) using Silicon-on-
Insulator (SOI) technology have been made to improve the control of gate
over channel and minimize the SCEs [9,10,11]. Junctions are becoming
increasingly difficult to engineering with high doping as required for ultra-
short devices in nanometer scales. Good control of doping concentrations
with greater number of dopants in active condition requires high
temperature anneals. This results in increase in cost. A transistor without
junctions will not need costly anneal diffusion steps to be fabricated. It will
save energy, effort, time and most importantly money. A Junctionless
device also avoids some of the inherent problems associated with sharp
gradient changes in junctions and interfaces. Above all, the device design
becomes simpler as opposed to ever growing complexity with scaling and
increase in functionality and performance of devices.
The idea of transistor without junctions was proposed by Lilienfield in his
gated-resistor apparatus in 1925 [10], well before the invention of first
transistor in 1947. A team of researchers from Tyndall Institute have
demonstrated the fully-Complementary Metal-Oxide-semiconductor
(CMOS) capable Junctionless device made with Silicon Nanowire (SiNW)
using SOI technology which appeared in Nature in 2010 [11]. Few other
teams of researchers have also demonstrated similar type of devices with
different names but the operation principles remain essentially the same.
This tri-gate (or Gate-all-around; GAA) device has advantages in reduced
the problems faced by bulk Metal-Oxide-semiconductor Field-effect
Transistors (MOSFET) devices and matching performance profile with MOS
devices. Junctionless devices have opened new doors to continue the
shrinking of size of transistor in sub-micron scales and hence the potential
of these devices is being investigated and discussed here by topical review.

The search results from high impact factor journals reveal that, during
past six months (July to Dec, 2010), research papers on Junctionless
devices is increasing. As many as 15 papers in IEEE, Elsevier
Sciencedirect, Nature Nanotechnology, and Applied Physics letters
appeared on this device.

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1.3. NATURE AND STRUCTURE OF TRANSISTOR

Junctionless Nanowire Transistor (JNT) [11,12] reported in Nature

nanotechnology (February 21, 2010) is a three terminal device with Drain,
Source and Gate terminals and a channel between Drain and Source
which is controlled by Gate terminal. This device is made upon thin-film
Silicon-on-Insulator (SOI) so it’s also classified as SOI-TFT device. With
Gate structure all around the Gate, it makes tri-gate or Gate-all-around
structure. To be precise, this device is a “Gated-resistor” as the authors
name it due to its resemblance to Lilienfield’s first gated-resistor transistor
[10] The gate is heavily doped p-type (P+) polysilicon material and heavily
doped n-type (N+) for n-channel and p-channel transistor respectively. For
the n-channel JNT, the Nanowire is uniformly and homogeneously doped
through the Drain, the channel to the Source by donor impurity, that is
(n-type or N+) doping. For p-type devices, the gate is n-type where as the
source-Channel-Drain formed by Si Nanowire are doped by acceptor
impurity (p-type material). The flow of current from Drain to Source is
realized in whole body (bulk) of Nanowire which acts as channel. When
Gate potential (VG) is made slightly greater then threshold voltage (Vth), the
majority carriers (as opposed to minority carriers in the Bulk MOS) flow
from Drain to Source in thin film of Nanowire. When VG is made
sufficiently larger than Vth so that VG equals Flat-band voltage (VG=VFB)
level, the device is completely in Accumulation Mode, which is the normal
mode of operation for JNT rather than Inversion Mode of Bulk MOSFETs.
This is contrary to the conventional MOS and other thin-film SOI based
devices where current flows at the surface of the channel in strong
inversion. In accumulation condition, gated-resistor/JNT becomes a
simple resistor. The n-channel JNT works with positive Gate (VG) and
Drain (VD) voltages. Whereas, opposite polarities are used for p-channel
Gated-resistor. Since the operation of gated-resistor resembles with
conventional MOSFET, so we will not discuss its operation at great length.

This device is also referred to as Junctionless Multi-gate field-effect

transistor [13], Vertical slit field-effect transistor [14], Nanowire pinch-off
FET [15], Accumulation-mode metal oxide semiconductor field-effect
transistors [16] (AMOSFETs) in literature by different researchers apart
from being called a gated-resistor or gated trans-resistor [11]. The gated-
resistor name comes due to 1) the fact that it has no junctions as in bulk
MOS devices and 2) the Si Nanowire acts as a resistor whose resistivity (or
conduction) is controlled by the Gate terminal, hence the name: gated-
(trans)-resistor. The Fact that Drain, Source and Channel are of same
doping polarity, there are no doping gradients and hence the device
structure becomes easier to design without costly thermal annealing and
diffusion steps [11]. This attribute makes the JNT design process easier
and cheaper as compared to bulk MOS devices. Hence, JNT is attracting
the attention in mico/nanoelectronics industry as a potential device for
continuing the scaling of transistors in sub-micron size. The device made

4
by Tyndal team; Jean Pierre Colinge and his colleagues/co-authors [11] is
focused here for review due to following reasons:

1. This device without junctions has comparable characteristics with

conventional planar and non-planar architectures as demonstrated
[11]
2. The design methodology is simple and easy to understand and the
scheme for the fabrication of JNTs on bulk Silicon is also proposed
by Kranti et al [12].
3. Results of the electrical behavior, characteristics and geometrical
data for the device is demonstrated both experimentally and with
simulations and is published in literature [11,12, 13,18].
4. Potential for further scaling the device is also demonstrated using
simulations [17, 20].
5. They have reduced short-channel effects, drain-induced barrier
lowering, and subthreshold slope degradation when aggressively
scaled down in size [19].
6. They are expected to have a reduced degradation in mobility with
gate voltage [19].
7. They relax the requirements reducing gate dielectric thicknesses
[19].
The device proposed by Colinge et al [11] has no Source-Channel and
Drain-Channel Junctions. The thin film of highly doped Si wire contains
all three structures i.e: Source, Channel and Drain without any doping
gradient. This is to say that no separate doping steps are used to engineer
the Source and Drain regions A simple schematic of the structure of n-
channel JNT without Showing Insulator Later (Buried Oxide) is shown in
Figure 1 below:

Figure1: The schematic of n-channel Nanowire Junctionless Transistor

[11].
One can notice that there are no junctions between channel and
Source/Drain regions. The structure shows that a thin layer of Gate oxide

5
is also shown to separate the Gate from channel. For closer description,
the device is illustrated in figure 2 in order to appreciate the small
geometrical scales and dimensions with Transmission Electron Microscope
(TEM) image coupled with schematic of the device. This isolation is
necessary for controlling the electric field and hence the amount of current
in the channel. The Gate voltage controls the current.

Figure 2: Schematic of JNT

with Transmission Electron
Microscope (TEM) image of the
transistor structure [25].

For p-channel device, only Si NW is doped with P+ impurities and the gate
is of N+ polysilicon. Figure 3 shows both cross section of both N-Channel
(A) and P-channel (B) of Gated-resistor or JNT [11].

Figure 3: Cross section of N-Channel gated-resistor (A) and P-channel

gated-resistor (B) of Gated-resistor or JNT[11].

Blue colour indicates strong p-type (acceptor) doping by BF 2 and light blue
colour represents the heavy doping by n-type material As (donor). Green
indicates gate oxide or SiO2.

6
1.4. THE CHARACTERISTICS OF JUNTIONLESS NANOWIRE
TRANSISTOR.

We explain the characteristics n-channel JNT in Accumulation Mode by

separately analyzing the effect of positive supply voltages at Gate and
drain terminals.
In normal unbiased condition, the device is off and no current flows from
the Drain to Source (depletion condition). The device operation with VD
held constant: at sufficiently low voltages for n-channel transistor. VG is
applied to gate terminal. This is shown in figure 4 [11].

Figure 4: Conduction under different values of Gate Voltage (V G). No active

channel when VG is below Vth (A). Active channel is whole Nanowire body
when VG is greater then Vth (B). Higher values of VG facilitate more
conduction through the body of SiNW (C) Sufficiently large value of V G
drive the device deeper in accumulation (D) [11,25].

When VG is applied, the device begins to form a channel between Drain

and Source and hence electrons (majority carriers for n-channel) drift
towards Drain from Source. This condition is shown as VG below Vth in
Figure 4A. As we progressively increase the VG, the channel becomes wider.
This means more electrons flow through channel, hence greater current
density until it is completely in accumulation as shown in figures 4B, C
and 4D.

The Nanowire body becomes channel itself. The Channel keeps expanding
as we pass the Vth and beyond till flat-band conditions are reached; figure
4D. After reaching Flat-band voltage (VG=VFB) level, the device is in flat-
band conduction [11].

In normal device operation, the influence of Drain Voltage counts more for
on-current of the device so we explain the effect of VD with VG held
constant at VG greater than Vth [2]. As VD is increased gradually, the gated-
resistor is driven into saturation in the same manner as bulk MOS

7
transistor. This is illustrated in figure 5 below. The amount of drain
current ID that results from increased VD is on-current (ION).

Figure 5: Gated-resistor under

different values of Drain
voltage (VD): A-D [12].VD equals
50 mV (A), VD = 200 mV:
higher VD makes gated-resistor
go into saturation (B), and
larger values of VD= 400 and
600 mV, at a given VG, drive
the device into depletion as
depicted in (C) & (D)
respectively.

ELECTROSTATIC PINCH-OFF IN GATED-RESISTOR

The cross sections of the gated-resistor must be of small geometries so

that their dimensions allow the channel region to be electrostatic depleted
to block the flow of electrons completely [11, 12]. The cross section of
Nanowire is shown in figure 6. This is done by drain voltage for a given V G.
Higher VD shifts the device from saturation to pinch-off as shown in
figures 5C and D for V D equals 400 and 600 mV respectively. Near pinch-
off, there is depletion like in traditional MOSFETs.

Figure 6: Cross section of Nanowire [25]

Figure 7 shows the current-voltage characteristics of Gated-resistor [25.

The current ID as function of VG for two values of VD (VD=50mV and 1.0V).
Note, the polarity of voltage is positive for n-channel and negative for p-
channel device. One can see that the DIBL is negligible. Further more, the
amount of ID is higher in n-channel than in p-channel due to higher
mobility of electrons than holes.
Behaviour of gated-resistor with drain voltage is shown in figure 8. Graphs
show ID as function of VD for different values of VG for n-and p-channel

8
gated resistors Si NW width, W is 20nm and the length of gate is 1 µm.
The W/L ratio is 0.02.

Figure 7: Measured ID versus VG of

N-and P-channel Junctionless
transistors [11]. Drain voltages of
+50mV and+1 V (Right side, n-
channel). Drain voltages of -50mV
and -1 V (left side, p-channel).

The off current is negligibly small.

Demonstrated ratio of Ion/Ioff
measured at V G=±1V and VG=0 is
higher then 1x106. The width of the
device is 30 nm and Length is 1
µm. The Width to Length ratio:
W/L=0.03 [11].

Figure 8: Output characteristics. ID as function of VD for different values of

VG: n-channel gated resistor (a) and a p-channel gated resistor (b) [11].

In the next section, we will evaluate the potential of gated-resistors by

comparing with current conventional MOSFETs and MuGFET
architectures based devices having junctions. Can gated-resistors be the
ultimate candidates for future short channel devices? A comparative
analysis is made to investigate its viability as future CMOS device.
Fabrication process of JNT is also presented.

9
2 RECENT RESEARCH RELEVANT TO THE JUNCTIONLESS DEVICES

Since the First fully CMOS capable Junctionless Nanowire Transistor

demonstrated experimentally by J.P. Colinge and his co-authors, number
of research groups has focused attention towards JNTs. Some were
already working on Nanowire tri-gate transistors with or with out
junctions independently. Several papers attempt to increase the
understanding of JNTS and by simulations, experiments and comparing
with conventional devices [11, 19, 21].
Long-channel (1µm) junctionless transistors differ in structure but have
similar characteristics with several advantages over their conventional
counter parts. Structural differences are highlighted in figure 9.
In MOS transistor, junctions and channel are made with alternating
doping polarity as shown above in figure 9(a). The n-channel device has p-
type channel and Source/Drain regions are doped with n-type material,
making NPN structure from Source to Drain with channel sandwiched
between two electrodes. Junctionless transistor is based upon SOI
technology but it no junctions between drain and Source figure 9(b).

(a) (b)
Figure 9: Bulk MOSFET with junctions (a) and SOI Junctionless transistor
(b) [21, 25]

Since the channel is homogeneously doped n-type for n-channel (or p-type
for p-channel) so it helps solve the problems that resulted from doping
gradients and statistical variations in doping and costly annealing issues:
Short-channel effects (SCEs), gate oxide thickness (e.g. gate tunneling,
etc.), junction depth and dopant density fluctuation.

The JNT has gate from 3 edges, so it is a 3-gate SOI device. This tri-gate
structure is especially useful to give the gate greater control over the
channel. Hence it limits the SCEs. Figure 10 [25], shows the evolution
from single gate to tri-gate and/or gate-all-around architectures for
conventional thin-film-SOI devices with junctions. The gate structure in
conventional SOI devices and Junctionless transistors is similar. Second
advantage of having no junctions is that there is no gradient change and
hence no diffusion takes place in JNT. Thermal budget and high

10
temperature anneals are excluded which saves energy, time and cost of
fabrication. This also serves as bases for fabricating the devices even with
shorter channel lengths since JNT doesn’t need the ultra-sharp doping
concentration gradients for switching between n-type and p-type (typical
values for doping concentration from n-type 1x1019 cm-3 to p-type 1x1018
cm-3). This shift of concentration within small distance has been a
constant challenge for short-channel devices. [11]

Figure 10: Evolution of SOI-based devices from single gate to Multi-gate

structure [25].
To help visualize the how doping profiles differ in Junctionless and
conventional MOS device, the figure 11 highlights the difficulty that stems
from shortening the channel and controlling the doping precisely.

Figure 11: Doping in Short-

channel and Ultra-short
Channels. MOS doping (a), JNT
doping (b) [25].
Gated-resistor structure makes
JNT operate differently then both
Bilk and FinFET tri-gate devices.
Gated-resistor is normally-on
device as opposed to its classic
cousins MOSFET and FinFET
which are normally-off devices
and rely on creation of channel
between source and drain.
Inversion channel is created by
induced electric field by gate
terminal. Drain current depends
upon gate voltage and general
IDnature
≈µCOX Wof I is described
si ⁄ L D(VDD-V TH)
2  (1) by
equation 1 (for simple gate for the
purpose of simplicity):
11
 (1)

Where COX is the gate oxide capacitance (ox/tox), W is the device width, L is
the gate length. Adding the gate electrode capacitance, C= COX WsiL (Wsi =
W) to this equation, we can calculate the intrinsic time delay  of
conventional device:

(2)

Equations 1 and 2 show dependence of ID and time delay upon many

factors. For example, if we wish to increase the speed performance of the
bulk MOS, we have to either reduce the gate length, L or increase the
mobility. Reducing L puts extra burden on junctions by increasing the
doping concentration. Increase in doping concentration reduces the
mobility due to rise in the scattering rate of charge carriers in dense
channel. Solution to this has been the popular strain Si, SiGe, techniques
to augment the performance of device by applying strain and compression
in channel region [22].

By contrast, the gated-resistor is put to flat-band condition with the shift

of flat-band and threshold voltage to positive voltage by the difference in
work function of Si NW and gate electrode. Resistor behaviour of device is
its working in flat-band condition and the current from drain to Source in
the channel is [11]:

(3)

Where ND the doping concentration of Nanowire and Tsi is the thickness of

the silicon Nanowire (or height of the Si NW), Wsi is the width of wire (the
distance between two gates in multi-gate structure). Note the equation 3
for ID for JNT is given as simple ID equation just as in case of single gate (in
order to explain the concept without increasing complexity). It is
interesting to note and appreciate the independence of I D from gate oxide
capacitance, in this mode of operation. This gives us the ease to increase
ID by increasing the doping in the wire. In the absence of junctions, this is
most probably the greatest advantage over bulk devices as increasing the
doping concentration is possible without worrying about statistical
problems, and gradients. The intrinsic delay () of gated-resistor is
calculated by [11]:

(4)

12
Notice that there is no change in the capacitance of the gate electrode in
both devices; Bulk MOS and gated-resistor [11]. Figure 12 shows
comparison between conventional MOSFETs and Gated-resistors with
different doping concentrations, on the basis of intrinsic delay. Notice the
gate delay (CV/I) given in picoseconds (ps) increases with an increase in
gate length in nanometers (nm) in both devices but decreases by
increasing the doping concentrations in gated-resistors. Hence, speed
(intrinsic delay) becomes independent of gate-oxide thickness. This is good
news that the efforts needed to continually decrease effective oxide
thickness (EOT) will not be necessary any more [19]. In figure 12, EOT is
equal to 1 nm for all gated resistors, and further it can be assumed that Tsi
equals L [11]. Looking at different curves in the figure, which correspond
to channel doping levels, as low as 1x1019 cm-3 to as high as 8x1019cm-3,
one can clearly appreciate the amount of improvement brought to
performance by increasing doping [11].

The threshold voltage depends on doping concentration, effective oxide

thickness and on the cross-sections of Si NW in gated-resistors [12]. This
makes gated-resistors lag behind conventional inversion mode ultra-thin
film devices in terms of threshold variation which is larger in gated-
resistors. Colinge et al [11] report a variation (dependance upon thickness
of Si NW; dVTH/dTSi) of 80 mV nm-1 in devices with a doping concentration
of 1x1019 cm-3 and an EOT of 2 nm.

Their simulations indicate that the variation in threshold due to thickness

of Si Nanowire is twice that of measured in the lightly doped, ultra-thin
inversion-mode SOI devices [11,23]. This variation can be controlled and
reduced by using commercially available thinner wafers of Si Nanowire.
Threshold voltage variations on the order of VTH up to 20 mV can be
achieved at wafer level by using thin-film SOI wafers with a TSi of less
than 0.2 nm [23].

The 2-D simulations using ATLAS by Choi, et al [18] show fluctuations in

the Vth due to variation of dimensions of thin film of SiNW are much higher
in Junctionless transistors than SOI thin-film gate-all-around (GAA or tri-
gate) inversion mode transistors. Figure 13 illustrates the difference in two
types of devices.

13
Figure 12: Comparison of intrinsic delay time in Bulk MOS and Gated-
resistors. Comparison of different doping concentrations in gated-resistors
is also shown.

Figure 13: Experimental ID–VG characteristics of (a) GAA inversion-mode

transistors and (b) GAA junctionless transistors with various Wsi values
(6, 10, and 13 nm) at VD of 0.05 and 1V. The doping concentration of each
device is shown in the inset of the graph.

This variation is primarily attributed to high doping concentrations in thin

SiNW[14]. To highlight the effect of WSi as parameter of doping in Vth

14
simulations [14] in figure 14 show clearly the dependability of Vth on WSi
and doping.

Figure 14: Schematics of the simulated devices. (a) Inversion-mode

transistor. (b) Junctionless transistor. (c) Vth fluctuation according to
various WSi’s in inversion-mode and junctionless transistors as a
parameter of doping concentration [18].

Dependance of Vth on change in Wsi is explained by the equation 5 below:

(5)

The effect of decreasing WSi on ID is shown in figure 15 with two aspect

ratios [12]. However, decreasing the width (WSi) is desired to suppress
SCEs. In order to give greater control to gates by closing them near to each
other, the WSi needs to be thinned. Consequently, gates suppress SCEs
and Vth rolloff by achieving greater control over the channel potential [18].

Figure15: ID saturation in JNTs with WSi = TSi and L=25 nm, Tox =1nm and
a poly+ polygate is used. VDD =1V and Ioff=100nA/um (a), ID saturation in
JNTs with TSi= 2xWSi and L=25 nm, Tox =1nm and a poly+ polygate is
used. VDD =1V and Ioff=100nA/um (b) [12].

15
3. SUBTHRESHOLD SLOPE (SS) AND DRAIN INDUCED BARRIER
LOWERING (DIBL) IN JUNCTIONLESS NANOWIRE TRANSISTORS

As explained earlier (please refer to figure 7 at page number 9), the Ion/Ioff
of gated-resistors is higher than 1x106 [11]. The superior behaviour of
device for subthreshold Slope (SS) and drain-Induced Barrier Lowering
(DIBL) is a key merit for gated-resistors. The SS defines how sharply a
device can switch from one state to another (on-off switching). Expressed
in mV/decade, the SS can be drawn as the inverse of the slope of ID (log)
versus VG below Vth. Gated-resistors demonstrate SS of 64mV/dec at
300K. The variation with temperature values of 225 to 475K remain fairly
close to the ideal lower limit (kBT/q) ln(10) [11]. This compares well with
numerical values of SS 63 mV/dec for best conventional SOI tri-gate
transistors and is much better then 80 mV/dec for classic Bulk transistors
[11,27]. To further understand the electrical characteristics of junctionless
transistor, we present the comparisons between junctionless and classical
SOI-based multi-gate (MuGFETs=Double-gate or Tri-gate TFTs) Inversion
Mode (IM) devices in figure 16 (a) and (b) [3]. For these simulations, the
effective channel length of IM devices is 8 nm (as opposed to original
physical channel length of 10nm due to S/D and S/G overlaps). Channel
doping is kept low in order to avoid corner effects [28].
The leakage current IOFF in junctionless device is well below the IOFF for IM
transistor (around 10-15) as the shown in figure 16(a) which plots ID as
function of VG. The DIBL is less than one-third the value observed in IM
devices. Figure 16(b) compares the results for two types of devices,
showing how DIBL and Vth vary with physical gate length (Lgate) [13]. This
figure plots DIBL by measuring the variation in Vth with change in VD from
50 mV to 1V. Hence the variation in Vth as function of VDS (DIBL = Vth(VDS
= 0.05 V)- Vth(VDS = 1 V)) [13]. These plots clearly establish the suitability
of Junctionless transistor for short channels as it is evident from looking
at DIBL and Vth values at 10 nm Lgate.

In multi-gate devices, the resistance due to overlap and underlap of gate

along the edges of drain and source becomes important in determining
where the Vth for a given device is. The effective channel length (the
junction length between source and drain) is decreased roughly by 10 to
20 percent from original physical length of channel. For example, the
figure 16 shows simulated threshold voltage of inversion-mode MuGFETs
as a function of effective channel length with Lgate =10 nm at V DS = 50
mV. One can appreciate the insensitivity of Vth of Junctionless transistor
to effective channel length by looking at straight horizontal line along x-
axis [13].

16
 Figure 16(a): Id–Vg characteristic of Figure 16(b): DIBL and
a junctionless device and an threshold voltage of junctionless
inversion-mode device with Lgate = and inversion-mode devices as a
10 nm [13]. function of physical gate length
[13].

4. FABRICATION PROCESS OF THE JUNCTIONLESS NANOWIRE

TRANSISTOR OR GATED-RESISTOR

Nanowire Junctionless Transistors are fabricated on SOI BOX substrate

like other SOI based devices but they differ in the structure of source and
drain regions. For substrate, readily usable standard SOI wafers can be
used. A Si layer on top of burried oxide is grown initially. The lengths of
these wafers can be from 300 to 400 nm. The thickness of SOI layer can
be adjusted up to 10 or 15 nm as per requirements. Second step is of e-
beam lithography to pattern the silicon nanowires or nanoribbons.
Nanowires with different widths and thickness can be patterned. Ideally,
thickness is in the range of 10 to 15 nm and widths can range from 20 to
40 nm. These dimensions define the actual size of devices and normally,
the Aspect Ratio (AR) of 1 or 2 is used but there are no hard and fast rules
to follow integral AR. Next step is doping the Si Nanowire with impurities.
Doping process is performed with ion-implantation in most modern
devices due to better control of dose and imputirty behaviour. A uniform
dose of P+ or N+ ions for P-type or N-type devices respectively is implanted
after growing the 10 nm gate oxide layer to dope the device. Recall that
doping for junctionless devices is uniform and homogenous for drain-
channel-source areas. No change of doping gradient or no separate
source/drain doping in the whole nanowire is performed. The
concentrations of P+ or N+ impurities can be optimised to achieve high
drive current and good source and drain contact resistance. Typical

17
concentration can start from 2x1019 cm-3 and can go as high as 5x1019
cm-3. The impurity materials are Arsenic for N-type and BF2 for P-type
devices. Full depletion is necessary for turning the device off
electrostatically. Small cross-sections make depletion easier to achieve.
Once doping is performed, gate structure is formed. A layer of amorphus
silicon with thickness of 50 nm is deposited in low-pressure chemical
vapour deposition (LPCVD) reactor at 550°C to form the gate. Gate is then
heavily doped with Boron or Arsenic ion impurity to form opposite doping
polarity with channel. N-type gate with Arsenic impurity profile of 2x1014
atoms per centimetre square (cm-2) for p-channel device, for example.
Boron is used (to dope the gate) for n-channel device. To activate the
dopant impurities by transforming amorphus to polysilicon, annealing is
performed for 30 min at 900°C in nitrogen. Contact electrode for gate is
patterned by oxide deposition and etching in reactive-ion etch (RIE)
reactor. Transmission electron microscope images of five parallel silicon
gated resistor nanowires/nanoribbons with a common polysilicon gate
electrode are illustrated in the figure 17. Image of individual nanowire is
magnified in Figure 17b for the sake of details. The oxide is deposited and
etched to form contact holes after the gate electrode. Finally, the
metallization by aluminium plus TiW is done thereby finising the process
by establishing the electrical contacts to the device terminals/ electrodes.

Figure 17: Transmission

electron micrograph of
silicon gated resistor
nanoribbons. Five parallel
devices with a common
polysilicon gate electrode
(a). Magnification of a single
nanoribbon device (b).
Individual atomic rows can
be seen in the silicon [11].

This device has the gate electrode wrapping from two sides and top of
channel (along three edges) so we call it multi-gate, tri-gate, or gate-all-
around device [11,26]. The major difference in the fabrication process
from classical trigate FETs is that: the channel of classical tri-gate is
either is left undoped or doped with p-type material at a concentration of
2x1017 cm-3 for n-type device. A heavy doped N+ Polysilicon is used as
gate. The source and drain junctions are formed using Arsenic doping by
ion-implantation (dose= 2x1014 cm-2 with an energy of 15 keV) [11].

18
5. POTENTIAL FOR SCALING

Is Nanowire junctionless transistor prone to short channel problems at

nanometer scales? It is a big question. The advantage of having no
junctions and hence no doping gradients is appealing and exciting
however, it needs to be investigated rigorously and extensively weather
that this advantage is sufficient to design nanometer transistors. The
present device under study “Nanowire Junctionless Transistors” [11], is a
device with channel length of 1 micrometer, which is not really a
nanoscale device [24].

The discussion can begin with few basic issues/questions:

1. What will be the trade-off between ultra-high doping and mobility
degradation in ultra-short channel lengths [19]?
2. With short channel and gate lengths, how the control of electrostatics of
device is achieved by gate?
3. What structure or architecture favours most suitably to realize short-
channel Junctionless transistors?
4. At higher values of VD, what percent of loss in saturation is tolerable
[19]?
5. What factors affect the threshold voltage and how [19]?

Each of above issues merits a focused discussion separately. A fair and

detailed discussion is beyond the scope of this review hence we confine our
talk to few important points only.

As the gate lengths are reduced to 10 nm or below, the gate in MOSFETs

loses control of electrostatic phenomenon, short-channel effects become
pronounced and gate has to compete with source and drain for charge
control in the depletion region and its close regions [29].

The most important parameter for Short-channel devices is the

length/thickness (length to thickness or Aspect ratio), that determines the
device size. Technology has evolved towards designing more gates on a
single device in order to give greater control to gate. For example, double-
gate, tri-gate or gate-all-around devices have been demonstrated for this
purpose. With more gates, thinner devices are possible and gates can
control the operation of device along the edges (tri-gate=left-right-top)
relatively easily. For this reason, 50 nm and 3 nm gate devices has been
reported through simulated results [17,20]. Figure 18 shows the structure,
geometry and cross section of short-channel Junctionless transistors. A 3
nm gate device structure and cross section is shown in figure 18 (a) and
(b) while TEM micrograph of cross-section pi gate (Ω or п gate) gated-
resistor is depicted in 18 (c) [17,20].

19
Figure 18: The structure, geometry and cross section of short-channel
Junctionless transistors. A 3 nm gate device structure (a), cross section of
Si NW (b) TEM micrograph of cross-section pi (п) gate gated-resistor (c)
[17,20].

In principle, gate length can scale with wire thickness, without reducing
the gate dielectric thickness [29].
The other issue of doping is important in Nanowire Junctionless devices
with short channels and/gates. Although, Junctionless device is without
junctions (hence no dopant gradient from junctions to channel) but heavy
doping is required for channel, source and drain. Therefore, the doping
concentration (and positioning of dopants) becomes critically important at
short channel lengths of few nanometers [24]. Localisation of dopants is
required to near perfect in order to avoid variations in V th from device to
device. As we have already seen above that highly doped channel make Vth
sensitive to WSi or in other words, Vth variations are due WSi (high doping).

SHORT-CHANNEL EFFECTS

Short channel effects are greatly improved in junctionless transistors due

the fact, the effective length (Leff) of gate is smaller in the on state than in

Figure 19: Different

effective gate lengths in: a
junctionless transistor in
the off state (a), a
junctionless transistor in
the on state(b), an
inversion-mode
transistor (c)[20,30].
the off state (LOFF > LON),
which is contrary to Bulk
MOSFETs where Leff Is

20
increased due to the presence of Space Charge Zone (SCE) and DIBL (L OFF
< LON). Figure shows how the length of device plays role at different times:
when the device is on and when it is off. For bulk MOSFETs, the Physical
length Lphysical is the actual designed length of channel, Leff the effective
length when device is on and LSCE is the effective length when the device is
off [20].

This is illustrated in figure 20. The graphs show the. Drain Current (ID) for
a 50 nm device as function of Gate voltage (VG) is shown in (a), and the
Subthreshold Slope (SS) versus Gate voltage VG is depicted in (b) [20].
It is apparent from the figure 20 that we have: (a) high on-off ratio (106), (b)
very good SS (60 mV/dec) and DIBL (7 mV) characteristics are achieved.
Absence of junctions and squeezing of device electrostatically makes these
results possible.

Figure 20: The electrical characteristics of 50nm JNT: Drain Current (ID) as
function of Gate voltage (VG) (a), Subthreshold Slope (SS) versus Gate
voltage VG (b) [20].

The out put characteristics (ID - VDS resulting from simulations) for 3nm
gate junctionless device are shown in figure 21 (a) and (b) for n and p-
channel respectively. This device shows good behaviour in saturation and
can be used in constant-current source applications [17].

21
Figure 21: The out put (ID - VDS) characteristic for SiNW junctionless
transistor dimensions shown in fig. 18 (a). n-type JNT doped by As
impurity atoms (a), p-type JNT doped by Ga impurity atoms (b) [17].

6. CONCLUSION

Nanowire Junctionless Transistors come up with better performance

to most modern junctioned transistors, and with relatively simpler and
cheaper fabrication/design methodology. These devices are viewed as
promising candidates for short-channel and ultra-short channel device
architectures with immunity to performance degradation. Although, there
are some technological barriers and deeper understanding of Physics,
governing the behaviour of devices with nanometer geometries, is required,
ultra-short-channel devices will eventually make visible difference in
forthcoming years.

22
7. Appendix A: Permission(s).

Mr. J.P. Colinge is the principal author of “Silicon Nanowire Transistors

Without Junctions” and co-author of most other papers studied in this
review. His email is attached here in which he has consented to allow us to
reproduce or copy figures from his articles.

From: Jean-Pierre Colinge <jean-pierre.colinge@tyndall.ie>

To: azhar ayaz <gemini_azri@yahoo.com>
Sent: Tue, January 18, 2011 10:05:23 AM

Subject: RE: Article inquiry+permission: NJTs

Hello/Bonjour,

J’ai mis toutes mes publications sur le transistor sans jonctions

« junctionless » sur un serveur à l’adresse suivante :

http://www.tyndall.xxxxxx/xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

Vous avez ma permission de reproduire/copier des figures de mes articles.

JPC
---------------------------------------
Prof. Jean-Pierre Colinge
Tyndall National Institute
Lee Maltings, Dyke Parade
Cork , Ireland
Tel.: +353 21 490 48 65
Fax.: +353 21 490 42 97

23
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26