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field effect transistors are produced using high cell density, DMOS ● 20V/5.2A,RDS(ON)=42mΩ@VGS=2.5V
trench technology. This high density process is especially tailored to ● Super high density cell design for extremely low RDS(ON)
minimize on-state resistance. These devices are particularly suited ● Exceptional on-resistance and maximum DC current
for low voltage application such as cellular phone and notebook capability
PIN CONFIGURATION
(SOP-8)
Top View
Jan, 2007-Ver1.3 01
ME9926
Dual N-Channel 2.5-V (G-S) MOSFET
td(on) 9.7
Turn-On Time
tr VDD=10V,ID=1.0A, VGEN=4.5V 16.4
ns
td(off) RG=6Ω 34.6
Turn-Off Time
tf 3.1
Ciss Input capacitance 576
Coss Output Capacitance VDS=8V, VGS=0V, f=1.0MHz 83 pF
Crss Reverse Transfer Capacitance 22
Notes
a. Pulse test; pulse width ≦ 300us, duty cycle≦ 2%
Jan, 2007-Ver1.3 02
ME9926
Dual N-Channel 2.5-V (G-S) MOSFET
Jan, 2007-Ver1.3 03
ME9926
Dual N-Channel 2.5-V (G-S) MOSFET
Jan, 2007-Ver1.3 04
ME9926
Dual N-Channel 2.5-V (G-S) MOSFET
MILLIMETERS
DIM
MIN MAX
A 1.35 1.75
A1 0.10 0.25
B 0.35 0.49
C 0.18 0.25
D 4.80 5.00
E 3.80 4.00
e 1.27 BSC
H 5.80 6.20
h 0.25 0.50
L 0.40 1.25
θ 0° 7°
Jan, 2007-Ver1.3 05