SOVERAN S.

DHAKAD
Asst Professor
Asst.
Electronics & Communication Engg. Deptt.
(M-Tech-
Tech- Embedded System & VLSI Design)

Email--Id
Email Id--soveran_vlsi@rediffmail.com
Contact-- 09685396020 ,0751-
Contact ,0751-2387520(O)

NAGAJI INSTITUTE OF TECHNOLOGY & MANAGEMENT,

THAKUR BABA CAMPUS ,JHANSI ROAD , NH-75 ,SITHOLI ,GWALIOR-474001
E-Mail –examcell@nitmindia.org
@ g ,,website:- nitmindia.org.
g
Contact No. -0751-2410201 ,2387520 ,9685396020
A HIGH DENSITY, LOW LEAKAGE, 5T SRAM
FOR EMBEDDED CACHE MEMORY
¾Memory
¾Operation
¾Sense Amplifier
p
¾Cache Memory
¾Leakage In SRAM Cell
¾Why 5T SRAM Cell
¾Structure Diagram Of 5T SRAM
¾Operation in 5T SRAM Cell
¾Implementation & Result
¾Conclusion & Future Work
¾Reference
¾A memory in terms of computer hardware is a storage unit.
unit
¾Storage devices such as magnetic device, hard disk, CDs,
DVDs etc
¾The memory of a computer stores the programs and data
while being
gpprocessed.
¾It is built up of small units called bits which can hold one
binary symbol of data (referred to as a ’1’ or a ’0’).
¾Also it helps to boot the system.
¾Memory directly accessible by CPU.
CPU
¾There are Various types of basic operations that have to
be supported
pp by
y a RAM. These are the writing
g and reading
g
of ’0’ and ’1’ respectively .
NITM , GWALIOR
 MEMORY

RAM ROM

RAM (Random Access Memory)-

¾Random Access Memory, a memory where information
can be stored and retrieved in non
non-sequential
sequential order.
order

ROM (Read Only Memory)-

¾ROM also
¾ROM, l k
known as firmware,
fi i an integrated
is i t t d circuit
i it
programmed with specific data when it is manufactured.
ROM chips are used not only in computers, but in most other
electronic items as well.
NITM , GWALIOR
¾It is an array of elements
which can either store 1 or 0.
¾It is dynamic in nature.
¾It is volatile .
¾It is made either of
semiconductors
i d or capacitors
i
as required.

NITM , GWALIOR
 bitline conditioning
wordlines
row decoderr bitlines

memory cells:
2n-k rows x
2m+k columns

n-k
k column
circuitry
n column
decoder
2m bits

NITM , GWALIOR
¾The memory cells in a SRAM are organized in rows and
columns.
Memory Cell = 2n-k Row Ҳ 2m+k Columns

¾I the
¾In th write
it operation
ti , the
th Word
W d line
li isi in
i active
ti state,
t t in
i
that cause each data bit to be stored in a selected cell in the
associated column.

¾In the read operation,

operation the read line is in active state,
state in
that cause the data bits stored in the selected row to appear
on the
th Data
D t I/O lines.
li

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NITM , GWALIOR
The 6T SRAM cell has a differential read operation. This
means that both the stored value and its inverse are used in
evaluation to determine the stored value. Before the onset of
a read
d operation,
ti th Word
the W d line
li i held
is h ld low
l and
d the
th two
t
bitlines connected to the cell through transistors M5 and M6
are precharged high . Since the gates of M5 and M6 are held
low, these access transistors are off and the cross-coupled
latch is isolated from the bitlines.

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 A_b bit_b

1.5

1.0
word bit

0.5

A
00
0.0
0 100 200 300 400 500 600
time (ps)

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Read Operation:-
¾If the value is a 1, stored at Q.
¾The read cycle is started by pre charging both the bit
lines to a logical 1, then asserting the word line WL,
enabling both the access transistors.
¾Th second
¾The d step
t occurs when
h the
th values
l stored
t d in
i Q and d
Q are transferred to the bit lines by leaving BL at its pre
charged
g value and discharging
g g BL through
g M1 and M5 to a
logical 0.
¾ On the BL side, the transistors M4 and M6 pull the bit line
toward VDD, a logical 1.1
¾If the content of the memory was a 0, the opposite would
happen and BL would be pulled toward 1 and BL toward 0.

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 Ab
A_b

1.5 A

bit b
bit_b
1.0

0.5
word

0.0
0 100 200 300 400 500 600 700
time (ps)

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Write Operation:-
¾The start of a write cycle begins by applying the value to be
written
itt to
t the
th bit lines.
li
¾If we wish to write a 0, we would apply a 0 to the bit lines, i.e.
setting BL to 1 and BL to 0.
This is similar to applying a reset pulse to a SR-latch , which
causes the flip flop to change state.
¾A 1 is written by inverting the values of the bit lines. WL is
then asserted and the value that is to be stored is latched in.
¾Note that the reason this works is that the bit line input-
d i
drivers are designed
d i d to
t be
b much h stronger
t th
than th relatively
the l ti l
weak transistors in the cell itself, so that they can easily
override the previous state of the cross-coupled inverters.

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¾It is practically embedded in every application that
requires electronic use interface such as digital cameras,
cameras
cell phones, etc.
¾I t l CPU caches
¾Internal h , hard
h d disk
di k buffers,
b ff router
t b ff
buffers,
LCD screens and printers also normally employ static RAM
to hold the image displayed .
¾Small SRAM buffers are also found in CDROM and CDRW
drives; usually 256 kB.

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¾A Sense
S Amplifier
A lifi is
i an essential
i l
circuit in designing memory chips.
¾ The resulting signal,
signal in the event of a
Read operation, has a much lower
voltage swing. To compensate for that
swing a sense amplifier is used to
amplify voltage coming off Bit Line.
¾The voltage
¾Th lt coming
i outt off the
th sense
amplifier typically has a fully swing (0 -
2.5V)) voltage.
g
¾Sense amplifier also helps reduce the
delay times and power dissipation in
the overall SRAM chip.
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There are many versions of sense
amplifiers used in memory chips :-
¾The one that we will use in our
design is called a Cross-coupled
Sense Amplifier
p demonstrated on a
block diagram below.
¾During a read sequence, Bit Line
and Bit Line are directed into X and
X inputs. Once SE has been set to
logic 1, the amplifier turns on, and
gives Y and Y as its outputs.

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¾Cache memory is basically a cost-effective method of
improving system performance.
¾Cache memory is a relatively small, high-speed memory
that stores the most recently used instructions or data.
¾Cache memory
e o can
ca also
al o use
e dynamic
d a ic RAM (DRAM).
(DRAM)
¾Cache memory stored information to the microprocessor
much faster than if only high-capacity DRAM is used.
used
¾Cache memory used to store data or instructions likely to
be used soon by the CPU. Its purpose is to speed up
operation by bridging the performance gap between the
CPU and the main memory.

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Two types of cache level are used in cache memory:
memory:-
L1 :- It usually integrated into the processor chip and has a
veryy limited storage
g capacity.
p y
¾It gives an extremely short access time, and therefore
provides the highest performance
¾This cache usually runs at the same clock frequency as
the CPU
L2 :-It is separate memory chip or set of chips external to
the processor and usually has a larger storage capacity
th
than L1 cache.
h
¾This is connected to CPU through an internal bus
Some higher-level caches (L3. L4, .), but L1 and L2 are the
most common.
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There are some very important requirements for a memory
when it is to be embedded as on-chip cache:
¾It has to be reliable and stable. This is of course true for
all memories, but is specially important for cache due to
the more extreme performance requirements and area
limitations.
¾Memory provide high performance gap between main
memory and the CPU.
¾Another important
p requirement
q is low power
p
consumption.

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Low power design is important from three different
reasons-
Technology driven forces
Minimum feature size,
Minimize parasitic capacitance
Higher operating speed
Design driven forces
Power consumption
p in digital
g circuits
Power consumption in analog circuits
Market driven forces
The growing demand for long life portable
equipment.

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There are various types of applications of low power-
¾Battery-powered portable systems, for example laptops,
CDs, ,DVDs
¾Electronic packet communication products such as;
cordless and cellular telephones, PDAs (Personal Digital
Assistants), pagers.
b GH processors for
¾Sub-GHz
¾S f high-performance
hi h f workstations
k t ti
and computers.
¾ Other applications such as WLANs (Wireless Local Area
Network) and electronic goals (calculators, hearing aids,
watches, etc.).

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¾The supply voltage must be reduced.
¾The threshold voltage (VT) must be reduced proportionally
with
ith the
th supply
l voltage
lt so th
thatt a sufficient
ffi i t gate
t overdrive
d i isi
maintained.
¾Reduction in the threshold voltage causes increase in
leakage current.
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¾During an idle phase,
phase the word lines are deselected (WL =
‘0’) and the bit lines are precharged (BL = ‘1’ and BL = ‘1’).
¾The memory cell data,data either transistors N4,
N4 P1,
P1 N2 (for bit
= ‘1’) or N3, P2, N1 (for bit = ‘0’) will be leaking .
¾The transistors in the off state in bold for bit = ‘0’. In this
case N3,N1 and P2 are off and will be leaking. The leakage
current in the memory cell would be as shown in equation:
ImemcellIdle = IDsub(N1) + IDsub(N3) + IDsub(P2)
where, IDsub is the sub threshold leakage current of
the MOSFET , which is given by the equation :-
IDsub = Is e VGS/(nKT)/q [1-VDS/eKT/q ]
where, Is and n are imperial parameters with n ≥ 1.
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¾ The sub threshold leakage in the whole memory core
is given by equation .
ImemcoreIdle = Nrows. Cools . ImemcellIdle
where, Nrows and Ncols are the number of rows and
columns respectively in the memory core.
¾ Thus to reduce the leakage of a memory cell we have
t concentrate
to t t on two
t componentst off leakage
l k :-
1. one is the leakage inside the cell .
2. Second is leakage to bit lines.

NITM , GWALIOR
Techniques
T h i are used
d to reduce
d the
h leakage
l k current is:-
i
Dual VT :-
¾This technique requires no additional control circuitry
and can substantially reduce the leakage current when
compared to low VT devices.
devices
¾No data are discarded and no additional caches
misses are incurred. However , high
high- transistors have
slower switching speed and lower current drive.
ABC-MTCMOS :-
¾It can reduce the leakage current significantly using a
simple circuit while in the sleep mode.

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¾I order
¾In d to reduce
d undesirable
d i bl leakage
l k current in
i the
h
sleep mode, the back gate bias is automatically
controlled to increase the threshold voltage.
g

NITM , GWALIOR
DVS (Dynamic Voltage Scaling):-
In this method to reduce the leakage power of SRAM cells,
in active mode.
¾When cells are not intended to be accessed for a time
period,
e iod they
the are
a e placed
laced in
i a sleep
lee mode.
ode
¾In a sleep mode the leakage power is significantly
reduced due to the decreases in both leakage current
and supply voltage.

NITM , GWALIOR
We have to used Two PMOS transistor P1,P2, to control the
supply voltage of the memory cell based on the
operating.
p g
1. Active Mode 2. Sleep Mode
¾ If cell is active mode , P1 supplies a standard supply
voltage, and P2 supplies a standby voltage.
¾ If cell is Sleep mode, P1 and P2 are controlled by
complementary supply voltage control signals.
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Embedded
E b dd d memory-
¾Easy to implement in generic CMOS process.
¾Easy to design as logic circuit.
¾Easy to test by finite-state machine.
Compliable design-
ed ce
¾Fixed cell size
s e to a
allow
ow us ded
dedicating
cat g in peripheral
pe p e a c circuit
cu t
design
¾Synchronous interface since 0.35µm
0 35µm generation simplifies
the design
¾A larger number of instances required
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¾In the 5T SRAM cell differs fundamentally from the cell
used in 2PMOS & 3 NMOS Transistors.

¾The latch of the cell is disconnected from the gnd supply to

f ilit t write.
facilitate it

¾This requires
q an additional metal wire and also destabilizes
all cells on the bit line during write.

¾The design and all simulations are carried out at 100nm

technology.

NITM , GWALIOR
Read Operation-The operation scheme when reading a 5T
cell is very similar to the 6T SRAM.
¾Before the onset of a read operation, the word line is held
low and the bitline is precharged.
¾The bitline is not precharged to VCC, So another value is
carefully chosen according to stability and performance
requirements.
¾If reading
di a ’0’,
’0’ BL will
ill now be
b pulled
ll d down
d th
through
h the
th
transistor combination. If instead a ’1’ is to be read, the
situation is slightly different from the 6T case.
NITM , GWALIOR
Write Operation-Writing in the 5T SRAM cell differs from
the 6T cell mainly by the fact that it is done from only one
bitline.
¾In the 5T cell the value to be written is held on the bitline,
and the word line is asserted.
¾The 6T cell was sized so that a ’1’
1 could not be written by
a high voltage on the bitline, the 5T cell has to be sized
differently.

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¾The difference between the 5T SRAM and the 6T SRAM is
how the sensing of the stored value is done.

¾The 6T cell has two bit lines and the stored value is sensed
differentially.

¾The 5T cell only has one bitline. Depending on the value

stored, the 5T bitline is either raised or lowered.

¾A few different techniques can be used for this. One idea

might be to use a type of sample and hold circuit that would
Sample the value before the read and then use this value as a
reference in a differential sense amplifier.

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NITM , GWALIOR
NITM , GWALIOR
NITM , GWALIOR
 Table 5.1: Leakage power and performance of 6T cell

Metrics Standard 6T cell

Read time (WL high up to 100mV difference in bit lines)

336ps

Write time (WL high up to node flips)

76ps

Leakage Power/cell 2.03nW

NITM , GWALIOR
Table 5.2: Comparison of leakage power reduction
techniques

Leakage Reduction Leakage Power Percentage

Technique Dissipation/Cell (in Reduction
n W)

Conventional 2.030 -

DVS 0.230 88.7

G t d VDD
Gated-VDD 0 033
0.033 98 3
98.3

NITM , GWALIOR
 Table 5.3:
5 3: Leakage power and performance of 5T cell
Metrics Standard 6T cell
Read time (WL high up to 100mV difference in bit lines) 365ps

Write time (WL high up to node flips) 102ps

Leakage Power/cell 1.79nW

Table 5.4: Comparison of leakage power dissipation in 6T

and 5T cell
Leakage Reduction Leakage Power Percentage
Technique Dissipation/Cell (in nW) Reduction

6T 5T
Conventional 2.030 1.790 11.8
DVS 0.230
. 0.170
. 7 26.0
Gated-VDD 0.033 0.029 12.1

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¾ Various circuit level techniques have been applied to 6T
and designed 5T SRAM cell for leakage power reduction
and compared. Out of all the techniques discussed DVS has
f
found
d to
t be
b the
th best
b t as it reduces
d l k
leakage comparable
bl to
t
Gated VDD as well as retain the cell information.

¾ It has been found that in conventional 6T SRAM cell up

to 98% reduction in leakage power can be achieved using
these techniques. With conventional 5T cell about 11.8%
leakage power reduction has been achieved than
conventional 6T cell. Further applying the leakage
reduction
d ti t h i
techniques t the
to th 5T cellll has
h shown
h 26% more
reduction in leakage than in the case of 6T cell.

NITM , GWALIOR
¾ In this thesis various circuit level leakage g p power
reduction techniques have been analyzed with 6T and 5T
SRAM cell at 180nm technology. A large reduction in
leakage has been observed.
observed As memory cells being
discussed have to be used in cache memory their stability is
also very important. So stability analysis of both 6T and 5T
cells after
f applying
i leakage reduction
i techniques
i can be
analyzed.
q
¾ Device level techniques such as retrograde
g well;; Halo
doping and LDD (Light Doped Drain) implantation can be
employed for leakage reduction in individual MOSFETs
which eventually will reduce in large reduction.
reduction As leakage
will be more significant beyond 100nm technology so this
work should be extended to higher technologies such as
90
90nm, 70
70nm or beyond.
b d

NITM , GWALIOR
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S Singh
Si h Dhakad,
Dh k d Shyam
Sh Akashe,
Ak h “CMOS VLSI
Design” National Conference in NEE ,Gwalior , Ist Oct. 2009.
[[2]] Soveran Singh g Dhakad, Shyam
y Akashe, “Cache
Memory cell for Leakage Power ” National Conference in
NEE , Gwalior ,26th June . 2010.

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[29] Soveran Singh Dhakad,

Dhakad Shyam Akashe,
Akashe “CMOS
CMOS VLSI Design
Design” National Conference in NEE
NEE, Gwalior,
Gwalior
Ist Oct. 2009.

[30] Soveran Singh Dhakad, Shyam Akashe, “Cache Memory cell for Leakage Power” National
Conference in NEE, Gwalior, 26th June. 2010.

NITM , GWALIOR
 THANK YOU
AND
HAVE A NICE DAY
NITM , GWALIOR