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Schematic of n-Channel
Enhancement Mode MOSFET
p-Channel Depletion- Cross-Section of nMOSFET and pMOSFET
Mode MOSFET
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MOS Capacitor Under Bias: MOS Capacitor Under Bias:
Electric Field and Charge Polarity of the applied voltage reversed
Parallel plate capacitor – n-type semiconductor substrate Means that a voltage must be applied to the
gate to create an inversion layer.
For the MOS capacitor with a p-type substrate,
a positive gate voltage must be applied to
create the electron inversion layer;
For the MOS capacitor with an n-type
substrate, a negative gate voltage must be
applied to create the hole inversion layer.
Negative gate bias:
Holes attracted to gate
In Smith & Sedra,
MOSFET Capacitance ε ox
Cox = .
– Case 1: Accumulation tox
Examine the cross-sectional view in the figure In R Jacob Baker,
below.
ε ox
With negative bias voltage, mobile holes from ′ =
Cox .
the substrate are attracted or accumulated tox
under the oxide, or dielectric. We follow Baker’s
book notation here.
′ ⋅A
Cox = Cox Consider less negative voltage, which is not
enough to attract a large number of holes
under the oxide and not positive enough to
attract a large number of electrons.
Depletion capacitance
in series with oxide C.
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MOSFET Capacitance – Case 2: Depletion MOSFET Capacitance – Case 2: Depletion
Under these conditions, the surface under the The MOSFET operated in this region is said to
gate is said to be nearly depleted (depleted of be in weak inversion or the subthreshold
free electrons and holes). region because the surface under the oxide is
We see that an additional capacitance exits. not heavily n+.
The new capacitance is the oxide capacitance
in series with the depletion capacitance.
The depletion layer is formed between the
substrate and the induced channel.
+++
–––
Example #1 - Capacitor
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Example #1 – Solution
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The positive potential on the gate attracts electrons under If Vs = Vfp and then Q’b = 0, the MOSFET is operating in the
the gate oxide. This charge is equal and opposite to the accumulation mode, or the MOSFET is OFF in circuit terms.
charge in the polysilicon gate material. At this point the number of holes at the oxide-
The charge/unit area is given by semiconductor surface is NA, the same concentration as the
bulk.
Qb′ = qN A X d = 2ε si qN A Vs − V fp
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As VGS is increased, the surface potential becomes more The threshold voltage of the n-channel MOSFET is
positive. defined as the applied gate voltage needed to
When Vs = 0, the surface under the oxide has become create an inversion charge in which the density is
depleted (the carrier concentration is ni).
equal to the concentration of majority carriers in
When Vs = –Vfp (a positive number), the channel is inverted
(electrons are pulled under the oxide forming a channel),
the semiconductor substrate.
and the electron concentration at the semiconductor-oxide In simple terms, we can think of the threshold
interface is equal to the substrate doping concentration. voltage as the gate voltage required to “turn on”
The value of VGS when Vs = –Vfp is arbitrarily defined as the the transistor.
threshold voltage, VTHN and the negative charge under the
gate oxide is given by
′ = 2qN Aε si − 2V fp
Qbo
with units of Coulombs/m2.
Note that the surface potential changed a total of 2|Vfp|
between the strong inversion and accumulation cases.
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In a simplified cross section of a MOSFET, the
Schematic of n-Channel gate, oxide, and p-type substrate regions are the
Enhancement Mode MOSFET same as those of a MOS capacitor.
In addition, now there are two n-regions, called
the source terminal and the drain terminal.
The current flow in a MOSFET is the result of the
flow of charge in the inversion layer, also called
the channel region, adjacent to the oxide-
semiconductor interface.
The channel length L and channel width W are
defined in the figure above.
The channel length is typically less than 1 µm.
The oxide thickness on order of 400 Å or less.
A thick oxide, called the field oxide, is deposited Basic Transistor Operation
outside the area in which the metal interconnect
lines are formed.
the gate material is usually heavily doped
polysilicon.
Modelling DiffusionFigures from CMOS Circuit Design, Layout, and Simulation, Copyright 2008, Wiley-IEEE,
CMOS d
• The time interval between collisions averaged • The net carrier velocity in an applied field is
over the entire electron population is τcn, the called the drift velocity, vd.
mean scattering time for electrons, is not • It can be found by equating the impulse (force
altered appreciably by the applied field. x time) applied to an electron during its free
flight between collisions with the momentum
gained by the electron in the same period.
• This equality is valid because steady state is
reached when all momentum gained between
collisions is lost to the lattice in the collisions.
Modelling DiffusionFigures from CMOS Circuit Design, Layout, and Simulation, Copyright 2008, Wiley-IEEE, Modelling DiffusionFigures from CMOS Circuit Design, Layout, and Simulation, Copyright 2008, Wiley-IEEE,
CMOS d CMOS d
• The force on an electron is –qE and the • The equation states that the electron drift
momentum gained is mn*vd. Thus, velocity vd is proportional to the field with a
proportionality factor that depends on the
− qEτ cn = mn*vd mean scattering time and the effective mass of
the nearly free electron.
or • The proportionality factor is an important
qEτ cn property of the electron called the mobility and
vd = − is designated by the symbol µn.
mn*
qτ cn
µn = L ( 3)
mn*
Modelling DiffusionFigures from CMOS Circuit Design, Layout, and Simulation, Copyright 2008, Wiley-IEEE, Modelling DiffusionFigures from CMOS Circuit Design, Layout, and Simulation, Copyright 2008, Wiley-IEEE,
CMOS d CMOS d
• Because vd = –µnE, the mobility describes how • Differential resistance of the channel region
– With a length dy and a width W, it is given by
easily an electron moves in response to an
applied field. 6474 8
eff. sheet Res.
Modelling DiffusionFigures from CMOS Circuit Design, Layout, and Simulation, Copyright 2008, Wiley-IEEE,
CMOS d
• Differential voltage drop across resistance • Transconductance parameter
– The differential voltage drop across this differential – The transconductance parameter, KP, for a n-channel
resistance is given by MOSFET is given by
ε ox
dV ( y ) = I D ⋅ dR =
ID In Smith’s book, this quantity is
⋅ dy ′ = µn ⋅
KPn = µ n ⋅ Cox
Wµ nQI′ ( y ) denoted as k’n. tox
I D ⋅ dy = Wµ nQI′ ⋅ dV ( y ) – For a p-channel MOSFET is given by
ε ox
– Substituting Eqn.(3) in this equation above, ′ = µp ⋅
KPp = µ p ⋅ Cox
tox
′ (VGS − V ( y ) − VTHN ) ⋅ dV ( y )
I D ⋅ dy = Wµ nCox L (4 ) where µp is the mobility of the holes in a PMOS
transistor.
ε ox A Cox ε ox
Cox = ′ =
Cox =
tox A tox
[
I D = K n ⋅ 2(VGS − VTHN )VDS − VDS
2
]
– For PMOS,
[
I D = K p ⋅ 2(VSG − VTHP )VSD − VSD
2
]
– Kn and Kp are defined in Neamen’s textbook.
– β, KPn and KPp are defined in Baker’s textbook. We
use these notation here in this course.
(a) The relative charge density is essentially constant along the (c) As vDS reach the point vGS–vDS(sat)=VTHN across the oxide at
entire channel length. the drain terminal, the induced inversion charge density at the
drain terminal is zero. The incremental channel conductance at
(b) When vDS increases, the voltage drop near the drain terminal the drain is zero, which means the slope of iD versus vDS curves
decreases, which means that the induced inversion charge is zero.
density near the drain also decreases. The incremental
conductance of the channel at the drain then decreases, which (d) For vDS>vDS(sat), the point in the channel at which the
causes the slope of iD versus vDS curve to decrease. inversion charge is zero moves toward the source terminal.
Electrons enter the source, travel through the channel toward
the drain, and then…
(d) …at the point where the charge goes to zero, are injected into
the space-charge region, where they are swept by the E-field to
• MOSFET Operation in the Saturation Region
the drain contact. In the ideal MOSFET, the drain current is
– The voltage V(y) when y = L in Eqn.(3) is simply VDS.
constant for vDS>vDS(sat). This region is referred to as the
In the previous analysis, we said that VDS is always
saturation region. As the applied gate-to-source changes, the iD
less than VGS – VTHN so that at no point along the
versus vDS curve changes.
channel is the inversion charge zero.
– When VDS = VGS – VTHN the inversion charge under – Increase in VDS beyond VDS,sat attract the fixed
the gate at y = L (the drain-channel junction) is zero, channel charge to the drain terminal depleting the
Eqn.(3). charge in the channel directly adjacent to the drain
– This drain-source voltage is called VDS,sat(=VGS–VTHN), (again, pinching off the channel).
and indicates when the channel charge becomes – Further increases in VDS do not cause an increase in
pinched off at the drain-channel interface. the drain current.
– Figure 6.10 shows that the depletion region, with a – When a MOSFET is operated with its channel
thickness of Xdl, between the drain and substrate pinched off, that is, VDS≥VGS – VTHN and VGS≥VTHN, it
increases, causing the channel to pinch off. is operating in the saturation region. Substitution of
– If VDS is increased until the drain-substrate depletion VDS,sat into Eqn.(5) gives
region extends from the drain to the source, the
⎡ 2
⎤
⋅ ⎢(VGS − VTHN )VDS −
device is said to be punched through. W VDS
I D = KPn ⋅ ⎥
– Large currents can flow under these conditions,
causing device failure.
L ⎣ 2 ⎦
= KPn ⋅
W ⎡
⋅ ⎢(VGS − VTHN )(VGS − VTHN ) −
(VGS − VTHN ) ⎤
2
– The maximum voltage, for ⎥
near minimum-size channel L ⎣ 2 ⎦
lengths, that can be applied
β
⋅ ⋅ (VGS − VTHN ) = ⋅ (VGS − VTHN ) L (6 )
between the drain and KPn W
=
2 2
source of a MOSFET is set
by the “punchthrough” 2 L 2
voltage. → for VDS ≥ VGS − VTHN and VGS ≥ VTHN
– We can define an electrical channel length of the – Since the depletion layer width Xdl increases with
MOSFET as the difference between the drawn increasing VDS, the drain current increases as well.
channel length, neglecting laterial diffusion, and the
depletion layer width, Xdl, between the drain n+ and Lelec (↓ ) = Ldrawn − X dl (↑ )
the channel under the gate oxide by
I D (↑ ) = ⋅ (VGS − VTHN )
KPn W
Lelec = Ldrawn − X dl ⋅
2
2 Lelec (↓ )
– Substituting into Eqn.(6), we obtain a better
representation of the drain current – This effect is called channel length modulation (CLM).
– If Ldrawn is increased the effects of Xdl changing (CLM)
become negligible.
⋅ (VGS − VTHN ) L (7 )
KPn W
ID = ⋅
2
2 Lelec
– Taking the derivative of Eqn.(7) with respect to VDS, – Typical values for λ, called the channel length
∂Lelec ∂ (Ldrawn − X dl )
modulation parameter, range from greater than 0.1
= = −1 V–1 for short-channel devices to 0.01 V–1 for long-
∂X dl ∂X dl channel devices.
– Equation (6) can be rewritten for a device operating in
∂I D ∂I D ∂Lelec
= ⋅ the saturation region, taking into account channel
∂VDS ∂Lelec ∂VDS length modulation as
– When VDS = VDS,sat or the drain current is at the • Characteristics of a long-channel NMOS device
triode/saturation region border, the drain current is – VGS = 5 V and VTHN = 1 V for an n-channel MOSFET.
sometime specified as
– Calculated VDS,sat = VGS – VTHN = 5 – 1 = 4 V.
– Typical curves for the NMOS in the simulation results:
I D , sat = I D when VDS = VDS , sat = VGS − VTHN
Short-Channel MOSFETs
∆vDS
r0 = =∞
∆iD vGS =const.
The electrical parameter of KPn is the oxide capacitance and Example #2 – Calculate the current in
carrier mobility, which are essentially constants for a given an n-channel MOSFET
fabrication technology.
The geometry, which is the width-to-length W/L ratio, is a variable See page 128 Example 3.1 (Neamen)
in the design of MOSFET that is used to produce specific current- Solution Example #2
voltage characteristics in MOSFET circuits. First, consider the units involved in the equation,
You can rewrite the conduction parameter in the form as follows:
KPn W
Kn = ⋅ , KPn = µ nCox is called the process conduction ⎛ cm 2 ⎞ ⎛ F ⎞
2 L W (cm ) ⋅ un ⎜⎜ ⎟⎟ ⋅ ε ox ⎜ ⎟
⎝ V − s ⎠ ⎝ cm ⎠ F
paremeter.
Kn = =
KPn is constant for a given fabrication technology 2 L(cm ) ⋅ tox (cm ) V −s
and W/L is the transistor design variable.
=
(C V ) = A
V −s V2
Wunε ox W ⋅ KPn β
Kn = = = = (0.249)(1.5 − 0.75)
2
2 Ltox 2L 2
= 0.140 mA
=
(40 ×10 )(650)(3.9)(8.854 ×10 )
−4 −14
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Note that all voltages and currents are positive using the
naming convention seen in the figure.
The devices are complementary.
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Symbols for p-Channel n-Channel Depletion-Mode MOSFET
Enhancement-Mode MOSFET
In addition to the n-channel enhancement-mode device and the p-
channel enhancement-mode device, there is the n-channel
depletion mode MOSFET and p-channel depletion-mode
MOSFET as well.
Symbols
Symbols
Finite Output Resistance
Non-ideal Current-Voltage
Characteristics For vGS>vDS(sat), the actual
point in the channel at which
Five non-ideal effects in the current-voltage the inversion charge goes to
characteristics of MOS transistors are examined. There zero moves away from the
effects are: drain terminal. The effective
Finite output resistance in the saturation region. channel length decreases,
Body effect. producing the phenomenon
called channel length
Sub-threshold conduction. modulation.
Breakdown effects. An exaggerated view of the
Temperature effects. current-voltage characteristics
is shown in figure on the next
slide.
1
ro ≅
λI DQ
Body Effect Body Effect
For the bias condition that the substrate, or The body effect can cause a degradation in
body, is connected to the source as assumed circuit performance because of the changing
previously, the threshold voltage is constant. threshold voltage.
This is not case for M2 in the circuit below. However, we will neglect the body effect in our
circuit analyses, for simplicity.
Zero or reverse-bias voltage exists across the source-
substrate pn junction here
A change in the
source-bias junction
voltage changes the
threshold voltage.
This is called body
effect. The same
situation exists in p-
channel devices.
iD = K n (vGS − VTHN )
The effect may not be
significant for single
device, but integrated
√iD is a linear function vGS. circuit with thousands or
A plot of this ideal millions of devices may
relationship is shown on the contribute to significant
right. power dissipation.
Subthreshold Conduction Breakdown Effects
Examine the current-voltage plot below: Examine the current-voltage plot below:
1V
=1 V
ID is related to VGS and VDS using For long channel MOSFET, this can be written as
VDS,sat = VGS – VTHN
⋅ ⋅ (VGS − VTHN ) [1 + λ (VDS − VDS , sat )]
KPn W
ID =
2
This term is very important when doing analogue
2 L
for VDS > VDS , sat = VGS − VTHN and VGS > VTHN design. It is only valid for long-channel MOSFETs.
The voltage VDS,sat simply indicates, for long- or
L (9 ) short-channel MOSFETs, the VDS at the boundary
between triode and saturation.
VDS,sat is the voltage where the MOSFET moves
from the triode region to the saturation region. When VDS = VDS,sat, the drain current is labeled
ID,sat or
2 L 2 L
So, eqn.(9) can be written
1
ro = Figure 9.3a on next slide shows the IV curves for each
λI D , sat component of the circuit where a single quadrant is used
for the IV plotting plane.
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A gate-drain connected MOSFET (Fig. 9.5) is seen often in
analogue design.
Comment: Because drain and gate terminals are shorted together,
In the triode region, the MOSFET behaves like a resistor. VGS=VDS.
In the saturation region, the MOSFET behaves like a current If VGS>VTHN, current is flowing through the device. Then for
source in parallel with a resistor as seen before in Fig. 9.3b. the MOSFET to operate in the saturation region,
The resistive component, whether in the triode or VDS VDS
saturation regions, is often called the MOSFET’s output 67 8 67 8
resistance. VD − VS ≥ VG − VS − VTHN or VD ≥ VG − VTHN
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2 L
and VSD , sat = VSG − VTHP
L (10 )
¾ Swap the subscripts of the symbols used in
the NMOS equations, the terminal currents
and voltages of the MOSFET are always
positive (both NMOS and PMOS).
NMOS Common-Source Circuit NMOS Common-Source Circuit
The DC equivalent circuit is shown here in (a). The drain-to-source voltage is
The gate-source junction is a capacitor, so dc
gate current is zero.
VDS = VDD − I D RD
R2
VG = VDD
R2 + R2
iD = K n (VGS − VTHN )
2
= (0.1)(2 − 1)
2
= 0.1 mA
Example #3 – DC circuit analysis Exercise #3.3
Drain-to-source voltage is Solve the exercise problem on p. 142 of the
textbook by Neamen.
VDS = VDD − I D RD = 5 − (0.1)(20 ) = 3 V
Power dissipated
Example #4 - PMOS
Example #4 - PMOS From circuit (b)
⎛ R2 ⎞ ⎛ 50 ⎞
See Neamen p.143 Example 3.4 VG = ⎜⎜ ⎟⎟(VDD ) = ⎜ ⎟(5) = 2.5 V
⎝ 1
R + R2 ⎠ ⎝ 50 + 50 ⎠
Example #4 - PMOS Example #4 - PMOS
Assume that the PMOS is not biased in the Solving this quadratic equation for ID,
saturation region. So, drain current is
[
I D = (0.2) 2(2.5 − 0.8)(5 − I D (7.5)) − (5 − I D (7.5))
2
]
[
I D = K p 2(VSG + VTHP )VSD − V 2
SD ] = (0.2)[3.4(5 − I (7.5)) − (5 − I D (7.5))2 ]
D
Source-to-drain voltage is
= −1.6 + 9.9 I D − I D2 (11.25)
VSD = VDD − I D RD 0 = 11.25I D2 − 8.9 I D + 1.6
Combining these two equations, 8.9 ± 79.21 − 4 ×11.25 ×1.6
ID =
[
I D = K p 2(VSG + VTHP )(VDD − I D RD ) − (VDD − I D RD )
2
] 2 ×11.25
[ ]
11.585 6.215
=
= (0.2 ) 2(2.5 − 0.8)(5 − I D (7.5)) − (5 − I D (7.5))
2 or
22.5 22.5
= 0.515 mA or 0.2762 mA
ID =
VDD VDS
− =
5 VDS
− (mA )
RD RD 20 20
⋅ (VGS − VTHN )
KPn W
ID =
2
The voltage at the source terminal is
2 L VS=–VGS=–2.24 V.
⎛ 80 ⎞
250 = ⎜ ⎟ ⋅ (3)(VGS − 0.8) ⇒ VGS = 2.24 V
2
⎝ 2⎠
Dc drain-to-source voltage is
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Summary of performing a small-signal analysis
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Example 9.5 Long-channel MOSFET parameters used in this unit. The VDD=5 V
Problem statement: and the scale factor is 1 µm (1e-6)
¾ Calculate the DC and AC voltages and currents for the
circuit seen in Fig. 9.17. Use the long-channel MOSFET
parameters from Ch. 6, (shown on next slide). Parameter NMOS PMOS Comments
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2 L
2I D L
Neglecting channel-length modulation results in VGS = ⋅ + VTHN
KPn W
2
⎛ VDS ,sat ⎞
KPn W ⎜ 64748 ⎟ Assuming both M1 and M2 are operating in the
ID = ⋅ ⋅ VGS − VTHN ⎟
2 L ⎜⎜ ⎟ saturation region (we’ll verify this in a moment), we get
⎝ ⎠
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STEP #1 (cont’d) STEP #1 (cont’d)
¾ To see if M1 is in saturation, we use
40 2 ?
VGS1 = VGS 2 = ⋅ + 0.8 = 1.058 V → VDS , sat ≈ 250 mV VD1 ≥ VG1 − VTHN
120 20
¾ The drain current of M3 is 20 µA. The source-to-gate → 3.842 ≥ (2.5 − 0.8 = 1.7 ) V (yes, M1 is in saturation )
voltage for M3 is ¾ Next we look at M4. M4’s source-to-gate voltage is 5 V.
¾ For PMOS to operate in saturation region,
2 ⋅ 20 2
VGS 3 = ⋅ + 0.9 = 1.158 V → VSD , sat ≈ 250 mV
40 30 VS −VD S −VG
} V}
¾ The drain potential of M1 and M3 is VSD ≥ VSG − VTHP → VD ≤ VG + VTHP
VD1 = VD 3 = VDD − VSG 3 = 3.842 V 5−VD
} } 5− 0
64SD7
V
48
3 ,sat VSD ≥ VSG − 0.9 → VD ≤ 0 + 0.9 = 0.9 V
VSG 3 − VTHP = (5 − 3.842) − 0.9 = 1.158 − 0.9 = 0.258 V
¾ So for M4 to be in saturation, VD ≤ 0.9 V. Gate of M2 is
¾ We know that M3 is in saturation. 2.5 V and VGS2=1.058 V, then its source is 1.442 V,
which makes it impossible for M4 to be saturated.
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?
STEP #1 (cont’d)
VD1 ≥ VG1 − VTHN
¾ To estimate the drain-to-source voltage of M4, we use
→ 3.842 ≥ (2.5 − 0.8 = 1.7 ) V (yes, M1 is in saturation )
⎛ 2
⎞
⋅ ⎜⎜ (VSG − VTHP )VSD −
W VSD
I D = KPP ⎟⎟
L ⎝ 2 ⎠
¾ ID=20 µA and its gate-source voltage is 5 V
30 ⎛ 2
⎞
20 = 40 ⋅ ⎜⎜ (5 − 0.9)VSD −
VSD
⎟
2 ⎝ 2 ⎟⎠
2
VSD − 246VSD + 2 = 0
VSD = 8.13 mV
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STEP #1 (cont’d) STEP #1 (cont’d)
¾ M4 can be thought of as a resistor with a value of LTSpice
Simulation
1 1
Rch ≈ = Spice directive
W
⋅ (VGS − VTHN ) ⎛ µA ⎞ 30
KPn ⎜ 40 ⎟ ⋅ (5 − 0.9) .op
L ⎝ V ⎠ 2
= 407 Ω
¾ Alternatively, the resistance can be estimated from
VSD 8.13 mV
= = 407 Ω
ID 20 µA
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W 30
g m 3 = 2 ⋅ KPp ⋅ I D = 2 ⋅ 40µ ⋅ ⋅ 20µ ≈ 150 µA V
L 2
¾ M4 is operating in the triode region and so we think of
it as a resistor (407 Ω).
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STEP #3 – Replace the active elements (e.g., MOSFETs) ¾ Notice how we can replace M3 with a resistor of 1/gm3.
with their small-signal models. The DC sources are
removed. That is, short out all DC voltage sources and
¾ This is because the AC voltage across M3 is vsg3 =vsd3 and
open up all DC current sources). the AC current through it is id or
¾ Fig. 9.18 shows the simplified AC schematic of Fig. 9.17. 1 vsd vsg
= =
g m id id
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The energy difference between the Ei and Ef is given by, for a
p-type semiconductor by
N
Ei − E fp = kT ⋅ ln A
ni
And for an n-type semiconductor by
N
E fn − Ei = kT ⋅ ln D
ni
The band diagram of a pn junction (a diode) is seen in the
figure below.
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E fn − E fp kT N N
Vbi = = ⋅ ln A 2 D
q q ni
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