1)What is difference between HFN synthesis and CTS?

Answer:
HFNs are synthesized in front end also.... but at that moment no placement infor
mation of standard cells are available... hence backend tool collapses synthesiz
ed HFNs. It resenthesizes HFNs based on placement information and appropriately
inserts buffer. Target of this synthesis is to meet delay requirements i.e. setu
p and hold.
For clock no synthesis is carried out in front end (why.....????..because no pla
cement information of flip-flops ! So synthesis won't meet true skew targets !!)
... in backend clock tree synthesis tries to meet "skew" targets...It inserts c
lock buffers (which have equal rise and fall time, unlike normal buffers !)... T
here is no skew information for any HFNs.
HFN synthesis tries to make fanout as less as possible.
While building and optimizing buffer tree special clock buffers are used to make
rise and fall transition same so that there is no difference in the duty cycle
of the clock. If there is change in duty cycle it will affect skew. (flop to flo
p delay)
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2)What is difference between normal buffer and clock buffer?
Answer:
Clock net is one of the High Fanout Net(HFN)s. The clock buffers are designed wi
th some special property like high drive strength and less delay. Clock buffers
have equal rise and fall time. This prevents duty cycle of clock signal from cha
nging when it passes through a chain of clock buffers.
Normal buffers are designed with W/L ratio such that sum of rise time and fall t
ime is minimum. They too are designed for higher drive strength.
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3)Is it possible to have a zero skew in the design?
Answer:
Theoretically it is possible....!
Practically it is impossible....!!
Practically we cant reduce any delay to zero.... delay will exist... hence we tr
y to make skew "equal" (or same) rather than "zero"......now with this optimizat
ion all flops get the clock edge with same delay relative to each other.... so v
irtually we can say they are having "zero skew " or skew is "balanced".
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4) If the full chip design is routed by 7 layer metal, why macros are designed u
sing 5LM instead of using 7LM?
Answer:
Because top two metal layers are required for global routing in chip design. If
top metal layers are also used in block level it will create routing blockage.
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5) What are the input needs for your design?
Answer:
For synthesis: RTL, Technology library, Standard cell library, Constraints
For Physical design: Netlist, Technology library, Constraints, Standard cell lib
rary
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6) What is SDC constraint file contains?
Answer:
Clock definitions
Timing exception-multicycle path, false path
Input and Output delays
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7)How did you do power planning?
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8)How to find number of power pad and IO power pads?
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9)How the width of metal and number of straps calculated for power and ground?
Answer:
Get the total core power consumption; get the metal layer current density value
from the tech file; Divide total power by number sides of the chip; Divide the o
btained value from the current density to get core power ring width. Then calcul
ate number of straps using some more equations. Will be explained in detail late
r.
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10)How to find total chip power?
Answer:
Total chip power=standard cell power consumption,Macro power consumption pad pow
er consumption.
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11)What are the problems faced related to timing?
Answer:
Prelayout: Setup, Max transition, max capacitance
Post layout: Hold
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12)How did you resolve the setup and hold problem?
* Setup: upsize the cells
* Hold: insert buffers
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13)In which layer do you prefer for clock routing and why?
Answer:
Next lower layer to the top two metal layers(global routing layers). Because it
has less resistance hence less RC delay.
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14)Define antenna problem and how did you resolve these problem?
Answer:
Increased net length can accumulate more charges while manufacturing of the devi
ce due to ionisation process. If this net is connected to gate of the MOSFET it
can damage dielectric property of the gate and gate may conduct causing damage t
o the MOSFET. This is antenna problem.
Decrease the length of the net by providing more vias and layer jumping.
Insert antenna diode.
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15)What is signal integrity? How it affects Timing?
Answer:
IR drop, Electro Migration (EM), Crosstalk, Ground bounce are signal integrity i
ssues.
If Idrop is more==>delay increases.
crosstalk==>there can be setup as well as hold voilation.
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16)What is IR drop? How to avoid? How it affects timing?
Answer:
There is a resistance associated with each metal layer. This resistance consumes
power causing voltage drop i.e.IR drop.
If IR drop is more==>delay increases
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17)What is EM and it effects?
Answer:
Due to high current flow in the metal atoms of the metal can displaced from its
origial place. When it happens in larger amount the metal can open or bulging of
metal layer can happen. This effect is known as Electro Migration.
Affects: Either short or open of the signal line or power line.
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18)What is latency? Give the types?
Answer:
Source Latency
It is known as source latency also. It is defined as "the delay from the clock o
rigin point to the clock definition point in the design".
Delay from clock source to beginning of clock tree (i.e. clock definition point)
.
The time a clock signal takes to propagate from its ideal waveform origin point
to the clock definition point in the design.
Network latency
It is also known as Insertion delay or Network latency. It is defined as "the de
lay from the clock definition point to the clock pin of the register".
The time clock signal (rise or fall) takes to propagate from the clock definitio
n point to a register clock pin.
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19)What is 'footprint' in the standard cell synopsys timing library .lib? Why th
ey are used? (They are same for all the stdcell with similar functionality)
Answer:
They are the same for cells with the same function because it makes it easier fo
r a physical synthesis tool to swap cells of the same function to meet timing an
d slew. Without that the tool would have to verify the function of the cell each
time it wanted to change the cell.
Foot prints are generally used while optimizing ,upsizing or downsizing,, so too
l will replace any cell with similar foot print, if two std cells which have sam
e foot print, they should be logically same i,e functionality and no of i.os, th
en tool can use them for optimizations, if footprint is inconsistent, then the o
ptimizations may result in invalid data
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20) What is DFM (Design for Manufacturability)?
Answer:
High-yielding, state of the art designs in VLSI technology are extremely challen
ging due to miniaturization as well as product complexity. The design methodolog
y called design for manufacturability (DFM) includes a set of techniques to modi
fy the design of integrated circuits (IC) in order to make them more manufactura
ble, i.e., to improve their functional yield, parametric yield, or their reliabi
lity