Digital Logic Design

Topic 14: Vending Machine Design

Problem
Objectives
• To design a Vending Machine Controller
– Design the state diagram
– Design the state table
– Write the VHDL code
• Simulate/test each module

11/6/2007 2
Design Description/Specifications
• Vending Machine Controller
1. The machine takes quarters only (Qi)
2. The machine can dispense:
1. Water: 75 cents (W)
2. Cola: 50 cents (C)
3. Beer: 50 cents (B)
3. The machine has a Coin Return button (Cr)
4. Only one input may be active at a time
5. A product can be dispensed in one clock cycle
6. If more than 75 cents is inserted, the money is
automatically returned
7. If no inputs are active, the state machine stays in the
current state
8. Outputs:
1. CRo: Coin Return Out (all money in the machine)
2. Wo: Water Out
3. Co : Cola Out
4. Bo : Beer Out
5. Qo : Quarter Out

11/6/2007 3
 FSM Design Steps
1. Obtain the specifications of the desired circuit 9
2. Derive the states of the machine and develop a state
diagram
1. Should show all possible states
2. Provide the conditions for which the circuit moves from one state to
the next
3. Develop the state table from the state diagram
4. Decide on the number of state variables needed to
represent all states
1. Minimize the number of states if possible
5. Choose the type of flip-flops that will be used in the
implementation
1. Derive the next-state logic expressions to develop the Input Logic
Circuit
2. Derive the logic expressions for the Output Logic Circuit
6. Implement the design
11/6/2007 4
State Diagram
Reset 1. The machine takes quarters only (Qi)
2. The machine can dispense:
1. Water: 75 cents (W)
A 2. Cola: 50 cents (C)
C 3. Beer: 50 cents (B)
Qi 3. The machine has a Coin Return button (Cr)
CRo
4. Only one input may be active at a time
5. A product can be dispensed in one clock cycle
B Cr 6. If more than 75 cents is inserted, the money is
automatically returned
Qi Cr
7. If no inputs are active, the state machine stays in the
current state
Cr
D 8. Outputs: All produce a pulse that activates the release
C mechanism:
Qi
E 1. CRo: Coin Return Out (all money in the machine)
Co 2. Wo: Water Out
C
K G 3. Co : Cola Out
Qo B 4. Bo : Beer Out
F B 5. Qo : Quarter Out
W
Bo Qi

H I
Wo Qo
J
Qo

11/6/2007 5
State Diagram
Reset Will this work?
If nothing has happened, or if the machine has been reset,
the machine is in state A
A
Qi
C
CRo

B Cr

Qi Cr
Cr
D
C Qi
E
Co
C
K G
Qo B
F B W
Bo Qi

H I
Wo Qo
J
Qo

11/6/2007 6
State Diagram
Reset If we input a quarter, the machine goes to state B (25 cents)

A
Qi
C
CRo

B Cr

Qi Cr
Cr
D
C Qi
E
Co
C
K G
Qo B
F B W
Bo Qi

H I
Wo Qo
J
Qo

11/6/2007 7
State Diagram
Reset If we input a quarter, the machine goes to state B (25 cents)

We can now:
A Do nothing (stay in State B)
Qi
C Hit the Coin Return (Go to state C and return the money)
CRo Insert a quarter (Go to state D and wait)

B Cr

Qi Cr
Cr
D
C Qi
E
Co
C
K G
Qo B
F B W
Bo Qi

H I
Wo Qo
J
Qo

11/6/2007 8
State Diagram
Reset If the machine is in state D (50 cents)

We can:
A Do nothing (stay in State D)
Qi
C Hit the Coin Return (Go to state C and return the money)
CRo Select a cola (go to state E, output a cola, then go to A)
Select a beer (go to state F, output a beer, then go to A)
Insert a quarter (75 cents - Go to state G and wait)
B Cr

Qi Cr
Cr
D
C Qi
E
Co
C
K G
Qo B
F B W
Bo Qi

H I
Wo Qo
J
Qo

11/6/2007 9
State Diagram
Reset If the machine is in state G (75 cents)

We can:
A Do nothing (stay in State G)
Qi
C Hit the Coin Return (Go to state C and return the money)
CRo Select a cola (go to state K, return a quarter, and then go to
state E, output a cola, then go to A)
Select a beer (go to state J, return a quarter, and then go to
B Cr state F, output a beer, then go to A)
Insert a quarter (return the quarter – too much money - Go
Qi Cr back to state G and wait)
Cr Select a water (go to state H, output a water, then go to
D state A)
C Qi
E
Co
C
K G
Qo B
F B W
Bo Qi

H I
Wo Qo
J
Qo

11/6/2007 10
State Diagram
Reset It will work, but we have 3 different states (I, J, and K) that
output a quarter.
A For a Moore machine, this is necessary, because each
Qi
C state then goes to a different state
CRo I ->G
J->F
K->E
B Cr

Qi Cr
Cr
D
C Qi
E
Co
C
K G
Qo B
F B W
Bo Qi

H I
Wo Qo
J
Qo

11/6/2007 11
State Diagram
Reset It will work, but we have 3 different states (I, J, and K) that
output a quarter.
A For a Moore machine, this is necessary, because each
Qi
C state then goes to a different state
CRo
But, if the input (B, C or Qi) is associated with state G as
well as the output (Qo), as in Mealy Machines, then we do
B Cr not need the three states (I, J, and K)

Qi Cr This is a simpler design!

Cr
D
C Qi
E
Co
C/Qo G
B B/Qo W Qi/Qo
F
Bo H
Wo

11/6/2007 12
 FSM Design Steps
1. Obtain the specifications of the desired circuit 9
2. Derive the states of the machine and develop a state 9
diagram
1. Should show all possible states
2. Provide the conditions for which the circuit moves from one state to
the next
3. Develop the state table from the state diagram
4. Decide on the number of state variables needed to
represent all states
1. Minimize the number of states if possible
5. Choose the type of flip-flops that will be used in the
implementation
1. Derive the next-state logic expressions to develop the Input Logic
Circuit
2. Derive the logic expressions for the Output Logic Circuit
6. Implement the design
11/6/2007 13
State Table
Reset We have:
8 states (3 state bits)
5 inputs (Cr, Qi, C, B, or W)
A 5 outputs (CRo, Qo, Wo, Bo, and Co)
Qi
C
CRo

B Cr

Qi Cr
Cr
D
C Qi
E
Co
C/Qo G
B B/Qo W Qi/Qo
F
Bo H
Wo

11/6/2007 14
 FSM Design Steps
1. Obtain the specifications of the desired circuit 9
2. Derive the states of the machine and develop a state 9
diagram
1. Should show all possible states
2. Provide the conditions for which the circuit moves from one state to
the next
3. Develop the state table from the state diagram 9
4. Decide on the number of state variables needed to
represent all states
1. Minimize the number of states if possible
5. Choose the type of flip-flops that will be used in the
implementation
1. Derive the next-state logic expressions to develop the Input Logic
Circuit
2. Derive the logic expressions for the Output Logic Circuit
6. Implement the design
11/6/2007 15
 VHDL Code: Entity
library
libraryIEEE;
IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use
useIEEE.STD_LOGIC_ARITH.ALL;
IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity
entityVend
Vendisis
Port
Port (Clock
( Clock: :ininstd_logic;
std_logic;
Reset
Reset: :ininstd_logic;
std_logic;
Cr,
Cr,Qi,
Qi,Ci,Ci,Bi,
Bi,Wi
Wi: :ininstd_logic;
std_logic;
CRo,
CRo, Qo, Co, Bo, Wo :out
Qo, Co, Bo, Wo : outstd_logic;
std_logic;
Q:Q:out
outStd_Logic_Vector
Std_Logic_Vector(2(2DOWNTO DOWNTO0));0));
end Vend;
end Vend;

11/6/2007 16
 VHDL Code: Architecture
architecture Behavioral of Vend is
architecture Behavioral of Vend is
TYPE State_type IS (A, B, C, D, E, F, G, H) ;
TYPE State_type IS (A, B, C, D, E, F, G, H) ;
SIGNAL y : State_type ;
SIGNAL y : State_type ;
begin
begin
Process
Process
Begin
Begin
If Reset = '0' then
If Reset = '0' then
y <= A; CRo <= '0'; Qo <= '0'; Co <= '0'; Bo <= '0'; Wo <= '0'; Q <= "000"; end if;
y <= A; CRo <= '0'; Qo <= '0'; Co <= '0'; Bo <= '0'; Wo <= '0'; Q <= "000"; end if;
Wait Until falling_edge (Clock);
Wait Until falling_edge (Clock);
CASE y IS
CASE y IS
WHEN A => Q <= "000";
WHEN A => Q <= "000";
If Qi = '1' then y <= B; end if;
If Qi = '1' then y <= B; end if;
WHEN B => Q <= "001";
WHEN B => Q <= "001";
If Cr = '1' then y <= C;
If Cr = '1' then y <= C;
elsif Qi = '1' then y <= D; end if;
elsif Qi = '1' then y <= D; end if;
WHEN C => Q <= "010";
WHEN C => Q <= "010";
CRo <= '1' after 0 ns, '0' after 200 ns;
CRo <= '1' after 0 ns, '0' after 200 ns;
y <= A;
y <= A;
WHEN D => Q <= "011";
WHEN D => Q <= "011";
If Cr = '1' then y <= C;
If Cr = '1' then y <= C;
elsif Qi = '1' then y <= G;
elsif Qi = '1' then y <= G;
elsif Ci = '1' then y <= E;
elsif Ci = '1' then y <= E;
elsif Bi = '1' then y <= F; end if;
elsif Bi = '1' then y <= F; end if;
WHEN E => Q <= "100";
WHEN E => Q <= "100";
Co <= '1' after 0 ns, '0' after 200 ns; y <= A;
Co <= '1' after 0 ns, '0' after 200 ns; y <= A;
WHEN F => Q <= "101";
WHEN F => Q <= "101";
Bo <= '1' after 0 ns, '0' after 200 ns; y <= A;
Bo <= '1' after 0 ns, '0' after 200 ns; y <= A;
WHEN G => Q <= "110";
WHEN G => Q <= "110";
If Cr = '1' then y <= C;
If Cr = '1' then y <= C;
elsif Qi = '1' then y <= G; Qo <= '1' after 0 ns, '0' after 200 ns;
elsif Qi = '1' then y <= G; Qo <= '1' after 0 ns, '0' after 200 ns;
elsif Ci = '1' then y <= E; Qo <= '1' after 0 ns, '0' after 200 ns;
elsif Ci = '1' then y <= E; Qo <= '1' after 0 ns, '0' after 200 ns;
elsif Bi = '1' then y <= F; Qo <= '1' after 0 ns, '0' after 200 ns;
elsif Bi = '1' then y <= F; Qo <= '1' after 0 ns, '0' after 200 ns;
elsif Wi = '1' then y <= H; end if;
elsif Wi = '1' then y <= H; end if;
WHEN H => Q <= "111";
WHEN H => Q <= "111";
Wo <= '1' after 0 ns, '0' after 200 ns; y <= A;
Wo <= '1' after 0 ns, '0' after 200 ns; y <= A;
END CASE ;
END CASE ;
end process;
end process;
end Behavioral;
11/6/2007
end Behavioral; 17
 Simulation/Test
This is the 1st Test Bench

2 quarters in, buy a beer

2 quarters in, buy a cola
3 quarters in, buy water
1 quarter in, hit Coin Return

11/6/2007 18
 Simulation/Test: Results
1st set of results

2 quarters in, buy a beer, a beer is dispensed

2 quarters in, buy a cola, a cola is dispensed
3 quarters in, buy water, a water is dispensed
1 quarter in, hit Coin Return, a quarter is returned

11/6/2007 19
 Simulation/Test 2
This is the 2nd Test Bench

5 quarters in, buy a beer

4 quarters in, buy a cola
0 quarters in, buy water
0 quarter in, hit Coin Return

11/6/2007 20
 Simulation/Test: Results 2
2nd set of results

RED:
5 quarters in: after 3, they start being returned

11/6/2007 21
 Simulation/Test: Results 2
2nd set of results

RED:
5 quarters in: after 3, they start being returned

BLUE:
Buy a beer: another quarter is returned and a beer is dispensed

11/6/2007 22
 Simulation/Test: Results 2
2nd set of results

RED:
4 more quarters in: after 3, they start being returned

11/6/2007 23
 Simulation/Test: Results 2
2nd set of results

RED:
4 more quarters in: after 3, they start being returned

YELLOW:
Buy a cola, a quarter is returned and a cola is dispensed

11/6/2007 24
 Simulation/Test: Results 2
2nd set of results

Magenta:
No quarters in: Buy water, nothing happens

Green:
Hit Coin Return, nothing happens

11/6/2007 25
Summary
• In this topic we:
– Designed a state machine that controls a
vending machine
• Designed the state diagram
• Designed the state table
• Wrote the VHDL code
– Looked at two new keywords
» falling_edge
» after Xns
– Simulated and tested each module

11/6/2007 26