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• Introduction
• Test Pattern Generation
• Test Response Analysis
• BIST Architectures
• Scan-Based BIST
TPG
ORA
• Exhaustive testing
• Pseudorandom testing
– Weighted and Adaptive TG
• Pseudoexhaustive testing
– Syndrome driver counter
– Constant-weight counter
– Combined LFSR and shift register
– Combined LFSR and XOR
– Cyclic LFSR
Z
Z
F/F F/F 0 1 1
S1 0 0 1
S1 1 0
S2 1 0 0
S2 0 1
S3 0 1 0
S1 1 0
S4 1 0 1
:
S5 1 1 0
S6 1 1 1
S7 = S0 0 1 1
:
Z=0101… Z=1100101…
2 states 7 states
Built-in self test.8
Two Types of LFSRs
C 1 C2 C n-1 C n = 1
D Q
Cn =1 Cn-1 Cn-2 C 1
D Q
Q1 Q2 Qn
Built-in self test.9
Mathematical Operations over GF(2)
• Multiplication (• ) • 0 1
0 0 0
• Addition ( ⊕ or simply +) 1 0 1
⊕ 0 1
0 0 1
1 1 0
Example: = = =
− = − = − =
if = − • + − • + − •
then
= + + =
Built-in self test.10
Analysis of LFSR using Polynomial
Representation
∞
= + + + + + = ∑
• Generating function :
=
Let =
be output sequence of an LFSR of type1
= ∑ −
=
= = =
∞
= ∑ ∑ − −
= =
∞
= ∑ − − + + − − + ∑
= =
∑
− −
+ + − −
= =
+ ∑
∴ =
depends on initial state and feedback
coefficients
Built-in self test.13
Denominator
= + + + +
is called the characteristic polynomial of the
LFSR
Example:
3 2 1 0
= + +
sequence
• Definition: The characteristic polynomial associated
with a maximum length sequence is a primitive
polynomial
• Theorem: # of primitive polynomials for an n-stage
LFSR is given by
λ = φ −
where
φ = ∏
−
Built-in self test.15
Primitive Polynomial
• # primitive polynomials of degree n N λ
1 1
2 1
4 2
8 16
16 2048
• Some primitive polynomials 32 67108864
1: 0 13: 4 3 1 0 25: 3 0
2: 1 0 14: 12 11 1 0 26: 8 7 1 0
3: 1 0 15: 1 0 27: 8 7 1 0
4: 1 0 16: 5 3 2 0 28: 3 0
5: 2 0 17: 3 0 29: 2 0
6: 1 0 18: 7 0 30: 16 15 1 0
7: 1 0 19: 6 5 1 0 31: 3 0
8: 6 5 1 0 20: 3 0 32: 28 27 1 0
9: 4 0 21: 2 0 33: 13 0
10: 3 0 22: 1 0 34: 15 14 1 0
11: 2 0 23: 5 0 35: 2 0
12: 7 4 3 0 24: 4 3 1 0 36: 11 0
Built-in self test.16
Primitive Polynomial (Cont.)
• Characteristic of maximum-length sequence:
– Pseudorandom though deterministic and
periodic
– # 1’s = # 0’s + 1
= + +
1 1 0 0
1 0 0 1
0 0 1 0
0 1 0 0
1 0 0 0 (repeat)
3 2 1 0
• Sequence becomes:
• Using “pseudorandom”
e.g. generate 232 pattern only
• Partitioning
Circuit
under
test (CUT)
• Using pseudo-exhaustive
Input Output
test Circuit response Signature
Data S( R’)
sequence T under sequence R’
Compression
test
unit
(CUT)
Error
indicator
Comparator
Correct Signature S( R0 )
• Ones Count
• Transition Count
• Parity Checking
• Syndrome Checking
• Signature Analysis
• C: single-output circuit
• R: output response =
• 1C(R) = # ones in = ∑
s-a-0 fault f2
x1 11110000
11001100 10000000 = R2
x2 11000000 = R1 Signature (ones count)
Counter
10000000 = R0
z
x3
10101010 =
Raw output
=
Input test
s-a-1 fault f1
test response =
pattern
sequence T
Signature
10000000 = R2 (transition count)
Counter
11000000 = R1
T Network 10000000 = R0 =
D Q
=
=
− −
• =
−
• Does not guarantee the detection of single-bit
errors
−
• Prob. (single-bit error masked) =
−
• Prob. (masking error) π
Built-in self test.27
Parity-check Compression
Signature
00000000 = R2
11000000 = R1 (parity)
10000000 = R0
D Q
T Network =
=
Clock =
random
test CUT
pattern
Counter /
Syndrome
+/- 0 1 * 0 1
0 0 1 0 0 0
1 1 0 1 0 1
• Linear ckt.:
Response of linear combination of inputs
= Linear combination of responses of individual
inputs
+ = +
Built-in self test.30
Use LFSR as Signature Analyzer
• Single-input LFSR
… …
⊕ Internal Type LFSR
• Initial state =
• Final state
= + or = +
: The remainder, or the signature
Built-in self test.31
Signature Analyzer (SA)
Input sequence:
1 1 1 1 0 1 0 1 (8 bits)
( ) = + + + + + 1 ( ) = 1 + + +
Time Input stream Register contents Output stream
12345
0 10101111 00000 Initial state
1 1010111 10000
: : :
5 101 01111
6 10 00010 1
7 1 00001 01
8 Remainder 00101 101
Quotient
Remainder ( ) = + () = 1+
Built-in self test.32
Signature Analyzer (SA) (Cont.)
+ + +
× +
= + + +
+ = + + + + + =
D Q
Cn Cn-1 Cn-2 C 1
N N
R R*
… ⊕ …
Ci
i D Q D Q
C
⊕ I
i A B
Normal: CK, B
Shift: S/T=0, A, B
MISR: S/T=1, A, B
CUT
D D
I I
TPG ORA
S S
T T
CUT
BIST
controller
TPG ORA
CUT
TPG ORA
• Distributed
• Embedded
• Combinational “Kernels”
• Chip level
• “Clouding” of circuit
• Registers based description of circuit
• BILBO registers
...
B2
Si 0
MUX
D Q D Q D Q D Q
1
...
Q Q Q Q S0
Q1
Q2 Qn-1 Qn
...
B1 B2 BILBO
0 0 shift register
0 1 reset
1 0 MISR (input ∗ constant ∗ LFSR)
1 1 parallel load (normal operation)
Built-in self test.46
Applications of BILBO
• Bus-oriented structure
BUS
R11 R1n
C1 … Cn
R21 R2n
BILBO
C2
…
BILBO
Cn
…
R1
C
C1
BILBO
R2
MISR or TPG ? R2 ?
Using CBILBO
+ +
TPG mode: C1, A2, B=0
MISR mode: C1, A1, C2=0
CUT
OR SA
CUT
1 0 0
S-a-0
1 0 0
0 1 0
1 0 1
1 1 0
1 1 1
0 1 1
0 0 1
32 bits
….. …..
S-a-0
Or
S-a-1
S-a-0