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Keywords Power MOSFET, single-shot, avalanche, ruggedness, safe operating
condition
Abstract Power MOSFETs are normally measured based on single-shot
Unclamped Inductive Switching (UIS) avalanche energy. This note
describes in detail the avalanche ruggedness performance, fundamentals
of UIS operation and appropriate quantification method for the safe
operating condition.
NXP Semiconductors AN10273
Power MOSFET single-shot/repetitive avalanche ruggedness rating
Revision history
Rev Date Description
02 20090327 Updated
Modifications: • The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
01 20030901 Initial version
Contact information
For more information, please visit: http://www.nxp.com
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AN10273_2 © NXP B.V. 2009. All rights reserved.
1. Introduction
Electronic applications have progressed significantly in recent years and have inevitably
increased the demand for an intrinsically rugged power MOSFET. Device ruggedness is
defined by the capacity of a device to sustain an avalanche current during an unclamped
inductive load switching event. However, the avalanche ruggedness performance of a
power MOSFET is normally measured within the industry as a single-shot Unclamped
Inductive Switching (UIS) avalanche energy or EAS. Whilst this provides an easy and quick
method of quantifying the robustness of a MOSFET in avalanche, it does not necessarily
reflect the true device avalanche capability (see Ref. 1, Ref. 2 and Ref. 3) in an
application.
This note explains the fundamentals of UIS operation and reviews the appropriate method
of quantifying the safe operating condition for a power MOSFET subjected to UIS
operating condition. The note also covers the much-discussed repetitive avalanche
ruggedness capability and how this operation can be quantified to operate safely.
L
drain
2
gate
001aaj764
Fig 1. Unclamped inductive load test circuit for MOSFET ruggedness evaluation
The peak load current passing through the MOSFET before turn OFF will be the
single-shot avalanche current (IAS) of the UIS event as illustrated in Figure 4. The rate at
which the avalanche current decays is dependent on inductor value and can be
determined by:
dI AS V BR – V S
----------- = – ---------------------- (2)
dt AV L
The peak avalanche power (PAV(pk)) dissipated in the MOSFET shown in Figure 5 is a
product of the breakdown voltage (VBR) and the avalanche current (IAS) as shown in
Figure 3 and Figure 4, respectively. The avalanche energy dissipated is the area under
the PAV waveform and can be estimated from the following expression:
P AV ( pk ) × t AV
E AS = ---------------------------------
- (3)
2
or
1 V BR
E AS = --- ⋅ ---------------------- ⋅ LI AS
2 (4)
2 V BR – V S
τ
dZ th ( τ – t )
T jrise ( τ ) = ∫ P AV ( t ) ---------------------- dt (5)
dt
0
where Zth is the power MOSFET transient thermal impedance. Alternatively, the maximum
Tjrise can be approximated by:
2
T jrise ( max ) ≈ --- P av ( pk ) Z th ( t ⁄ 2 ) (6)
3 AV
where Z th ( t ⁄ 2) is the device transient thermal impedance at half the tAV period.
AV
The maximum junction temperature resulting from the avalanche event will therefore be:
VDS
VGS VBR
BVDSS
VS VS
ON OFF
ID P
IAS PAV(pk)
area in PAV triangle
= avalanche energy
(EAS) dissipated
Fig 4. Current passing through MOSFET, ID Fig 5. Peak avalanche power, PAV(pk)
Tj
Tj(max)
Tjrise(max)
Tj
tAV time
001aaj769
Blackburn (see Ref. 2) has discussed a general guideline in detail on the appropriate
method of quantifying the single-shot avalanche capability of a device by taking avalanche
current and initial junction temperature into consideration. Safe operation for a device
single-shot UIS event can be defined by a maximum allowed avalanche current as a
function of avalanche time. The maximum allowed avalanche current is set so that a safe
maximum junction temperature, Tj(max) of 175 °C, is never exceeded. Using Equation 7,
Figure 7 can be plotted.
001aaj770
102
Tj = 25 °C
Iav
(A)
Tj = 150 °C
10
1
10−2 10−1 1 10
tav (ms)
Figure 7 shows the SOAR curves of a device single-shot avalanche capability. The 25 °C
junction temperature curve shows the maximum allowable IAS for a given tAV at an initial
Tj of 25 °C. This maximum IAV will give rise to a maximum junction temperature,
Tjrise(max) of 150 °C resulting in a Tj(max) of 175 °C.
The area under the SOAR curve will be the safe operating area (SOA). Similarly the
150 °C junction temperature curve will be the maximum operating limit for an initial Tj of
150 °C. The IAS(max) will induce a Tjrise(max) of 25 °C resulting in a Tj(max) of 175 °C. Again
the area under the curve will be the SOA.
Due to the traumatic nature of the avalanche event, a repetitive avalanche operation can
be hazardous for a MOSFET, even when individual avalanche events are well below the
single-shot UIS rating. This type of operation involves additional parameters such as the
frequency, duty cycle and the thermal resistance (Rth) of the application during the
repetitive avalanche event. However, it is possible to derate the single-shot rating to define
a repetitive avalanche safe operating area.
To obtain the average repetitive avalanche power dissipated (PAV(R)) resulting from the
repetitive UIS operation as shown in Figure 10. It is necessary to first calculate the EAS for
a single avalanche event using Equation 3. Subsequently substituting EAS into the
expression gives:
P AV ( R ) = E AS × f (8)
VGS
VBR
BVDSS
IAR VS
tAV time
time
001aaj771 001aaj772
Fig 8. Gate pulse, VGS Fig 9. MOSFET drain-source voltage, VDS and
repetitive avalanche current, IAR
P Tj
∆Tj
To Tj(avg)
PAV(pk)
Tmb
PAV(R)
tAV time tAV time
001aaj773 001aaj774
Fig 10. Repetitive avalanche power PAV(R) Fig 11. Transient junction temperature components of
MOSFET during repetitive avalanching
The temperature (To) comprises the mounting base temperature (Tmb) and the
temperature rise resulting from any ON state conduction (Tcond).
T O = T mb + T cond (9)
In addition there is a steady-state average junction temperature rise (∆Tj) resulting from
the average repetitive avalanche power loss.
AN10273_2 © NXP B.V. 2009. All rights reserved.
∆T j = P AV ( R ) × R th ( j – amb ) (10)
where Rth(j-amb) is the thermal resistance of the device in the application. The summation
of equations Equation 9 and Equation 10 will give the average junction temperature, Tj(avg)
of a power MOSFET in repetitive UIS operation.
T j ( avg ) = T O + ∆T j (11)
Figure 12 shows the avalanche SOAR curves for BUK764R0-55B where ‘Rep. Ava’
represents the repetitive avalanche SOAR curve.
001aaj775
102
Tj = 25 °C
Iav
(A)
Tj = 150 °C
10
Rep. Ava
1
10−2 10−1 1 10
tav (ms)
Fig 12. Single-shot (initial Tj = 25 °C and 150 °C) and repetitive (Rep. Ava) avalanche
ruggedness SOAR curves of BUK764R0-55B limited to a Tj(max) of 175 °C and
Tj(avg) of 170 °C, respectively
The two conditions which must be satisfied for safe operation of a power MOSFET under
repetitive avalanching mode are as follows:
5. Conclusion
Power MOSFETs can sustain single-shot and repetitive avalanche events. Simple design
rules and SOAR regions have been provided.
6. Examples
The following examples examine cases of avalanche operation acceptance evaluation.
Based upon the above calculations, the operating condition is acceptable if the device
Tj < 50 °C.
4. Calculate the average ∆Tj rise from repetitive avalanche (∆Tj) using Equation 10
(∆Tj = 135 °C).
5. Determine the average junction maximum temperature in repetitive avalanche
operation (Tj(avg)) using Equation 11 (Tj(avg) = 235 °C). Therefore, condition 2 is not
achieved.
Based on the above calculations, the operating conditions satisfied the first but not the
second requirement for safe repetitive avalanche operation. This was because the
maximum Tj(avg) exceeded 170 °C.
To make the above operation viable, the design engineer has to achieve the 2nd condition
by reducing the Tj(avg). This can be achieved simply by improving the heat sinking of the
device. Reducing the Rth(j-amb) from 5 K/W to 2.5 K/W will give a Tj(avg) of 167.5 °C
satisfying condition 2 for safe repetitive avalanche operation.
7. Appendix A
The following table describes the symbols used throughout this application note.
8. References
[1] Turn-off Failure of Power MOSFETs — D.L. Blackburn, Proc. 1985 IEEE Power
Electronics Specialists Conference, pp 429-435, June 1985.
[2] Power MOSFET Failure Revisited — D.L. Blackburn, Proc. 1988 IEEE Power
Electronics Specialists Conference, pp 681-688, April 1988.
[3] Boundary of Power-MOSFET, Unclamped Inductive-Switching (UIS)
Avalanche-Current Capability — Rodney R. Stoltenburg, Proc. 1989 Applied
Power Electronics Conference, pp 359-364, March 1989.
9. Legal information
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Draft — The document is a draft version only. The content is still under
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internal review and subject to formal approval, which may result in
to result in personal injury, death or severe property or environmental
modifications or additions. NXP Semiconductors does not give any
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Applications — Applications that are described herein for any of these
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10. Figures
Fig 1. Unclamped inductive load test circuit for MOSFET Fig 8. Gate pulse, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ruggedness evaluation . . . . . . . . . . . . . . . . . . . . . .3 Fig 9. MOSFET drain-source voltage, VDS and repetitive
Fig 2. Gate pulse, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . .5 avalanche current, IAR . . . . . . . . . . . . . . . . . . . . . . 7
Fig 3. MOSFET Drain-Source Voltage, VDS . . . . . . . . . . .5 Fig 10. Repetitive avalanche power PAV(R) . . . . . . . . . . . . 7
Fig 4. Current passing through MOSFET, ID . . . . . . . . . .5 Fig 11. Transient junction temperature components of
Fig 5. Peak avalanche power, PAV(pk) . . . . . . . . . . . . . . .5 MOSFET during repetitive avalanching. . . . . . . . . 7
Fig 6. Transient junction temperature profile of MOSFET Fig 12. Single-shot (initial Tj = 25 C and 150 C) and
during an avalanche event . . . . . . . . . . . . . . . . . . .5 repetitive (Rep. Ava) avalanche ruggedness SOAR
Fig 7. Single-shot avalanche ruggedness SOAR curves of curves of BUK764R0-55B limited to a Tj(max) of
BUK764R0-55B limited to a Tj(max) of 175 C . . . . .6 175 C and Tj(avg) of 170 C, respectively. . . . . . . . . 8
11. Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Understanding power MOSFET single-shot
avalanche events . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Single-shot UIS operation. . . . . . . . . . . . . . . . . 3
2.1.1 Single-shot UIS waveforms. . . . . . . . . . . . . . . . 5
2.2 Single-shot avalanche ruggedness rating. . . . . 5
3 Understanding power MOSFET repetitive
avalanche events . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Repetitive UIS operation . . . . . . . . . . . . . . . . . . 7
3.1.1 Repetitive UIS waveforms. . . . . . . . . . . . . . . . . 7
3.2 Temperature Components . . . . . . . . . . . . . . . . 7
4 Repetitive avalanche ruggedness rating . . . . . 8
5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.1 Single-shot avalanche case . . . . . . . . . . . . . . . 9
6.1.1 Calculation steps . . . . . . . . . . . . . . . . . . . . . . . 9
6.2 Repetitive avalanche case . . . . . . . . . . . . . . . . 9
6.2.1 Calculation steps . . . . . . . . . . . . . . . . . . . . . . . 9
7 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
9.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
9.2 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
9.3 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
10 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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