HDL Lab Manual

COMBINATIONAL CIRCUITS IMPLEMENTATION USING VHDL

1. LOGIC GATES:       

TRUTH TABLE:
         
a b c(and) d (or) e(not) f(nand )  g(nor) h (xor) i(xnor)  
0 0              
0 1              
1 0              
1 1              

VHDL VERILOG
library IEEE; module gate1(a,b,c,d,e,f,g,h,i);
use IEEE.STD_LOGIC_1164.ALL; input a, b;
use IEEE.STD_LOGIC_ARITH.ALL; output c,d,e,f,g,h,i;
use IEEE.STD_LOGIC_UNSIGNED.ALL; assign c=a & b;
entity logicgate is                                             assign d=a | b;
    Port ( a,b : in std_logic;            assign e= ~a;                                       
c,d,e,f,g,h,i : out std_logic); assign f= ~(a & b);
end logicgate;                            assign g= ~(a | b);
architecture Behavioral of logicgate is assign h= a ^ b;
begin assign i=  ~( a ^ b);   
c<= a and b;                                                    endmodule
d<= a or b;
e<= not a
f<= a nand b;
g<= a nor b;
h<= a xor b;
i<= a xnor b;
end Behavioral;

Dept. of E&C, Ekalavya Institute of Tech. 8

HDL Lab Manual

2. HALF ADDER:

TRUTH TABLE:
 
a b sum(s) carry(c) EXPRESSIONS:     S = A  B
0 0 0 0                                               C = AB
0 1 1 0
1 0 1 0
1 1 0 1

Dataflow:

VHDL VERILOG
library IEEE; module half(a,b,s,c);
use IEEE.STD_LOGIC_1164.ALL;  input a,b;
use IEEE.STD_LOGIC_ARITH.ALL;  output s,c;
use assign s=a ^ b;
IEEE.STD_LOGIC_UNSIGNED.ALL; assign c=a & b;
entity half is endmodule
    Port ( a,b : in  std_logic;  
               s,c : out  std_logic);
end half;
architecture dataflow of half is
begin
s<= a xor b;
c <= a and b;
end dataflow;

Behavioral :

VHDL VERILOG
library IEEE; module half(a,b,s,c);
use IEEE.STD_LOGIC_1164.ALL; input a,b;
use IEEE.STD_LOGIC_ARITH.ALL; output s,c;
use IEEE.STD_LOGIC_UNSIGNED.ALL; reg s,c;
entity half is always@ (a,b)
    Port ( a,b : in std_logic; begin
            s,c : out std_logic); s=a ^ b;
end half; c=a & b;
architecture Behavioral of half is end
begin endmodule
process(a,b)  
begin
s<= a xor b;
c <= a and b;
end process;
end Behavioral;

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HDL Lab Manual

Logic Circuit for Half Adder:

Structural:
VHDL VERILOG
library IEEE; module half(a,b,s,c);
use IEEE.STD_LOGIC_1164.ALL; input a,b;
use IEEE.STD_LOGIC_ARITH.ALL; output s,c;
use IEEE.STD_LOGIC_UNSIGNED.ALL; xor u1(s,a,b);
entity half is and u2(c,a,b);
    Port ( a,b : in  std_logic; endmodule
             s,c : out  std_logic);  
end half;
architecture structural of half is  
component xor1
 port (x,y:in std_logic;
            z:out std_logic);
 end component;
 component and1
 port (l,m:in std_logic;
            n:out std_logic)
end component;
begin
u1:xor1 port map(a,b,s);
u2:and1 port map(a,b,c);
end structural;

Note: Separate Entity and Architecture should be written for each component along with
library and package statement.

Dept. of E&C, Ekalavya Institute of Tech. 10

HDL Lab Manual

3. FULL ADDER:
TRUTH TABLE:

a b c s cout
EXPRESSIONS:   S = A  B  Ci
0 0 0 0 0                                               CO = AB+BC+CA

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Dataflow:
VHDL VERILOG
  library IEEE; module half(a,b,ci,s,co);
use IEEE.STD_LOGIC_1164.ALL; input a,b,ci;
use IEEE.STD_LOGIC_ARITH.ALL; output s,co;
use IEEE.STD_LOGIC_UNSIGNED.ALL; assign s=a^b^ci;
entity full is assign co=(a & b) | (b & ci) | (ci & a);
port ( a,b,c : in  std_logic; endmodule
           s,co : out  std_logic);  
end full;  
architecture Behavioral of full is
begin
s<= a xor b xor c;
co <= (a and b) or (b and c) or (c and a);
end Behavioral;

Behavioral:
VHDL VERILOG
  library IEEE; module half(a,b,ci,s,co);
use IEEE.STD_LOGIC_1164.ALL; input a,b,ci;
use IEEE.STD_LOGIC_ARITH.ALL; output s,co;
use IEEE.STD_LOGIC_UNSIGNED.ALL; reg s,co;
entity full is always@ (a,b,ci)
port ( a,b,c : in  std_logic; begin
           s,co : out  std_logic); s=a^b^ci;
end full; co=(a & b) | (b & ci) | (ci & a);
architecture Behavioral of full is end
begin endmodule
process(a,b,c)  
begin  
s<= a xor b xor c;
co <= (a and b) or (b and c) or (c and a);
end process;
end Behavioral;

Dept. of E&C, Ekalavya Institute of Tech. 11

HDL Lab Manual

Logic Circuit for Full Adder:

Structural:
VHDL VERILOG
  library IEEE; module full(a,b,cin, s,cout);           
use IEEE.STD_LOGIC_1164.ALL; input a,b,cin;
use IEEE.STD_LOGIC_ARITH.ALL; output s,cout;
use IEEE.STD_LOGIC_UNSIGNED.ALL; wire s1,s2,s3,s4;
entity full is xor u1(s1,a,b);
    port ( a,b,cin : in  STD_LOGIC; xor u2(s,s1,cin);
           s,cout : out  STD_LOGIC); and u3(s2,a,b);
end full; and u4(s3,b,cin);
architecture structural of full is and u5(s4,cin,a);
component xor1 or u6(cout,s2,s3,s4);
port(x,y:in std_logic; endmodule
            z:out std_logic);
end component;
component and1
port(l,m:in std_logic;
            n:out std_logic);
end component;
component or1
port(p,q,r:in std_logic;
     r:out std_logic);
end component;
signal s1,s2,s3,s4:std_logic;
begin
u1:xor1 port map(a,b,s1);
u2:xor1 port map(s1,cin,s);
u3:and1 port map(a,b,s2);
u4:and1 port map(b,cin,s3);
u5:and1 port map(cin,a ,s4);
u6:or1 port map(s2,s3,s4, cout);
end structural;

Note: Separate Entity and Architecture should be written for each component along with
library and package statement.
Dept. of E&C, Ekalavya Institute of Tech. 12
HDL Lab Manual

4:MULTIPLEXER (8:1)                                                                         

 TRUTH TABLE:

INPUTS SELECT   LINES O/P

d(7) d(6) d(5) d(4) d(3) d(2) d(1) d(0)     s(2) s(1) s(0) f

X X X X X X X 0 0 0 0 0

X X X X X X X 1 0 0 0 1

X X X X X X 0 X 0 0 1 0

X X X X X X 1 X 0 0 1 1

X X X X X 0 X X 0 1 0 0

X X X X X 1 X X 0 1 0 1

X X X X 0 X X X 0 1 1 0

X X X X 1 X X X 0 1 1 1

X X X 0 X X X X 1 0 0 0

X X X 1 X X X X 1 0 0 1

X X 0 X X X X X 1 0 1 0

X X 1 X X X X X 1 0 1 1

X 0 X X X X X X 1 1 0 0

X 1 X X X X X X 1 1 0 1

0 X X X X X X X 1 1 1 0

1 X X X X X X X 1 1 1 1

VHDL VERILOG
 library IEEE; module mux(d, s, f);
use IEEE.STD_LOGIC_1164.ALL; input [7:0] d;
use IEEE.STD_LOGIC_ARITH.ALL; input [2:0] s;
use IEEE.STD_LOGIC_UNSIGNED.ALL; output f;
entity mux is reg f;
    Port ( d : in  std_logic_vector (7 downto 0); always @ (d,s)
           s : in  std_logic_vector (2 downto 0); begin
            f : out  std_logic); case (s)
end mux; 3'b000: f=d[0];
architecture Behavioral of mux is 3'b001: f=d[1];
begin 3'b010: f=d[2];
process(d,s) 3'b011: f=d[3];
begin 3'b100: f=d[4];
case(s) is 3'b101: f=d[5];
when "000" =>f<=d(0); 3'b110: f=d[6];
when "001" =>f<=d(1); 3’b111: f=d[7];
when "010" =>f<=d(2); endcase
when "011" =>f<=d(3); end
when "100" =>f<=d(4); endmodule
when "101" =>f<=d(5);
when "110" =>f<=d(6);
when "111" =>f<=d(7);
when others=>null;
end case;
end process;
end Behavioral;

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HDL Lab Manual

5: DEMULTIPLEXER (1:8):  
TRUTH TABLE:
                                                    

SELECT   LINES I/P                                                    OUTPUT

s(2) s(1) s(0) f y(7) y(6) y(5) y(4) y(3) y(2) y(1) y(0)    

0 0 0 0 X X X X X X X 0

0 0 0 1 X X X X X X X 1

0 0 1 0 X X X X X X 0 X

0 0 1 1 X X X X X X 1 X

0 1 0 0 X X X X X 0 X X

0 1 0 1 X X X X X 1 X X

0 1 1 0 X X X X 0 X X X

0 1 1 1 X X X X 1 X X X

1 0 0 0 X X X 0 X X X X

1 0 0 1 X X X 1 X X X X

1 0 1 0 X X 0 X X X X X

1 0 1 1 X X 1 X X X X X

1 1 0 0 X 0 X X X X X X

1 1 0 1 X 1 X X X X X X

1 1 1 0 0 X X X X X X X

VHDL VERILOG
 library IEEE;  module demux (f, s, y);
use IEEE.STD_LOGIC_1164.ALL; input f;
use IEEE.STD_LOGIC_ARITH.ALL; input [2:0] s;
use IEEE.STD_LOGIC_UNSIGNED.ALL; output [7:0] y;
entity dmux is reg[7:0] y;
port(f:in std_logic; always @ (s,f)
s:in std_logic_vector(2 downto 0); begin
y:out std_logic_vector(7 downto 0)); case (s)
end demux; 3'b000:y[0]=f;
architectural behavioral of dmux is 3'b001:y[1]=f;
begin 3'b010:y[2]=f;
process(f,s) 3'b011:y[3]=f;
begin 3'b100:y[4]=f;
case(s) is 3'b101:y[5]=f;
when "000" =>y(0)<=f; 3'b110:y[6]=f;
when "001" =>y(1)<=f; 3’b111:y[7]=f;
when "010" =>y(2)<=f; endcase
when "011" =>y(3)<=f; end
when "100" =>y(4)<=f; endmodule
when "101" =>y(5)<=f;
when "110" =>y(6)<=f;
when "111" =>y(7)<=f;
when others=>null;
end case;
end process;
end behavioral;
Dept. of E&C, Ekalavya Institute of Tech. 14
HDL Lab Manual

6. a ENCODER WITHOUT PRIORITY (8:3):                  

 TRUTH TABLE:
 
INPUT OUTPUT
s(7)   s(6) s(5) s(4) s(3) s(2) s(1) s(0) y(2) y(1) y(0)
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

VHDL VERILOG
library IEEE;  module encod(y, s);
use IEEE.STD_LOGIC_1164.ALL; input [7:0]s;
use IEEE.STD_LOGIC_ARITH.ALL; output [2:0] y;         
use IEEE.STD_LOGIC_UNSIGNED.ALL; reg [2:0]y;
entity enco is always @(s)
    Port ( s : in  std_logic_vector (7 downto 0); begin
           y : out  std_logic_vector (2 downto 0)); case (s)
end enco; 8'd1:y=3'd0;
architecture Behavioral of enco is 8'd2:y=3'd1;
begin               8'd4:y=3'd2;
process(s) 8'd8:y=3'd3;
begin 8'd16:y=3'd4;
case(s) is 8'd32:y=3'd5;
when "00000001" =>y<="000"; 8'd64:y=3'd6;
when "00000010" =>y<="001"; 8’d128:y=3'd7;
when "00000100" =>y<="010"; endcase
when "00001000" =>y<="011"; end
when "00010000" =>y<="100"; endmodule
when "00100000" =>y<="101";
when "01000000" =>y<="110";
when "10000000" =>y<="111";
when others=>null;
end case;
end process;
end behavioral;
 

Dept. of E&C, Ekalavya Institute of Tech. 15

HDL Lab Manual
6. b ENCODER WITH PRIORITY (8:3):
TRUTH TABLE:

INPUT OUTPUT
i(7)   i(6) i(5) i(4) i(3) i(2) i(1) i(0) y(2) y(1) y(0)
1 X X X X X X X 1 1 1
0 1 X X X X X X 1 1 0
0 0 1 X X X X X 1 0 1
0 0 0 1 X X X X 1 0 0
0 0 0 0 1 X X X 0 1 1
0 0 1 0 0 1 X X 0 1 0
0 1 0 0 0 0 1 X 0 0 1
1 0 0 0 0 0 0 1 0 0 0

VHDL VERILOG
library IEEE;  module encod(y, i);
use IEEE.STD_LOGIC_1164.ALL; input [7:0] i;
use IEEE.STD_LOGIC_ARITH.ALL; output [2:0] y;
use IEEE.STD_LOGIC_UNSIGNED.ALL; reg [2:0] y;
entity enc is always @(i)
    Port ( i : in  std_logic_vector(7 downto 0); begin
           y : out  std_logic_vector(2 downto 0)); casex (y)
end enc; 8'b1XXXXXXX:y=3'd7;
architecture Behavioral of enc is 8'b01XXXXXX:y=3'd6;
begin 8'b001XXXXX:y=3'd5;
process(i) 8'b0001XXXX:y=3'd4;
begin 8'b00001XXX:y=3'd3;
if i(7)='1' then y<="111"; 8'b000001XX:y=3'd2;
elsif i(6)='1' then y<="110"; 8'b0000001X:y=3'd1;
elsif i(5)='1' then y<="101"; 8’b00000001:y=3'd0;
elsif i(4)='1' then y<="100"; endcase
elsif i(3)='1' then y<="011"; end
elsif i(2)='1' then y<="010"; endmodule           
elsif i(1)='1' then y<="001";
elsif i(0)='1' then y<="000";
else
y<="111";
end if;
end process;
end Behavioral;
 

7. 3:8 DECODER:               

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HDL Lab Manual
                                                  
TRUTH TABLE:

INPUT
OUTPUT

s s(1) s(0) y(7)     y(6) y(5) y(4) y(3) y(2) y(1) y(0)
(2)

0 0 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 1 0 0

0 1 1 0 0 0 0 1 0 0 0

1 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 1 0 0 0 0 0

1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0

VHDL VERILOG
library IEEE;  module decod(s, y);
use IEEE.STD_LOGIC_1164.ALL; input [2:0] s;
use IEEE.STD_LOGIC_ARITH.ALL; output [7:0] y;
use IEEE.STD_LOGIC_UNSIGNED.ALL; reg [7:0]y;
entity dec1 is always @(s)
    Port ( s : in  std_logic_vector (2 downto 0); begin
           y : out  std_logic_vector (7 downto 0)); case (s)
end dec1; 3'd0:y=8'd1;
architecture Behavioral of dec1 is 3'd1:y=8'd2;
begin 3'd2:y=8'd4;
process(s) 3'd3:y=8'd8;
begin 3'd4:y=8'd16;
case(s) is 3'd5:y=8'd32;
when "000" =>y<="00000001" ; 3'd6:y=8'd64;
when "001" =>y<="00000010"; 3’d7: y=8'd128;
when "010" =>y<="00000100"; endcase
when "011" =>y<="00001000"; end
when "100" =>y<="00010000"; endmodule
when "101" =>y<="00100000";
when "110" =>y<="01000000";
when "111" =>y<="10000000";
when others=>null;
end case;
end process;
end Behavioral;
 
 

Dept. of E&C, Ekalavya Institute of Tech. 17

HDL Lab Manual

8. TWO-BIT COMPARATOR:      
             
TRUTH TABLE:

A1 A0 B1 B0 Y1 (A > B) Y2 (A = B) Y3 (A < B)
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

VHDL VERILOG
library IEEE; module comparator (a,b,y);
use IEEE.STD_LOGIC_1164.ALL; input [1:0] a,b;
use IEEE.STD_LOGIC_ARITH.ALL; output [2:0] y;
use IEEE.STD_LOGIC_UNSIGNED.ALL; reg [2:0] y;
entity comp is always@(a,b)
    Port ( a,b : in  std_logic_vector (1 downto 0); begin
           y : out  std_logic_vector (2 downto 0)); if(a==b)
end comp; y=3’b010;
architecture Behavioral of comp is else if(a>b)
begin y=3’b100;
process(a,b) else
begin y=3’b001;
if (a>b) then end
y<=”100”; endmodule
elsif (a<b) then
y<= “001”;
else
y<= “010”;
end if;
end process;
end Behavioral;

Dept. of E&C, Ekalavya Institute of Tech. 18

HDL Lab Manual

9. Binary to gray (USING EXOR GATES):     

            
TRUTH TABLE:

Inputs Outputs

B (3) B (2) B (1) B (0) G (3) G (2) G (1) G (0)

0 0 0 0 0 0 0 0
EXPRESSIONS: G(0)=B(0)  B(1)
0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1 G(1)=B(1)  B(2)
G(2)=B(2)  B(3)
0 0 1 1 0 0 1 0
G(3)=B(3)
0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

VHDL VERILOG
library IEEE; module bgv(b, g);
use IEEE.STD_LOGIC_1164.ALL; input [3:0] b;
use IEEE.STD_LOGIC_ARITH.ALL; output [3:0] g;
use IEEE.STD_LOGIC_UNSIGNED.ALL; reg[3:0]g;
entity Binary_Gray is always@(b)
port(  b: in std_logic_vector(3 downto 0);           begin
        g: out std_logic_vector(3 downto 0));       g[0]=b[0]^b[1];
end  binary_gray; g[1]=b[1]^b[2];
architecture behavioral of  Binary_gray is g[2]=b[2]^b[3];
begin g[3]=b[3];
g(3)<= b(3); end
g(2)<= b(3) xor b(2); endmodule
g(1)<= b(2) xor b(1);  
g(0)<= b(1) xor b(0);
end behavioral; 
 
 

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HDL Lab Manual

10.a) SR FLIP-FLOP:

TRUTH TABLE:-

Reset S R Clock Qn+1 Qn+1 bar Status

1 X X X 0 1 Reset
No Change
0 0 0 Clk Qn Qn bar (Memory)
0 0 1 Clk 0 1 Reset
0 1 0 Clk 1 0 Set
0 1 1 clk Invalid

VHDL VERILOG
library IEEE; module srff(clk,rst, sr,q,qb);
use IEEE.STD_LOGIC_1164.ALL; input clk,rst;
use IEEE.STD_LOGIC_ARITH.ALL; input [1:0] sr;
use IEEE.STD_LOGIC_UNSIGNED.ALL; output q,qb;
entity srff is reg q,qb;
    Port ( s,r,clk,rst : in  STD_LOGIC; always@(posedge clk)
           q : out  STD_LOGIC; begin
qb : out  STD_LOGIC); if(rst==1)
end srff; begin
architecture Behavioral of srff is q=1’b0;qb=1’b1;
begin end
process(clk,rst) else
begin begin
if(rst='1')then case(sr)
q<='0';qb<='1'; 2'b00:begin q=q;qb=qb; end
elsif rising_edge(clk)then 2'b01:begin q=1’b0;qb=1’b1;end
if(s='0' and r='0')then 2'b10:begin q=1’b1;qb=1’b0;end
q<=q;qb<=qb; 2'b11:begin q=1’bz;qb=1’bz;end
elsif(s='0' and r='1')then default:begin q=1’b0;qb=1’b1;end
q<='0';qb<='1'; endcase
elsif(s='1' and r='0')then end
q<='1';qb<='0'; end
elsif(s='1' and r='1')then endmodule
q<='X';qb<='X';
end if;
end if;
end process;
end Behavioral;

Dept. of E&C, Ekalavya Institute of Tech. 20

HDL Lab Manual

10. b) D FLIP FLOP:

TRUTH TABLE:

Qn+1
Reset D Clock Qn+1 bar

1 0 X 0 1

0 0 Clk 0 1
0 1 clk 1 0

VHDL VERILOG
library IEEE; module dff(clk,rst,d,q,qb);
use IEEE.STD_LOGIC_1164.ALL; input clk;
use IEEE.STD_LOGIC_ARITH.ALL; input rst,d;
use IEEE.STD_LOGIC_UNSIGNED.ALL; output q,qb;
entity dff is reg q, qb;
    Port ( d,res,clk : in  STD_LOGIC; always@(posedge clk)
          q: inout  STD_LOGIC; begin
qb : out  STD_LOGIC); if(rst==1)
end dff; begin
architecture Behavioral of dff is q=1’b0;
begin end
process(clk) else
begin begin
if (res ='1') then q=d;
q<='0'; end
elsif rising_edge(clk) then qb=~q;
q<=d; end
end if; endmodule
qb<= not q;
end process;
end Behavioral;

Dept. of E&C, Ekalavya Institute of Tech. 21

HDL Lab Manual

10. c) JK FLIP FLOP WITH ASYNCHRONOUS RESET:           

TRUTH TABLE:

Reset J K Clock Qn+1 Qn+1 bar Status

1 X X X 0 1 Reset
0 0 0 Clk Qn Qn bar No Change
0 0 1 Clk 0 1 Reset

0 1 0 Clk 1 0 Set
0 1 1 clk Qn bar Qn Toggle

VHDL VERILOG
library IEEE; module jkff(jk, clk,rst, q,qb);
use IEEE.STD_LOGIC_1164.ALL; input [1:0]jk;
use IEEE.STD_LOGIC_ARITH.ALL; input clk,rst;
use IEEE.STD_LOGIC_UNSIGNED.ALL; output q,qb;
entity jk is reg q,qb;
        Port ( j,k,clk,reset : in  STD_LOGIC; wire  clkd;
          q : inout STD_LOGIC; reg [20:0] COUNT;
qb : out  STD_LOGIC); initial COUNT=0;
end jk; assign clkd=COUNT[20];
  always @(posedge clk)
architecture Behavioral of jk is begin
signal div:std_logic_vector(22 downto 0); COUNT = COUNT + 1;
signal clkd:std_logic; end
begin always@(posedge clkd)
---------------------------------------- begin
process(clk) if(rst==1)
begin begin
if rising_edge(clk) then            ----CLOCK DIVIDER q=1’b0;
div<= div+1; end
end if; else
end process; begin
clkd<=div(22); case(jk)
---------------------------------------- 2'b00:q=q;
-----for simulation clkd is replaced by clk 2'b01:q=1’b0;
process(clkd,reset)   2'b10:q=1’b1;
begin default:q=~(q);
if(reset='1')then endcase
q<= '0'; end
elsif rising_edge(clkd)then qb=~q;
if(j='0' and k='0')then end
q<= q; endmodule
elsif(j='0' and k='1')then
q<= '0';
elsif(j='1' and k='0')then
q<= '1';
elsif(j='1' and k='1')then
q<= not q;
end if;
end if;

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qb<=not q;
end process;
end Behavioral;

10 d) T FLIP-FLOP:   
                                                                                               
TRUTHTABLE:
 
Reset T Clock Qn+1 Qn+1 bar
1 X X 0 1
0 0 Clk Qn Qn bar
0 1 Clk Qn bar Qn

VHDL VERILOG
library IEEE; module tff(clk,rst,t, q,qb);
use IEEE.STD_LOGIC_1164.ALL; input clk,rst,t;
use IEEE.STD_LOGIC_ARITH.ALL; output q,qb;
use IEEE.STD_LOGIC_UNSIGNED.ALL; reg q,qb;
entity tf is reg [19:0] COUNT;
       Port ( t,clk,rst : in  STD_LOGIC; wire clkd;
           q : inout  STD_LOGIC; initial COUNT=0;
qb : out  STD_LOGIC); assign clkd=COUNT[19];
always @(posedge clk)
end tf; begin
  COUNT = COUNT + 1;
architecture Behavioral of tf is end
signal div:std_logic_vector(22 downto 0); always@(posedge clkd)
signal clkd:std_logic; begin
begin if(rst==1)
---------------------------------------------- begin
process(clk) q=0;
begin end
if rising_edge(clk)then     ----CLOCK DIVIDER else
div<= div+1; begin
end if; case(t)
end process; 1'b0: q=q;
clkd<=div(20); 1'b1: q=~(q);
---------------------------------------------- endcase
-----for simulation clkd is replaced by clk end
process(clkd,rst)           qb=~q;
begin end
if(rst='1')then endmodule
q<='0';
elsif rising_edge(clkd) then
if( t ='1') then
q<= not q;
else
q<=q;
end if;
end if;
qb<=not q;
end process;
end Behavioral;

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11. ASYNCHRONOUS BINARY UP COUNTER:        

 
TRUTHTABLE :

RST CLOCK QD QC QB QA
1 ↑ 0 0 0 0
0 ↑ 0 0 0 0
0 ↑ 0 0 0 1
0 ↑ 0 0 1 0
0 ↑ 0 1 0 0
0 ↑ 0 1 0 1
0 ↑ 0 1 1 0
0 ↑ 0 1 1 1
0 ↑ 1 0 0 0
0 ↑ 1 0 0 1
0 ↑ 1 0 1 0
0 ↑ 1 0 1 1
0 ↑ 1 1 0 0
0 ↑ 1 1 0 1
0 ↑ 1 1 1 0
0 ↑ 1 1 1 1

VHDL VERILOG
library IEEE; module asynup(clk,rst,q);
use IEEE.STD_LOGIC_1164.ALL; input clk,rst;
use IEEE.STD_LOGIC_ARITH.ALL; output [3:0] q;
use IEEE.STD_LOGIC_UNSIGNED.ALL; reg [3:0] q;
 entity up is reg [22:0] COUNT;
       Port ( rs,clk : in  STD_LOGIC;  wire clkd;
         q : inout  std_logic_vector (3 downto 0)); initial COUNT=0;
 end up; assign clkd=COUNT[22];
 architecture Behavioral of up is always @(posedge clk)
signal div:std_logic_vector(22 downto 0); begin
signal temp:std_logic_vector (3 downto 0); COUNT = COUNT + 1;
signal clkd:std_logic; end
begin always@(posedge clkd)
------------------------------- begin
process(clk) if(rst==1)
begin begin
if rising_edge(clk)then       ----CLOCK DIVIDER q=4'b0000;      /*FOR ASYNCRONOUS
div<= div+1; DOWN COUNTER CHANGE q=4'b1111*/
end if; end
end process; else
clkd<=div(22); begin
-----for simulation clkd is replaced by clk q=q+1;           /*FOR ASYNCRONOUS DOWN
process(clkd,rs)                                                 COUNTER CHANGE Q=Q-1*/
begin end
if(rs='1')then temp<=(others=>'0');                end
-----for down counter temp<="1111"; endmodule
elsif rising_edge(clkd ) then
temp<=temp+1;                                                
------for down counter temp<= temp-1;
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q<= temp;
end if;
end process;
end Behavioral;

12.ASYNCHRONOUS BCD UP COUNTER:        

 TRUTHTABLE :
RST CLOCK QD QC QB QA
1 ↑ 0 0 0 0
0 ↑ 0 0 0 0
0 ↑ 0 0 0 1
0 ↑ 0 0 1 0
0 ↑ 0 1 0 0
0 ↑ 0 1 0 1
0 ↑ 0 1 1 0
0 ↑ 0 1 1 1
0 ↑ 1 0 0 0
0 ↑ 1 0 0 1

VHDL VERILOG

library IEEE; module asynup(clk,rst,p,q);

use IEEE.STD_LOGIC_1164.ALL; input clk,rst;
use IEEE.STD_LOGIC_ARITH.ALL; output [3:0] q;
use IEEE.STD_LOGIC_UNSIGNED.ALL; reg [3:0] q;
entity manin3 is reg [22:0] COUNT;
Port ( clk,rst : in std_logic; wire clkd;
q : inout std_logic_vector (3 downto 0)); initial COUNT=0;
end ; assign clkd=COUNT[22];
architecture Behavioral of manin3 is always @(posedge clk)
signal div:std_logic_vector(22 downto 0); begin
signal clkd:std_logic; COUNT = COUNT + 1;
signal temp:std_logic_vector(3 downto 0); end
begin always@(posedge clkd)
-------------------------------------- begin
process(clk) if(rst==0 | q==4'b1001)     /*FOR BCD
begin DOWN change q==4'b0000*/
if rising_edge(clk) then ----CLOCK DIVIDER begin
div<= div+1; q=4'b0000;                  /*FOR BCD DOWN
end if; change q=4'b1001*/
end process; end
clkd<=div(22); else
-------------------------------------- begin
---for simulation clkd is replaced by clk q=q+1;                     /*FOR BCD DOWN
process(clkd,rst) change q= q-1*/
begin end
if rising_edge(clkd) then end
if rst='0' or q="1001" then endmodule
temp<="0000";  
else
temp<=temp+1;
end if;
end if;
end process;
q<=temp;

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end Behavioral;

13. SEQUENCE COUNTER:

VHDL VERILOG

library IEEE; module any(clk,rst, q);

use IEEE.STD_LOGIC_1164.ALL; input clk,rst;
use IEEE.STD_LOGIC_ARITH.ALL; output [3:0] q;
use IEEE.STD_LOGIC_UNSIGNED.ALL; reg[3:0]q;
  reg[22:0]count;
entity SEQ is wire clkd;
    Port ( clk : in  std_logic; initial count=0;
       z : out  std_logic_vector (3 downto 0)); initial q=4'b0001;
end SEQ; assign clkd=count[22];
  always@(posedge clk)
architecture Behavioral of SEQ is begin
signal ps,ns :integer:=0; count=count+1;
signal clkdd: std_logic_vector(22 downto 0); end
signal clkd: std_logic; always@(posedge clkd)
begin begin
-------------------------------------------------- if(rst==1)
process(clk) begin
begin q=4'b0000;
if rising_edge(clk) then end
clkdd<=clkdd+'1'; ----CLOCK DIVIDER else
end if; begin
end process; case(q)
clkd<=clkdd(22); 4'd1:q=4'd3;
--------------------------------------------------  4'd3:q=4'd5;
-----for simulation clkd is replaced by clk 4'd5:q=4'd7;
process(ps) 4'd7:q=4'd9;
begin 4'd9:q=4'd1;
  case ps is default:q=4'd0;
when 0=>z<="0000";ns<=1; endcase
when 1=>z<="0010";ns<=2; end
when 2=>z<="0011";ns<=3; end
when 3=>z<="0100";ns<=4; endmodule
when 4=>z<="0000";ns<=0;
when others=>null;
end case;
end process;
process(clkd)
begin
if rising_edge(clkd) then
ps<= ns;
end if;
end process;
end Behavioral;

14. 32 BIT ALU

    Write a model for 32 bit ALU using the Schematic diagram shown below A(31:0) B(31:0) out.
 
 ALU should use combinational logic to calculate an output based on the four bit op-code input.

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 ALU should pass the result to the out bus when enable line in high, and tri-state the out bus when
the enable line is low.
 ALU should decode the 4 bit op-code according to the given in example below.
 OPCODE                                      ALU OPERATION
1.                                                                                                      A+B
2.                                                                                                      A-B
3.                                                                                                       A Complement
4.                                                                                                      A*B
5.                                                                                                      A AND B
6.                                                                                                      A NAND B
7.                                                                                                      A XOR B
8.                                                                                                      A OR B

VHDL VERILOG
library IEEE; module aluver(a,b,en,op,c,d,cy);
use IEEE.STD_LOGIC_1164.ALL; input [31:0] a,b;
use IEEE.STD_LOGIC_ARITH.ALL; input en;
use IEEE.STD_LOGIC_UNSIGNED.ALL; input [3:0] op;
entity alu is output [31:0] c,d;
Port ( a,b : in  std_logic_vector(31 downto 0); output cy;
         c,d: out  std_logic_vector(31 downto 0); reg [31:0] c,d;
         op: in std_logic_vector(3 downto 0); reg [32:0]cl;
         en: in std_logic; reg [63:0]e;
         cy: out std_logic); always @(a,b,en,op,e,cl)
end alu; begin
architecture Behavioral of alu is if (en==1)
signal c1:std_logic_vector(32 downto 0); case (op)
signal e:std_logic_vector(63 downto 0); 4'b0001:cl=a+b;
begin 4'b0010:if (a<b)
process (a,b,en,op,e,c1) begin
begin c=b-a;
if en='1' then end
case op is else
when "0001"=>c1<=('0'& a)+('0'& b); begin
c<=c1(31 downto 0); c=a-b;
cy<=c1(32); end
when"0010"=>if(a<b)then c<=b-a; 4'b0011:c=~a;
else c<=a-b; 4'b0100:e=a*b;
end if; 4'b0101:c=a&b;
when"0011"=>c<=not a; 4'b0110:c=~(a&b);
when"0100"=>e<=a*b; 4'b0111:c=a^b;
d<=e(63 downto 32); endcase
c<=e(31 downto 0); else
when"0101"=>c<=a and b; begin
when"0110"=>c<=a nand b; c=32'bZ;
when"0111"=>c<=a xor b; end
when “1000”=>c<=a or b; end
when others=>null; endmodule
end case;
else
c<=(others=>'Z');
d<=(others=>'Z');
end if;
end process;
end behavioral;

INTERFACING PROGRAMS

1 a. Write a VHDL code to generate Ramp waveforms using DAC.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ramp_wave is
Port ( clk : in std_logic;
rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end ramp_wave;
architecture Behavioral of ramp_wave is
signal temp : std_logic_vector(3 downto 0);
signal counter : std_logic_vector(0 to 7);
signal en :std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp <= temp + '1' ;
end if;
end process;
process(temp(3))
begin
if rst='1' then
counter <= "00000000";
elsif rising_edge(temp(3)) then
counter <= counter + 1 ;
end if;
end process;
dac_out <=counter;
end Behavioral;

UCF file(User constraint File):

NET "clk" LOC = "p52" ;

NET "dac_out<0>" LOC = "p21" ;
NET "dac_out<1>" LOC = "p18" ;
NET "dac_out<2>" LOC = "p17" ;
NET "dac_out<3>" LOC = "p15" ;
NET "dac_out<4>" LOC = "p14" ;
NET "dac_out<5>" LOC = "p13" ;
NET "dac_out<6>" LOC = "p12" ;
NET "dac_out<7>" LOC = "p1" ;
NET "rst" LOC = "p74" ;

NOTE: The following procedure is common for Saw tooth, Ramp, Triangular and Square wave  programs.
 Procedure:

1. Make the connection between FRC5 of the FPGA board to the DAC connector of the VTU
card2.
2. Make the connection between FRC1 of the FPGA board to the Dip switch connector of the VTU
card2.
3. Connect the downloading cable and power supply to the FPGA board.
4. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode and select
the respective BIT file and click program.
5. Make the reset switch on (active low) and analyze the data.
 
b. Write a VHDL code to generate Stair case waveforms using DAC.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Stair case_wave is
Port ( clk : in std_logic;
rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end Stair case_wave;
architecture Behavioral of Stair case _wave is
signal temp : std_logic_vector(3 downto 0);
signal counter : std_logic_vector(0 to 7);
signal en :std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp <= temp + '1' ;
end if;
end process;
process(temp(3))
begin
if rst='1' then
counter <= "00000000";
elsif rising_edge(temp(3)) then
counter <= counter + 15 ;
end if;
end process;
dac_out <=counter;
end Behavioral;

UCF file(User constraint File):

NET "clk" LOC = "p52" ;

NET "dac_out<0>" LOC = "p21" ;
NET "dac_out<1>" LOC = "p18" ;
NET "dac_out<2>" LOC = "p17" ;
NET "dac_out<3>" LOC = "p15" ;
NET "dac_out<4>" LOC = "p14" ;
NET "dac_out<5>" LOC = "p13" ;
NET "dac_out<6>" LOC = "p12" ;
NET "dac_out<7>" LOC = "p1" ;
NET "rst" LOC = "p74" ;

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c. Write a VHDL code to generate Triangular waveforms using DAC.                     

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity triangular_wave is
Port ( clk : in std_logic;
rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end triangular_wave ;
architecture Behavioral of triangular_wave is
signal counter : std_logic_vector(0 to 8);
signal temp : std_logic_vector(3 downto 0);
signal en :std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp <= temp + '1' ;
end if;
end process;
process(temp(3))
begin
if rst='1' then
counter <= "000000000";
elsif rising_edge(temp(3)) then
counter <= counter + 1 ;
if counter(0)='1' then
dac_out <=counter(1 to 8);
else
dac_out <=not(counter(1 to 8));
end if;
end if;
end process;
end Behavioral;

UCF file(User constraint File):

NET "clk" LOC = "p52" ;
NET "dac_out<0>" LOC = "p21" ;
NET "dac_out<1>" LOC = "p18" ;
NET "dac_out<2>" LOC = "p17" ;
NET "dac_out<3>" LOC = "p15" ;
NET "dac_out<4>" LOC = "p14" ;
NET "dac_out<5>" LOC = "p13" ;
NET "dac_out<6>" LOC = "p12" ;
NET "dac_out<7>" LOC = "p1" ;
NET "rst" LOC = "p74" ;
                                                                                                                                   

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d. Write a VHDL code to generate Square waveforms using DAC.              

 
 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity square_wave is
Port ( clk : in std_logic;
rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end square_wave;
architecture Behavioral of square_wave is
signal temp : std_logic_vector(3 downto 0);
signal counter : std_logic_vector(0 to 7);
signal en :std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp <= temp + '1' ;
end if;
end process;
process(temp(3))
begin
if rst='1' then
counter <= "00000000";
elsif rising_edge(temp(3)) then
if counter<255 and en='0' then
counter <= counter + 1 ;
en<='0';
dac_out <="00000000";
elsif counter=0 then
en<='0';
else
en<='1';
counter <= counter-1;
dac_out <="11111111";
end if;
end if;
end process;
end Behavioral;
UCF file(User constraint File):
NET "clk" LOC = "p52" ;
NET "dac_out<0>" LOC = "p21" ;
NET "dac_out<1>" LOC = "p18" ;
NET "dac_out<2>" LOC = "p17" ;
NET "dac_out<3>" LOC = "p15" ;
NET "dac_out<4>" LOC = "p14" ;
NET "dac_out<5>" LOC = "p13" ;
NET "dac_out<6>" LOC = "p12" ;
NET "dac_out<7>" LOC = "p1" ;
NET "rst" LOC = "p74" ;
 
 

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2. Write a VHDL code to control speed, direction of DC motor.

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

Library UNISIM;
use UNISIM.vcomponents.all;
entity dcmotor is
generic(bits : integer := 8 ); -- number of bits used for duty cycle.

-- Also determines pwm period.

port ( CLK: in STD_LOGIC; -- 4 MHz clock
RESET,DIR: in STD_LOGIC; -- dircntr
pwm : out std_logic_VECTOR(1 DOWNTO 0);
rly: out std_logic;
ROW: in STD_LOGIC_VECTOR(0 to 3) ); -- this are the row lines
end dcmotor;

architecture dcmotor1 of dcmotor is

signal counter : std_logic_vector(bits - 1 downto 0):="11111110";

signal DIV_REG: STD_LOGIC_VECTOR (16 downto 0); -- clock divide register
signal DCLK,DDCLK,datain,tick: STD_LOGIC; -- this has the divided clock.
signal duty_cycle: integer range 0 to 255;
signal ROW1 : STD_LOGIC_VECTOR(0 to 3); -- this are the row lines

begin
-- select the appropriate lines for setting frequency
CLK_DIV: process (CLK, DIV_REG) -- clock divider
begin
if (CLK'event and CLK='1') then
DIV_REG <= DIV_REG + 1;
end if;
end process;
DDCLK<=DIV_REG(12);
---------------------------- END OF CLOCK DIVIDER -------------------------------------------------
tick <= row(0) and row(1) and row(2) and row(3);
process(tick)
begin
if falling_edge(tick) then
case row is
when "1110" => duty_cycle <= 255 ; --motor speed 1
when "1101" => duty_cycle <= 200 ; --motor speed 2
when "1011" => duty_cycle <= 150 ; --motor speed 3
when "0111" => duty_cycle <= 100 ; --motor speed 4
when others => duty_cycle <= 100;
end case;
end if;
end process;

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process(DDCLK, reset)
begin
if reset = '0' then
counter <= (others => '0');
PWM<="01";
elsif (DDCLK'event and DDCLK = '1') then
counter <= counter + 1;
if counter >= duty_cycle then
pwm(1) <= '0';
else
pwm(1) <= '1';
end if; end if;
end process;
rly<=DIR --motor direction control
end dcmotor1;

UCF file (User constraint File):

NET "CLK" LOC = "p52" ;

NET “DIR” LOC = “p76”;
NET "pwm<0>" LOC = "p4" ;
NET "pwm<1>" LOC = "p141" ;
NET "RESET" LOC = "p74" ;
NET "rly" LOC = "p2" ;
NET "ROW<0>" LOC = "p69" ;
NET "ROW<1>" LOC = "p63" ;
NET "ROW<2>" LOC = "p59" ;
NET "ROW<3>" LOC = "p57" ;

Procedure:

1. Make the connection between FRC9 of the FPGA board to the DC motor connector of
the VTU card2.
2. Make the connection between FRC7 of the FPGA board to the Keyboard connector of
the VTU card2.
3. Make the connection between FRC1 of the FPGA board to the Dip switch connector of
the VTU card2.
4. Connect the downloading cable and power supply to the FPGA board.
5. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode
and select the respective BIT file and click program.
6. Make the reset switch on (active low).
7. Press the HEX keys and analyze the speed changes.

 
 
 
 
 
                                           
             

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3. Write a VHDL code to control speed, direction of Stepper motor.

 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity STEPPER is
Port ( dout : out std_logic_vector(3 downto 0);
clk,reset: in std_logic;
row:in std_logic_vector(1 downto 0);
dir:in std_logic);
end STEPPER;

architecture Behavioral of STEPPER is

signal clk_div : std_logic_vector(25 downto 0);

signal clk_int: std_logic;
signal shift_reg : std_logic_vector(3 downto 0);

begin
process(clk)
begin
if rising_edge (clk) then
clk_div <= clk_div + '1';
end if;
end process;

clk_int<=clk_div(21) when row="00"else

clk_div(19) when row="01"else
clk_div(17) when row="10"else
clk_div(15) ;
process(reset,clk_int,dir)

begin
if reset='0' then
shift_reg <= "1001";
elsif rising_edge(clk_int) then
if dir='0' then
shift_reg <= shift_reg(0) & shift_reg(3 downto 1);
else
shift_reg<=shift_reg(2 downto 0) & shift_reg(3);
end if;
end if;
end process;
dout <= shift_reg;
end Behavioral;
 

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UCF file(User constraint File):

 
NET "clk" LOC = "p52" ;
NET "dir" LOC = "p76" ;
NET "dout<0>" LOC = "p141" ;
NET "dout<1>" LOC = "p2" ;
NET "dout<2>" LOC = "p4" ;
NET "dout<3>" LOC = "p5" ;
NET "reset" LOC = "p74" ;
NET "row<0>" LOC = "p77" ;
NET "row<1>" LOC = "p79" ;

 
 
Procedure:

1. Make the connection between FRC9 of the FPGA board to the Stepper motor
connector of
the VTU card2.
2. Make the connection between FRC7 of the FPGA board to the Keyboard connector of
the
VTU card2.
3. Make the connection between FRC1 of the FPGA board to the Dip switch connector of
the
VTU card2.
4. Connect the downloading cable and power supply to the FPGA board.
5. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode
and
select the respective BIT file and click program.
6. Make the reset switch on (active low).
7. Press the HEX keys and analyze the speed changes.

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
                                                                                                                                   

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4. Write a VHDL code to control external lights using relays.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity extlight is
Port ( cntrl1,cntrl2 : in std_logic;
light : out std_logic);
end extlight;

architecture Behavioral of extlight is

begin
light<= cntrl1 XOR cntrl2 ;
end Behavioral;

UCF file(User constraint):

NET "cntrl1" LOC = "P74";

NET "cntrl2" LOC = "P76";
NET "light" LOC = "P5";

Procedure:

1. Make the connection between FRC9 of the FPGA board to the External light
connector of the VTU card2.
2. Make the connection between FRC1 of the FPGA board to the Dip switch connector of
the VTU card2.
3. Connect the downloading cable and power supply to the FPGA board.
4. Then open the Xilinx IMPACT software (refer ISE flow) select the slave serial mode
and select the respective BIT file and click program.
5. Make the reset switch on (active low) and analyze the data.

 
 
 
 
 

Dept. of E&C, Ekalavya Institute of Tech. 36