2010 IRPS Tutorial Program
Mark Porter, Medtronics
[111] BASIC CONCEPTS AND METHODS FOR
RELIABILITY DATA ANALYSIS ― W. Meeker ―
Iowa State University―Reliability assurance processes in
manufacturing industries require data-driven information
for making product-design decisions. Life tests,
accelerated life tests, and accelerated degradation tests are
commonly used to collect reliability data. Data from
products in the field provide another important source of
useful reliability information. These reliability studies
typically yield data that are censored and/or truncated,
require the use of less familiar distributions like the
Weibull, the lognormal, and the gamma, and call for
inferences that involve extrapolation.
This tutorial will present and discuss the analyses of
several different life data analysis applications in the area
of product reliability and materials evaluation. The
analyses illustrate the use of a mix of proven traditional
techniques, enhanced and brought up to date with modern
computer-based methodology. Methods used in the
analyses include probability plotting, maximum likelihood
estimation, analysis of data with multiple failure modes,
acceleration models, accelerated life testing, accelerated
degradation testing, and the analysis of recurrence data
from repairable systems.
This tutorial will focus primarily on graphical presentation
of the results of the analyses and will describe the
applications, data, concepts, statistical methods, and
interpretation of the results.
[112] EMERGING TRENDS IN FA FOR 32NM AND
BELOW ― M. Bruce – Independent Consultant ―This
tutorial describes emerging trends in FA for 32nm
technology nodes and below. The state of tools and
techniques will be described for design debug and
identifying defects at a level required to keep pace with
scaling. The semiconductor industry faces enormous
challenges as defects move from being physically viewable
to atomic level perturbations that cause circuits to
malfunction. A holistic approach will be presented from
design debug to manufacturing defect analysis.
[113] PARASITIC AND RELIABILITY ISSUES OF
GAN-BASED HIGH ELECTRON MOBILITY
TRANSISTORS ― M. Damman and G. Meneghesso ―
Fraunhofer - Institut für Angewandte Festkörperphysik and
University of Padova ― Gallium Nitride represents an
almost ideal material for the fabrication of high power
microwave devices and circuits: its high energy gap (3.4
eV vs. 1.4 eV for GaAs) is reflected into a very high
breakdown field (3500 kV/cm); piezoelectric and
spontaneous polarization effects within AlGaN/GaN result
in 2D gas densities above 1013 cm-2, 5 times higher than for
GaAs-based HEMTs, without requiring doping of the
barrier layer. Saturation and overshoot velocity are around
3 x 107 cm/s, with relatively good electron mobility values
(1200 cm2/V.s). Epitaxial structures can be grown on
silicon carbide with limited lattice mismatch, thus
exploiting the excellent thermal conductivity and semi-
insulating properties of this material, suitable for RF and
microwave device operation. GaN HEMTs are therefore
extremely promising for power electronics applications
from power conditioning to microwave amplifiers and
transmitters. Front-end applications are also interesting,
due to the intrinsic robustness and survivability of high
breakdown voltage GaN HEMTs, coupled with reasonable
noise figures. Satellite communications, high performance
radars and commercial ground base stations currently
represent target system applications. Within these
applications, it is expected that GaN-based transistors will
replace the so far used Si-transistors in the near future
mainly due to their larger bandwidth capabilities, their
higher operating voltages as well as their higher linear
efficiencies.
In the last years, GaN HEMTs have been subject to various
optimization processes, starting from the material
properties, to the control of surface and buffer properties
aimed at reducing transient phenomena, gate-lag effects
and the "current collapse" problems. A better control of
short-channel effects, gate current, and degradation
phenomena at high electric fields, together with the
development of suitable structures for the management of
the electric field (using T-shaped and Γ-shaped gates and
field-plates) have lead to the progressive increase of the
operating drain voltage from 12 V to 24 V and 48 V.
In this tutorial recent reliability data under DC and RF
operation and the current understanding of the major
degradation mechanisms will be presented. In particular,
failure modes and mechanisms of GaN HEMTs, identified
within the framework of various accelerated tests,
including step-stress short tests (<150 hours) and life tests
with a duration exceeding 3000 hours, will be presented.
The proposed methodology includes a detailed
characterization of the main parasitic effects in GaN
HEMT devices (gate leakage current, current collapse,
kink effect, etc.) by means of DC and pulsed electrical
measurements. The observed failure modes are
subsequently analyzed by two-dimensional device
simulations in order to validate hypotheses on physical
failure mechanisms. Electroluminescence microscopy and
spectroscopy is adopted to evaluate hot carrier effects in
GaN HEMTs, and as a powerful failure analysis tool.
[121] ADVANCED GATE STACK RELIABILITY:
CORRELATING STRUCTURAL AND ELECTRICAL
CHARACTERISTICS ― G. Bersuker – SEMATECH ―
Relentless device scaling challenges the traditional
“empirical” approach to device characterization, which
becomes too costly and time consuming. Introduction of
new materials and complex multi-component gate stack
structures shift emphasis to instabilities caused by process-
related defects rather than stress-generated ones, which are
usually associated with the time dependency of device
characteristics. This points to a growing need to identify
the nature of defects affecting electrical characteristics of
devices, specifically their reliability, that would allow
developing physics-based predictive degradation models,
as well as provide helpful feedback to the fabrication
process optimization efforts. The process development can
be greatly accelerated when reliability characteristics can
be correlated to the electrically-active atomic structural
features of the dielectric stacks. In this tutorial, we focus
on analysis and interpretation of electrical data provided
by a variety of measurement techniques in an effort to
understand the gate stack material characteristics
contributing to instability of electrical parameters.
[122] NBTI: CONFUSION, FRUSTRATION,
AND…PROMISE? ― J. Campbell ― NIST ―The
negative-bias temperature instability (NBTI) is a reliability
problem that, in the last ten years, has risen from relative
obscurity to become the most important reliability problem
in advanced pMOSFET devices. Even though a significant
effort has been spent trying to eliminate NBTI signatures
(negative threshold voltage shift and transconductance
degradation after inversion gate stress at elevated
temperatures), the issue still persists. NBTI’s elusiveness is
due to the fact that NBTI-induced degradation relaxes very
quickly after the conclusion of stress. This makes NBTI
characterizations quite tedious and clouds the fundamental
understanding of the degradation/relaxation mechanism. In
high- gate stacks, the situation is complicated further by
inherent fast charge trapping issues and the emergence of
an additional positive bias temperature instability (PBTI)
component. While this depiction of NBTI may seem
hopeless, there have been renewed efforts to uncover the
fundamental physical mechanisms that govern the process.
This tutorial summarizes noteworthy NBTI experimental
observations/techniques and discusses how these
observations might be leading towards a fundamental
understanding of NBTI. A general aim is to examine how
these observations validate/invalidate the current
understanding of NBTI.
[123] NBTI MEASUREMENT: HOW TRICKY COULD
IT GET? ― D.S. Ang ― Nanyang Technological
University ― Just when we thought we had completely
understood the long-standing negative bias-temperature
instability (NBTI) phenomenon, observation of non-
negligible recovery effect has forced us to rethink the
manner by which measurement of transistor degradation
should be carried out. This tutorial will provide an
overview of the numerous measurement methodologies
proposed in recent years to address the challenge posed by
NBTI recovery and discuss their relative merits and
demerits. It will also introduce the ultrafast switching
(UFS) method and show how this method could provide
more comprehensive information regarding transistor
degradation − threshold voltage shift, mobility degradation
and charge pumping current − using a single experimental
set-up. During the development of this technique, an
important insight into the behavior of the drain current
versus gate voltage curve in the high gate voltage regime
was derived and will also be discussed. In short, we will
show that the severe “bending” of the Id-Vg curve in the
high gate voltage regime, previously thought to be a
consequence of mobility attenuation by surface roughness
scattering, is actually the result of interface degradation
due to rapid charge trapping. This finding raises an
important concern over NBTI characterization in the high
gate voltage regime (e.g. the “on-the-fly” technique) using
simplified Id-Vg models. We will wrap up the talk with a
discussion on some of the results obtained using the UFS
method that may potentially offer a better understanding of
the elusive NBTI phenomenon.
[124] CMOS CHANNEL HOT CARRIER
QUALIFICATION FROM PHYSICS TO END OF LIFE
PROJECTIONS ― G. LaRosa and S. Rauch – IBM
―This tutorial covers the state of the art understanding on
the physics of channel hot carrier and currently
experienced challenges with CMOS scaling. Its
implications to a rigorous technology qualification
methodology more closely related to circuit/product
operations are also provided. It is shown how to apply DC
CHC models, developed from accelerated stress
conditions, to actual circuit waveforms. The use of
idealized waveforms to produce simplified AC projection
equations to be used in design manuals is explained. We
cover recent proposals for the correct treatment of
PMOSFET AC hot carrier, and the distinction between hot
carrier and NBTI in PMOSFETs. These ideas apply to
high- technologies which exhibit NMOSFET PBTI as
well. Finally, an overview of the industry adopted
qualification targets to be used for CHC End of Life
projections is given. As an example, the commonly used
“T0.1” or similar lifetime adopted as a Foundry target is
described and proven not to be indicative of actual product
lifetime or failure rate and not providing guidance to
ensure reliable system design and product test strategy.
[131] MECHANISMS, MODELING, MEASUREMENT
AND MITIGATION OF SOFT ERRORS ― C. Slayman,
K. Warren, and J. Wilkinson – Independent Consultant,
ISDE, Medtronic ― Soft errors continue to be a key
reliability concern for electronics. Unlike hard failures, a
soft error's transient nature and varying manifestations
makes it difficult to develop appropriate strategies for test
and characterization. Without reliable data on the rate and
modes of occurrence it is not possible to know if a system
can meet its reliability objectives or to design appropriate
mitigations. The tutorial addresses these questions for
engineers working on systems for terrestrial applications.
The tutorial is divided into 3 sessions of 1.5 hours each.
Physics of Soft Errors: The first session solidifies the
participant's background in soft errors by describing the
nuclear reactions, charge deposition and circuit responses
that create soft errors. The session will cover the history of
soft errors, their manifestations, and relevant test
standards. Results from nuclear modeling will be
introduced to illustrate key concepts.
Testing and Simulation: Session 2 takes the participants
through the details of the JESD89A soft error testing
standard including real-time testing and accelerated test
methods for terrestrial cosmic rays, alpha particles and
thermal neutrons. Descriptions of modeling to supplement
test methods are presented. Specialty test methods such as
ion microbeam and heavy ion testing will also be briefly
described.
Mitigation and Case Studies: In the last session a variety
of techniques are discussed for mitigating the effect of soft
errors. The subjects will range from IC process
adjustments, through circuits, and up to system level
recovery. Case studies will also be reported from the
literature and the authors' experiences.
[141] PHYSICS-BASED MATHEMATICAL
MODELING OF BATTERIES ― P. Gomadam ―
Medtronic Energy and Component Center ―Batteries have
current and potential applications as power sources to a
very wide variety of electrical and electronic devices –
from small handheld devices (e.g. watches and cell-
phones) to those demanding very high energy and power
(e.g. electric vehicles and grid storage systems). It is,
therefore, critical to understand the working of batteries so
as to be able to optimally design and reliably manufacture
them for a given application. Building batteries and testing
them in the lab is the most common approach to
understanding performance, but it is highly resource-
consuming and has limited applicability. Another approach
is to understand the battery from the fundamental physical
and chemical processes occurring during operation, and to
use them in combination with mathematics, to develop a
theoretical, predictive model of the battery. In addition to
offering great insight, this approach drastically minimizes
the expensive building-and-testing required, as well as
significantly widens applicability. Further, for applications
with very high reliability requirements, it is critical to have
performance accurately characterized ahead of time and,
thus, predictive mathematical models form necessary and
valuable tools. Furthermore, many applications involve
batteries operating together with mechanical components
or as part of sophisticated electronic circuitry, where
understanding the interaction between the battery and the
other components of the system are important. Using the
mathematical model of the battery, with the models of the
other components, offers a most efficient and reliable
approach to understanding the system.
In this tutorial, we present the development of a physics-
based mathematical model that predicts the performance of
a lithium-based non-rechargeable battery, relevant for a
class of implantable medical devices. The mathematical
model is a set of coupled ordinary differential and
algebraic equations governing the electrochemical reaction
kinetics of the battery, and requiring a numerical solution
to predict battery performance. We present data obtained
from individual testing of the main components of the
battery electrodes, and show how they were compared with
the model to obtain important thermodynamic and kinetic
parameters. The model predictions, made using these
parameters, are compared to the performance of
manufactured batteries over a wide range of design and
operating conditions. We present the comparisons and
show that the model accurately predicts battery
performance. Finally, we provide an overview of how
battery models are typically used as part of implantable
medical electronics product development.
[132] PROCESS INTEGRATION FOR COPPER
INTERCONNECTS IN LOW-K DIELECTRICS ― J.
Gambino ― IBM ― Interconnect processes using copper
wiring and low- dielectrics are reviewed for advanced
technology nodes. First, the structure and properties of
low- materials and barrier layers are described. Porous
dielectrics are generally required to achieve < 2.5, but
these materials are mechanically weak and chemically
reactive, making integration very challenging.
Next, integration issues are described including patterning,
cleans, metallization, chemical mechanical polishing
(CMP), and packaging. The patterning process is
becoming increasingly difficult because of the smaller
dimensions, the need for reduced line width variation, and
the use of dielectrics that contain carbon. Hardmasks are
increasingly being used to solve problems such as resist
erosion and resist strip damage of the low- material.
Metallization is more difficult because the liner and Cu
seed thicknesses must be drastically reduced, to avoid
increasing the line resistance and allow void-free Cu
plating to occur. The physical vapor deposition (PVD)
techniques that have been used in previous technology
generations are preferred for process simplicity. However,
other deposition methods, such as atomic layer deposition
(ALD) for the liner and direct plating to replace the seed
layer, may be required as interconnect dimensions are
reduced. CMP is increasingly challenging because of the
low mechanical strength of the low- dielectrics and the
need for reduced dishing and dielectric erosion. New
planarization methods are being used to address these
problems. Packaging is increasingly difficult because of
the low mechanical strength of the dielectrics. Dicing,
wirebonding, molding, and underfill processes must be
optimized when packaging chips that have low-
dielectrics in the stack. The effect of each of these
interconnect processes on reliability will be discussed.
[142] FLASH MEMORY RELIABILITY: A COMBINED
CHARACTERIZATION AND MODELING APPROACH
― L. Larcher and P. Pavan ― University of Modena ―
This course will present the basic concepts of the Flash
memory reliability, employing dedicated physical models
to understand mechanisms behind the observed reliability
phenomena. This perspective provides both a simple
explanation for experimental characterization results, as
well as extraction guidelines for device reliability
improvements.
The course will address the following points:
• Basic fundamentals of Flash memory reliability
• NOR and NAND Flash reliability requirements
• Key role of tunnel oxide: charge trapping and defect
generation effects on endurance, disturbs and retention
• Reliability issues in nano-Flash devices (RTN, etc.)
• Reliability issues related to high-k material
introduction (band-gap engineered tunneling barriers,
charge trapped memory devices MANOS)
[143] SILICON SYSTEM DESIGN FOR HIGH
AVAILABILITY APPLICATIONS ― A. Silburt ―
Cisco Systems ― This tutorial presents a methodology for
developing a specification for soft error performance of an
integrated hardware/software system that must achieve
highly reliable operation. The methodology enables
tradeoffs between reliability and cost to be made during
the early silicon design and SW architecture phase. An
accelerated measurement technique using neutron beam
irradiation is also described that ties the final system
performance to the reliability model and specification. The
methodology is illustrated for the design of a line card for
an internet core router.
[144] RELIABILITY CHANLLENGES IN THE
PHOTOVOLTAIC INDUSTRY ― A. Terao ―
SunPower― Photovoltaic (PV) modules are essentially
semiconductor devices, most of them made on slices of
silicon. However, some of their characteristics make then
very different than other electronic devices. They are
optoelectronic devices handling high currents,
encapsulated in large low-cost packages, stringed in series
to create high DC voltages.
When it comes to reliability, these differences have
important consequences in terms of failure analysis
techniques, physics of failure, accelerated life test,
statistical analysis, etc. The requirements are very high
too: more than twenty-five-year life expectancy in
uncontrolled outdoor stress conditions.
This tutorial will present the challenges faced by this
young PV industry growing at an exponential rate. It will
focus on the reliability of the main components of
photovoltaic systems, namely solar cells and PV modules
but will also briefly cover entire systems, from residential
rooftops to utility-scale power plants.
[211] THEORETICAL ASPECTS OF RELIABILITY
STATISTICS AND DATA ANALYSIS ― K. Croes, P.
Roussel, and G. Groeseneken – IMEC ― The statistical
aspects of different stages in reliability research will be
theoretically discussed. Four such stages are considered: a)
the design of the test structures, b) the choice of test
conditions, c) the actual performance of the test and d) the
final data analysis.
• The influence of test structure and choice of failure
criterion on the final result of a reliability study will
be discussed.
• The theory about planning reliability experiments will
be covered. The question of how to obtain more
reliable estimates with a given amount of test samples
and test time will be addressed.
• The specifications of a test system (resolution,
accuracy, gradients, etc.) will be linked to the final
interpretation of the data.
• The analysis of the final data will be the bigger part of
the tutorial. Here, we will introduce the different
failure types, failure time distributions, the least-
squares and maximum likelihood fitting method
together with their specific confidence interval
calculation techniques. Besides this, two more
advanced models will be discussed: bimodal
distributions and models for HBD distributions
including SBD.
[221] MEMS TEST, YIELD, AND RELIABILITY ― I.
De Wolf – IMEC ―This course will discuss MEMS
reliability from a very broad perspective, starting with
metrology tests addressing planarity and stress gradients;
yield testing; functional testing using electrical, optical or
mechanical actuation or detection schemes; and reliability
testing.
Possible ways to tackle reliability, through standard testing
or through a FMEA/physics-of-failure driven methodology
will be presented.
A short overview and discussion of the large number of
failure mechanisms that can occur in MEMS and MEMS
packages will be given.
The main focus of the course is on characterization and
test methods that can be used to study the reliability of
MEMS and of wafer-level MEMS packages. In many
cases existing techniques can be used or adapted for
MEMS testing and reliability assessment through simple
modifications. Several examples of this will be given. In
some cases dedicated instrumentation has to be used.
MEMS reliability is often linked to materials related
reliability issues. It requires information on material
properties. Techniques and test structures that can be used
to gather this information will be discussed.
It will be shown that several reliability issues in MEMS
can be solved by a proper material choice and design, by
packaging, or by applying alternative actuation schemes.
[222] RELIABILITY CHALLENGES OF 3D
INTEGRATION ― I. De Wolf – IMEC ―3D integration
is a technology that allows for the vertical stacking and
connecting of layers of basic electronic components, such
as integrated circuits (IC). This technology promises better
performance and smaller and cheaper systems, linking
various designs and applications (logic, memory, analog,
passives, sensors, etc) together in 3D.
However, as is the case for each new technology, this
might bring unknown reliability issues. 3D technology in
general goes together with several non-standard processing
steps such as the fabrication and filling of high aspect-ratio
through silicon vias (TSVs), the thinning of chips or
wafers, and the stacking and interconnection of these
chips. Not only each of these processing steps, but also the
total 3D stack brings new reliability issues.
In this course various yield and reliability related
challenges encountered in the 3D-SIC (stacked IC) process
which is under development in IMEC will be discussed.
This include problems related to
• TSV formation: stress and stability of the Cu in the
TSV, stress induced in the silicon and possible impact
on active devices, barrier issues, possible effects of
TSVs on the BEOL, effect of TSV on chip strength,
etc.
• Chip thinning: thinning-induced damage in the Si or
the devices, mechanical stress, potential thermo-
mechanical effects, wafer strength, etc.
• Bonding: SnCu micro-bump reliability, IMC growth,
Cu-Cu bonding issues, bonding-induced stresses and
damage, particles, co-planarity issues, etc.
• Thermal issues in stacked ICs.
In addition some failure analysis challenges will be
discussed.
[231] DESIGN IN RELIABILITY IN ADVANCED
CMOS ― V. Huard – STMicroelectronics ― The
continuous scaling of CMOS technologies down to sub-
micron range inevitably yields to reliability challenges
such as Negative Bias Temperature Instability (NBTI),
Time-Dependent Dielectric Breakdown (TDDB) and Hot
Carrier Injection (HCI). All these effects contribute to
degrading transistor temporal performance though
impacting overall product performance. Improvements in
reliability were made historically by the means of process
improvements which is proving to be more and more
difficult in advanced CMOS nodes. Supporting product
reliability in advanced nodes will require understanding,
simulating and mitigating reliability aspects during both
the process development stage as well as during the design
stage.
Design for Reliability in advanced CMOS requires a set of
predictive modeling and simulation tools called Design-In
Reliability. This set should integrate leading edge
reliability mechanisms, diagnose their impact on product
operations, and allow evaluating performance/reliability
trade-offs.
This tutorial will present both basic and advanced topics
on reliability modeling and simulation tools, including:
underlying reliability physics of leading reliability
mechanisms, transistor-level reliability modeling approach
within the framework of compact models, some ageing
effects in full-custom designs (SRAM, RFCMOS, Analog)
and simulation approach for hierarchical reliability
analysis.
[232] ADVANCED ESD DESIGN AND
QUALIFICATION ISSUES ― C. Duvvury – Texas
Instruments ― Component level IC ESD has been
constantly challenging for silicon technologies at every
turn of the technology node scaling and with the
development of higher speed circuits. These include the
effects from new transistor structures to the recent trend
for SoC. This tutorial will first review the most common
protection design techniques used by the industry today
and then describe the severe impact coming from
technology scaling on the design capability. Equally
important to the component ESD is the issue of system
level protection at the board level. The tutorial will also
address this important topic and give an insight into the
strategies for coupling both types of protection design.
Finally with the approach of 32nm and 22nm technologies
there is now a new paradigm shift in ESD target levels for
realistic and practical qualification. This roadmap for ESD
will be reviewed.
[241] FAILURE ANALYSIS OF PHOTOVOLTAIC
MODULES AND CELLS ― G. Alers – USCS ― The
efficiency of a photovoltaic module can degrade through
many mechanisms. Isolating these mechanisms and
making quantitative measurements of degradation rates is
the challenge of failure analysis. Failure mechanisms for
modules and cells will be quite different. The normal
procedure for understanding the failure of a module is (1)
measuring the electrical performance including light and
dark IV curves, (2) visual inspection, and (3) thermal
imaging. Based on the results of these initial screening
tests additional tests may be performed. This tutorial will
begin with an introduction to the basics of how to analyze
IV curves at the module and cell level. Thermal imaging
techniques will then be reviewed including far-infrared,
near infrared, lock-in thermography and thermal
reflectance imaging. Electroluminescence and
photoluminescence are additional evaluation tools that are
now commonly used for fully packaged modules. One of
the most versatile techniques is Laser Beam Induced
Current (LBIC) which has been used extensively at the cell
level to map out efficiency. At the cell level, most of the
failure analysis tools used for the microelectronics industry
are also applicable to photovoltaic materials. A list of
common failure modes for both modules and cells will be
presented with their characteristic signatures.
[242] BUILDING IN RELIABILITY AND
QUALIFICATIONS OF PV ELECTRONICS
PRODUCTS ― P. Chaparala – National Semiconductor
Corp. ― In recent years, there has been a significant
increase in deployment of distributed Balance of System
(BOS) products such as power optimizers and micro-
inverters in the photovoltaic industry. Market for smart
solar panels, where IC electronics are integrated into
panels for communication, security and power
optimization is expected to grow significantly in the near
future. Warranties of this new generation of power
electronics products are expected to match with solar panel
warranties of more than 20-years in outdoor environments.
Lack of industry-standard reliability qualification tests and
acceleration models makes it quite challenging to build
and validate long-term reliability into PV-electronics
products cost-effectively. In this tutorial, various PV-
industry qualification standards, models and test methods
to qualify PV-electronics will be reviewed. Also, building-
in reliability methods at various product development
phases, including concept, design, prototype and
manufacturing of power electronic system products will be
presented.
 2010 IRPS RELIABILITY YEAR IN REVIEW SEMINAR

James H. Stathis, IBM

GATE DIELECTRICS - Jason Campbell - The gate
dielectrics year-in-review includes a comprehensive
examination of the past year’s reports which detail
gate stack reliability issues and the corresponding
physical mechanisms which limit the performance
and lifetimes of advanced devices. The intent of this
presentation is to critically examine and publicize the
most important advancements in understanding and
mitigating various instabilities (BTI, TDDB, Noise,
etc…) in a variety of technologically relevant (oxide,
oxynitride, and high-k) gate stacks. In addition, this
review includes a short discussion regarding
reliability issues involved with the adoption of
alternative channel materials and the instabilities
associated with resistive/phase-change memories.
INTERCONNECT RELIABILITY - Fen Chen - This
review will provide an overview of 2009-2010
publications dealing with interconnect reliability
mechanisms including breakdown of BEOL
dielectrics, electromigartion, and stress migration for
an IRPS audience. The literatures of recent trends in
BEOL interconnect process development such as
doped Cu seeds, metal-cap, and airgap for 45nm and
beyond, and in reliability analysis methodologies for
addressing interconnect reliability challenges also
will be reviewed.
FAILURE ANALYSIS - Philippe Perdu - “More
Moore” and “More than Moore” trends have
triggered incredible challenges for microelectronic
failure analysis. It mostly concerns Fault Isolation,
Chip access, Defect Localization, Sample Preparation
and Physical analysis. In addition to a general
overview through key papers, a more specific focus
on defect localization will show the advanced
solutions developed to find the defect.
NANO-CMOS - Shinichi Takagi - The Nano-
electronics session in YIR will focus on the recent
progress of nano-scaled MOSFETs. After brief
summary of advanced CMOS platform and the
critical issues, three directions of future nano FETs,
ultrathin body/3D CMOS, new channel material
CMOS and emerging ultralow voltage FET concepts
will be reviewed.