CS141 Verilog Tutorial – Two Phase Clocking

Verilog Tutorial – Two Phase Clocking Guide

Lukasz Strozek

October 25, 2005

1 Introduction

Time has come to start thinking about designing and implementing actual sequential cir-
cuits. Fortunately, Verilog provides us with useful primitives and structures that support
sequential designs. In particular, the always keyword lets you define variables with state.
A variable inside of an always block is assigned a value conditional on an event, specified in
the argument to always. If the event has not happened, the value of the variable does not
change. You should see by now that this means that your design is not stateless anymore.

2 Latches versus Flip-flops

First, let’s quickly recall the difference between latches and flip-flops. For simplicity, we will
only talk about D latches and flip-flops. Both latches and flip-flops have one data input, a
clock input, and a data output.

A latch is a circuit which propagates data from its input to its output only if the clock
input is high. This means that when the clock input is low, the value of the output doesn’t
change.

A flip-flop is a circuit which propagates data from its input to its output only on clock
transition (either transition from low to high, or a transition from high to low – we’ll talk
about positive edge flip-flops, i.e. those that are sensitive to transitions from low to high).
The following diagram illustrates the function of a latch and a flip-flop:

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CS141 Verilog Tutorial – Two Phase Clocking

clock

input

output

latch flip-flop

3 Single phase (edge-based) clocking designs

Using only flip-flops, one can design very complicated sequential designs. All you need to
do is have a clock, to which you connect all your flip-flops, and emulate your FSM state
transitions by wiring up appropriate flip-flops. Refer to the lecture notes for more examples
of using D flip-flops.

The following example shows how one would use flip-flops in Verilog. The code below
implements a circuit which produces an oscillating signal if input is equal to 1. Convince
yourself that this is indeed the case.

always @(posedge clock or reset)

if(reset) begin
output = 1’b0;
end
else if(input) begin
output = ~output;
end

Unfortunately, there is a serious problem with using flip-flops in complicated designs which
include multi-level logic (i.e. designs where outputs from one flip-flop become inputs to
another flip-flop). This problem is called a race condition. Take the following circuit,
where the values of A, B and C are initially 0:

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CS141 Verilog Tutorial – Two Phase Clocking

B
A C

clock

When A is (asynchronously) set to 1, what happens to C after the first rising clock edge?
Well, on one hand, just before the first rising clock edge, the value of B is 0 (because it was
initially equal to 0), so after the first rising clock edge, the value of C should still be 0. But
on the other hand, just before the first rising clock edge, the value of A is 1, so on the first
rising clock edge this value is propagated to B. If the propagation is fast enough, this value
of 1 might also get propagated through the second flip-flop to C. This is not what we would
like, but depending on a number of external circumstances (such as the sizes of transistors
used to build each flip-flop or clock skew), we might end up seeing what we didn’t expect.

4 Two phase clocking designs

A two phase clocking design fixes this problem. It uses latches as opposed to flip-flops and
features two non-overlapping clocks (i.e. when one clock is high, the other clock is guaranteed
to be low even with pretty high clock skew). Essentially, we avoid race conditions by following
a few rules that state that only certain types of signals can go into certain types of latches.

Let’s explain this more carefully. Let φ1 and φ2 be the two clocks. The diagram below shows
the waveform of both clocks:

φ1

φ2

Call the latch that has φ1 as clock input the “φ1” latch, and the latch that has φ2 as clock
input the “φ2” latch. Moreover, call any signal that is guaranteed not to change while φ1 is
high the “s1” signal, and any signal that is guaranteed not to change while φ2 is high the

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CS141 Verilog Tutorial – Two Phase Clocking

“s2” signal. In other words, s1 signals are those suitable to be used in φ1 latches, and s2
signals are those suitable to be used in φ2 latches.

Also, define v1 as the signal that becomes stable (i.e. not changing) before φ1 falls and stays
stable for some time after, and similarly define v2. Of course, s1 signals are also v1 signals.
The diagram below shows the minimium requirements for each signal. The wide line shows
when the signal must remain stable:

φ1

φ2

s1

s2

v1

v2

The rules are as follows (symmetric rules for v2 inputs and φ2 latches apply):

• All inputs into the φ1 latch must be v1 inputs (remember, that includes s1 inputs)

• The outputs out of the φ1 latch are s2 inputs.

• Think of combinational logic as a block taking a bunch of v1 inputs and outputting

a bunch of v1 outputs. In a special case that all inputs to combinational logic are s1
inputs, the outputs are also s1

v1
|

.. ..
| {z }

{z

v1 s2 v1 or s1 . CL v1 s1 . CL s1
}

φ1

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CS141 Verilog Tutorial – Two Phase Clocking

It turns out that you can design any single phase project using two phase clocking with the
above rules in mind. Let’s give an example of the design above (oscillating signal if input is
equal to 1) using two phase clocking scheme.

// align inputs to phi2

always @(phi1 or input_v1)
if(phi1) input_s2 = input_v1;

// propagate registers
always @(phi1 or output_s1)
if(phi1) output_s2 = output_s1;

// handle reset and perform everything else

always @(phi2 or reset_async or input_s2)
if(reset_async) begin
output_s1 = 1’b0;
end
else if(phi2) begin
if(input_s2) begin
output_s1 = ~output_s2;
end
end

Let’s analyze this code. It really consists of three parts.1

• Taking stray inputs and aligning them to φ2, i.e. passing them through a φ1 latch
(recall that the output of such as latch is a s2 signal and so it’s suitable to be used as
an input to φ2). You may assume that all user inputs are v1 inputs

• Propagating registers. If you have a register that is type s2 and you want to reuse it,
you must propagate it through φ1 to create a s1 version of it. Otherwise, the value of
your register will be lost

• Performing actual FSM computation using φ2. Essentially, take all necessary s2 inputs
and compute s1 outputs while φ2 is high

1
Actually, the fourth part – an asynchronous reset – is part of the third part. Simply, if the asynchronous
reset is asserted, reset all your s1 signals regardless of the value of φ2)

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CS141 Verilog Tutorial – Two Phase Clocking

All three rules above can be summarized in the following Verilog rules (they are symmetric
if you’re using φ2 instead of φ1):

• Every always clause should contain exactly one clock and all the inputs that are
necessary to compute the outputs. Since you’re using φ1, the always clause can only
contain v1 (or s1) signals

• Inside the always block, you can only assign values to s2 signals. The signals used to
compute these values can only be of type v1

• Combinational logic should never mix v1 and v2 signals; if you’re using v1 inputs, the
outputs should be v1 (unless all inputs are s1 in which case the output becomes an s1
output).2

Convince yourself that such design indeed eliminates all race conditions.

2
In other words, the output of a combinational logic becomes the “lowest common denominator” of all
the inputs – if at least one of the inputs is v1 but not s1, the output must be v1