IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO.

1, JANUARY 1999 107

A Compact Rail-to-Rail Output Stage for CMOS Operational Amplifiers

Barbaros S.ekerkıran

Abstract— This paper presents a CMOS output stage devised

for driving heavy resistive loads. An operational amplifier of this
type has been fabricated in a 3-m double-polysilicon CMOS
technology. With a supply voltage of 75 V and load of 470 ,

the amplifier has a 74.6-V output swing and features a 60-mA

short-circuit output current. Although simple, the proposed con-
figuration enables the output transistors to be driven efficiently.
Index Terms— CMOS analog integrated circuits, operational
amplifiers, output stages.

I. INTRODUCTION

L OW-impedance drive capability along with high output

swing is a significant challenge in CMOS operational
amplifier output stage design since CMOS has emerged as
an industry standard. A popular approach for realizing high
swing output stage has been to employ a pseudosource fol-
lower, shown in Fig. 1, in which a common-source transistor
together with an error amplifier is used in place of source-
follower transistors. Proper control of the quiescent current is
a key design constraint due to the random threshold voltage
and high transconductance of pullup and pulldown devices.
Thus, any practical circuit must incorporate an additional
quiescent current stabilizing circuitry [1]. The output stage
of the amplifier by Fisher [2] uses the pseudosource follower
in parallel combination with a conventional class-AB source
follower. The real usefulness of the conventional source-
follower transistors lies in quiescent current control and in
reducing the excess phase shift introduced by error amplifiers
by providing a feedforward path to the output node at high
frequencies. The output swing capability of the amplifier by
Fisher has been improved by Nagaraj [3]. The improved
configuration has been used recently in the amplifier by Sæther
et al. [4].
This paper presents an output stage for CMOS operational
amplifiers, based on the topology using the conventional
class-AB source follower in parallel combination with a pseu-
dosource follower. In the proposed circuit, the source-follower
and the pseudosource-follower stages are merged in such a way
that the source-follower transistors are used as input devices
in error amplifiers.
Fig. 1. Pseudosource-follower architecture.
half error amplifiers AMP-P and AMP-N, respectively, the
common-source connected output transistors Mp7 and Mn7,
and the current stabilization circuit. The circuit uses a fully
symmetrical architecture. Since the negative-half subcircuit
formed by AMP-N and Mn7 is an inverted mirror image of the
positive-half subcircuit formed by AMP-P and Mp7, only the
latter will be discussed for the sake of brevity. Mn1 and Mp2
make up the input stage of AMP-P, the gate of Mn1 and the
source of Mp2 being the inverting and the noninverting inputs,
respectively. Also note that the input voltage , after being
level shifted by the source follower Mn1, is applied to the
gate of Mp2.
The feedback loop operates as follows. Assume that the
input and the output voltages are positive and that a large
resistive load pulls the output node toward ground. The
decreasing gate overdrive of Mp2 causes the drain current of
Mn3 to increase. This results in a higher gate-to-source voltage
for Mp7. The output voltage goes high until it reaches a level
where the drain current of Mn3 becomes equal to the sum of
the currents through Mp12 and Mp6. Ignoring the body effect,
the open-loop gain of AMP-P can be expressed as
(1)

II. CIRCUIT DESCRIPTION AND OPERATIONS
The circuit schematic of the new output stage is shown
in Fig. 2. The dimensions of relevant transistors are given in
Table I. The circuit consists of the positive-half and negative-
Manuscript received September 26, 1997; revised May 15, 1998.
The author is with the ETA ASIC Design Center and Electronics and Com-
munication Engineering Department, Istanbul Technical University, Istanbul
80626 Turkey.
Publisher Item Identifier S 0018-9200(99)00409-6.
0018–9200/99$10.00  1999 IEEE
where is the gate transconductance of Mp2 and
and are drain-to-source resistances of Mp6 and Mp12,
respectively. The output resistance of Mn3 has been neglected
since it forms the output transistor of a cascode configured
stage and consequently its value is high compared to the drain-
to-source resistances of Mn6 and Mp12. In this configuration,
the gate voltage of Mp7 can be pulled down to . Therefore,
for a given supply voltage, the highest possible current can be
obtained through Mp7.
108 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 1, JANUARY 1999

Fig. 2. Circuit schematic of the proposed output stage.

TABLE I
COMPONENT SIZES

The quiescent current stabilizer circuit includes transistors

Mn(p)8–Mn(p)12. The current through output transistors Mp7
and Mn7 is sensed by Mn8 and Mp8. Mp8, Mn9, and Mn8 Fig. 3. Photomicrograph of the complete operational amplifier.
are connected in series; hence the current through these three
transistors is equal to the saturated drain current of Mn8 or
Hence, the negative feedback mechanism prevents the lowest
Mp8, whichever is less. When the voltage produced across
of the currents through output transistors to exceed
Mn9 exceeds the sum of the threshold voltages of Mn10
and Mp10, these transistors become conductive. Since the
aspect ratio of Mn9 is selected small compared to that of (2)
Mn10 and Mp10, any increase in voltage across the diode-
connected Mn9 beyond causes a noticeable
enlargement in the current through Mn10 and Mp10. At where is the transconductance parameter of Mn9.
this point, the gate overdrive of Mn9 equals . The The positive-half and the negative-half subcircuits have
current flowing through Mn10 and Mp10 is mirrored by the been compensated using Miller capacitors and ,
Mn11–Mn12 and Mp11–Mp12 pairs striving for reduction of respectively. The transistors Mn13 and Mp13 serve as zero-
gate-to-source voltage of the output transistors Mp7 and Mn7. nulling MOS resistors.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 1, JANUARY 1999
; CLOAD = 100 pF
Fig. 4. Currents drawn from Vdd (IDD) and Vss (ISS) versus input voltage
with a resistive load of 470
.
Fig. 5. Step response of the output stage with a load of 470
jj2 2 nF for
:
an 8-VPP , 50-kHz square signal.
100 pF.
III. IMPLEMENTATION AND TEST RESULTS
An experimental operational amplifier that combines a high
gain input amplifier with a cascade connection with an output
stage based on the proposed architecture was designed and
fabricated in a 3- m, double-polysilicon CMOS technology.
Internal details of the input amplifier are outside the scope of
this paper. The photomicrograph of the operational amplifier
is shown in Fig. 3. The prototype enables testing of the output
stage independently of the input stage.
A. Output Stage
Fig. 4 shows the current drawn from the positive power
supply (IDD) and the negative power supply (ISS) as a
function of the input voltage. The step response of the output
stage with a load of 470 2.2 nF is shown in Fig. 5. Note that
the circuit is devised especially to drive heavy resistive loads,
and its settling behavior deteriorates for small resistive loads
connected in parallel with large capacitors. The short-circuit
output current is measured to be 60 mA. Since the bias current
is 300 A, the current efficiency, defined as the ratio of the
available output current to the bias current, is found to be 200.
109
TABLE II
OPERATIONAL AMPLIFIER PERFORMANCE SUMMARY. SUPPLY
7
VOLTAGE = 5 V, RLOAD = 470
Fig. 6. Second and third harmonics of the unity-gain connected amplifier
jj
versus output swing at 10 kHz with a load of 470
B. Complete Amplifier
The experimental results for the complete amplifier are sum-
marized in Table II. In Fig. 6, the second and third harmonics
are shown versus the output swing for a 10-kHz sinusoidal
signal into 470 100 pF.
IV. CONCLUSIONS
A new rail-to-rail output stage for CMOS operational ampli-
fiers has been presented. Unique error amplifier and quiescent
current stabilization circuits are combined to form a compact
circuit. This modification confers good current control and
high output swing capability to the output stage along with
a simple architecture.
ACKNOWLEDGMENT
The author would like to thank Prof. U. C.ilingiroglu for
his useful suggestions and the Semiconductor Technology
Research Laboratory (YITAL) of the Scientific and Techni-
110
cal Research Council of Turkey for the fabrication of the
experimental chips.
REFERENCES
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 1, JANUARY 1999
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