Agenda

Introduction: Session 3: SystemVerilog Assertions

SystemVerilog Motivation Language Tutorial
Vassilios Gerousis, Infineon Technologies Bassam Tabbara, Novas Software
Accellera Technical Committee Chair Tecnhology and User Experience
Session 1: Alon Flaisher, Intel
SystemVerilog for Design Using SystemVerilog Assertions
Language Tutorial and Testbench Together
Johny Srouji, Intel Jon Michelson, Verification Central
User Experience
Matt Maidment, Intel Session 4: SystemVerilog APIs
Doug Warmke, Model Technology
Session 2:
Session 5: SystemVerilog Momentum
SystemVerilog for Verification
Verilog2001 to SystemVerilog
Language Tutorial Stuart Sutherland, Sutherland HDL
Tom Fitzpatrick, Synopsys
User Experience SystemVerilog Industry Support
Faisal Haque, Verification Central Vassilios Gerousis, Infineon
Lunch: 12:15 – 1:00pm End: 5:00pm

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 SystemVerilog 3.1
Design Subset

Johny Srouji
Intel
Chair – SV-Basic Committee

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Presentation Outline
• Data Types
• Structures & Unions
• Literals
• Enumerated Data Types
• Constants & Parameters
• Scope & Lifetime
• Interfaces

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Basic SV3.1 Data Types
reg r; // 4-state Verilog-2001 single-bit datatype
integer i; // 4-state Verilog-2001 >= 32-bit datatype
bit b; // single bit 0 or 1
logic w; // 4-valued logic, x 0 1 or z as in Verilog
byte b8; // 8 bit signed integer
int i; // 2-state, 32-bit signed integer
shortint s;// 2-state, 16-bit signed integer
longint l; // 2-state, 64-bit signed integer

Make your own types using typedef

Use typedef to get C compatibility
typedef shortint short;
typedef longint longlong;
typedef real double;
typedef shortreal float;

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2 State and 4 State Data Types

reg a;
Verilog reg and integer
Verilog type bits can contain x
integer i;
SystemVerilog and z values

Equivalent to these
logic a;
SystemVerilog logic signed [31:0] i; 4-valued
SystemVerilog types

bit a; These SystemVerilog

SystemVerilog int i; types have two-valued
bits (0 and 1)

IfIfyou
youdon't
don'tneed
needthe
theXXand
andZZvalues
valuesthen
then
use
usethe
theSystemVerilog
SystemVerilogbit
bitand
andint
inttypes
types
which
whichMAKE
MAKEEXECUTION
EXECUTIONFASTER
FASTER

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Packed And Unpacked Arrays
a0
unpacked bit a [3:0]; a1
array of unused a2
bits a3
Don’t get them mixed up
packed
array of bit [3:0] p; p3 p2 p1 p0
bits

bit [15:0] memory [1023:0];

1k 16 bit memory[i] = ~memory[i];
unpacked memory[i] [15:8] = 0;
memory
Packed indexes
can be sliced

1k 16 bit Can operate on

packed bit [15:0] [1023:0] Frame; entire memory
always @inv Frame = ~Frame;
memory

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Structures
struct { bit [7:0] opcode;
bit [23:0] addr;
} IR; // anonymous structure

Like
LikeininCCbut
butwithout
without
the
theoptional
optionalstructure
structure
tags
tagsbefore
beforethe
the{{

typedef struct { bit [7:0] opcode;

bit [23:0] addr;
} instruction; // named structure type

instruction IR; // define variable

IR.opcode = 1; // set field in IR

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Unions
typedef union { union
int n;
real f; provide storage for
again,
again,like
likeininCC
} u_type; either int or real

u_type u;
structs and unions can be
initial assigned as a whole
begin Can be passed through
u.n = 27; int
tasks/functions/ports as a
$display("n=%d", u.n);
whole
u.f = 3.1415; real
$display("f=%f",u.f); can contain fixed size packed
$finish(0); or unpacked arrays
end

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 Packed Structures
Represents bit or part selects of vectors
struct packed { reg [24:0] Entry;
bit Valid; `define Valid 24
byte Tag; `define Tag 23:16
bit [15:0] Addr;
} Entry; `define Addr 15:0
iTag = Entry.Tag; iTag = Entry[`Tag];
iAddr = Entry.Addr; iAddr = Entry[`Addr];
iValid = Entry.Valid iValid = Entry[`Valid]
32 0
2
packed unpacked Valid
packedstruct
structmay
may struct 1 Tag
contain
containother
otherpacked
packed 0 Addr
structs
structsor
orpacked
packedarrays
arrays 24 23 1615 0
Valid Tag Addr
packed
struct

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SV 3.1 Literals
• SV literal values are extensions of those
for Verilog reg [31:0] a,b;
reg [15:0] c,d; This works
...
a = 32'hf0ab;
like in Verilog
c = 16'hFFFF

Adds the ability to a = '0; This fills the packed

specify unsized literal b = '1; array with the same
c = 'x; bit value
single bit values with d = 'z;
a preceding ‘
logic [31:0] a; These are
...
a = 32'hffffffff; equivalent
a = '1;

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SV 3.1 Literals

This works
like in Verilog Adds time literals
#10 a <= 1;
#5ns b <= !b;
#1ps $display("%b", b);

You can also

specify delays with
explicit units

Similar to C, but with Adds Array literals

the replication operator int n[1:2][1:3] = {{0,1,2},{3{4}}}
({{}}) allowed

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Enumerated Data Types
enum {red, yellow, green} light1, light2; anonymous int
type

enum {bronze=3, silver, gold} medal; silver=4, gold=5

enum {a=0, b=7, c, d=8} alphabet; Syntax error

enum {bronze=4’h3, silver, gold} medal;

silver=4’h4,
gold=4’h5

typedef enum {red, green, blue, yellow, white, black} Colors;

Colors col;
integer a, b;
a=2*3=6
a = blue * 3; col=3
col = yellow; b=3+1=4
b = col + green;

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 Type Casting
int'(2.0 * 3.0) A data type can be changed
shortint' {8’hFA, 8’hCE} by using a cast (‘) operation
17 ' (x – 2)

• Any aggregate bit-level object can be reshaped Objects

Objectsmust
musthave
have
– Packed ⇔ Unpacked, Array ⇔ Structure identical
identicalbit
bitsize
size
typedef struct {
bit [7:0] f1;
f1 A
bit [7:0] f2;
bit [7:0] f3[0:5]; f2
} Unpacked_s;
typedef struct packed { f30 f31 f32 f33 f34 f35
bit [15:0][0:2] f1;
bit [15:0] f2;
} Packed_s; B
Unpacked_s A;
Packed_s B; f10 f11 f12 f2
…
A = Unpacked_s’(B);
B = Packed_s’(A);
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Constants
• Use like defines or parameters
• Global constant (const) is resolved at the END of
elaboration.
• Local constant (localparam) is resolved at the BEGINNING
of elaboration.
– No order dependency problems when compiling
• specparam is used for specify blocks
const bit TRUE = 1;
global constant
const logic option = a.b.c; Can’t be
Can contain an expression overridden
module top; with
with any hierarchical path name localparam int TRUE = -1; defparam
localparam bit FALSE = 0;
local constant
initial
$display(“TRUE=%d", TRUE); // -1
endmodule

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 Parameters
module top;
logic clk; Override parameters
by name
clockgen #(.start_value(1'b1), .delay(50),
.ctype(int)) c (clk);

always @clk $display("t=%t clk=%b", $time, clk);

initial
begin
repeat(10) @(posedge clk) ;
$finish(0);
end
Parameter used
endmodule before definition

module clockgen (output ctype clk);

parameter logic start_value=0;
parameter type ctype=bit;
parameter time delay=100;

initial clk <= start_value;

Parameters can have
always #delay clk <= !clk; explicit type

endmodule
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Variable Types
• Static variables
– Allocated and initialized at
time 0
– Exist for the entire
simulation
• Automatic variables
– Enable recursive tasks and
functions
– Reallocated and initialized
each time entering a block
– May not be used to trigger
an event
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• Global variables
– Defined outside of any module
(i.e. in $root)
– Accessible from any scope
– Must be static
– Tasks and functions can be
global too
• Local variables
– Accessible at the scope where
they are defined and below
– Default to static, can made
automatic
– Accessible from outside the
scope with a hierarchical
pathname
 Scope and Lifetime
top inst;
data declared outside
of modules is static int max = 10;
and global int n;
module top;
int n;
initial begin
i is automatic and automatic int i;
local to that block n = 1; data declared inside
for (i=2; i<=max; i++) of a module is static
n *= i; and available to all
end tasks and functions in
initial begin : myblock that module
n = 1;
for (int i=2; i<=max; i++)
n *= i;
global n $root.n = n; local n
end
endmodule

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Task and Function Arguments
• Default Arguments
– Definition: task foo(int j=5, int k=8);
– Usage: foo(); foo(5); foo(,8); foo(5,8);
• Pass by Name
foo(.k(22)); // j uses default
Optional “read-only” qualifier
• Pass by Reference
– Declaration: task tk([const] ref int[1000:1] ar);
– Usage: tk(my_array); // note: no ‘&’

Simplifies Task/Function Usage

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 Familiar C Features In
SystemVerilog
do continue starts
begin next loop iteration works with:
for
if ( (n%3) == 0 ) continue;
while
if (foo == 22) break; forever
end break exits repeat
while (foo != 0); the loop do while
…
Blocking Assignments Extra parentheses
if ( (a=b) ) … required to distinguish
as expressions while ((a = b || c)) from if(a==b)

Auto increment/ x++;

decrement operators if (--c > 17) c=0;
Assignment Operators
a += 3; Semantically equivalent
s &= mask; to blocking assignment
Wildcard Comparisons f <<= 3;
X and Z values act as
a =?= b
wildcards
a !?= b
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SystemVerilog Interfaces
Design On A White Board HDL Design

Complex signals
SystemVerilog Bus protocol repeated in blocks
Interface Bus Hard to add signal through hierarchy
Design Signal 1
Signal 2
Read()
Communication encapsulated in interface
Write()
- Reduces errors, easier to modify
Bus Bus Assert
- Significant code reduction saves time
- Enables efficient transaction modeling
Bus
- Allows automated block verification

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What is an Interface?
• Provides a new hierarchical structure
– Encapsulates communication
– Captures Interconnect and Communication
– Separates Communication from Functionality
– Eliminates “Wiring” Errors
– Enables abstraction in the RTL

int i; int i;
logic [7:0] a; wire [7:0] a;

typedef struct { interface intf;

At
Atthethesimplest
simplest int i;
int i; level an interface
logic [7:0] a; level an interface wire [7:0] a;
isistotoaawire
wire endinterface : intf
} s_type;
what
whataastruct structisis
totoaavariable
variable

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How Interfaces work
interface intf;
bit A,B;
byte C,D; modA intf modB
logic E,F;
endinterface
Instantiate
intf w; Interface An interface is similar to a module
straddling two other modules
modA m1(w);
modB m2(w);
An
Aninterface
interfacecan
cancontain
contain
module modA (intf i1); anything
anythingthat
thatcould
couldbebeininaa
endmodule module
moduleexcept
exceptother
other
module modB (intf i1); module
moduledefinitions
definitionsor
or
endmodule instances
instances

Allows structuring the information flow between blocks

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 Example without Interface
module memMod(input logic req,
bit clk,
logic start,
logic[1:0] mode,
logic[7:0] addr,
inout logic[7:0] data,
output logic gnt,
logic rdy);
always @(posedge clk)
gnt <= req & avail;
endmodule
module top;
logic req,gnt,start,rdy;
bit clk = 0;
logic [1:0] mode;
logic [7:0] addr,data;
memMod mem(req,clk,start,mode,
addr,data,gnt,rdy);
cpuMod cpu(clk,gnt,rdy,data,
req,start,addr,mode);
endmodule

module cpuMod(input bit clk,

Top clk
logic gnt, req
logic rdy, start
inout logic [7:0] data, gnt
rdy
output logic req,
CPU Mem
mode[1:0]
logic start,
addr[7:0]
logic[7:0] addr,
logic[1:0] mode); data[7:0]
endmodule

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Example Using Interfaces
Bundle signals interface
interface simple_bus; module top; instance
in interface
logic req,gnt; bit clk = 0;
logic [7:0] addr,data; simple_bus sb_intf; Connect
logic [1:0] mode; interface
logic start,rdy; memMod mem(sb_intf, clk);
endinterface: simple_bus
cpuMod cpu(.b(sb_intf),
Use interface .clk(clk));
keyword in port list endmodule
module memMod(interface a,
input bit clk); Top clk
logic avail;
always @(posedge clk)
a.gnt <= a.req & avail; sb_intf
CPU Mem
endmodule
Refer to intf
signals
module cpuMod(interface b,
input bit clk);
endmodule
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 Encapsulating Communication
interface serial(input bit clk);

Parallel Interface logic data_wire;

logic data_start=0;
interface parallel(input bit clk);
task write(input data_type d);
logic [31:0] data_bus;
for (int i = 0; i <= 31; i++)
logic data_valid=0;
begin
if (i==0) data_start <= 1;
task write(input data_type d);
else data_start <= 0;
data_bus <= d;
data_wire = d[i];
data_valid <= 1;
@(posedge clk) data_wire = 'x;
@(posedge clk) data_bus <= 'z;
end
data_valid <= 0;
endtask
endtask
task read(output data_type d);
task read(output data_type d);
while (data_start !== 1)
while (data_valid !== 1)
@(negedge clk);
@(posedge clk);
for (int i = 0; i <= 31; i++)
d = data_bus;
begin
@(posedge clk) ;
d[i] <= data_wire;
endtask
@(negedge clk) ;
end
endinterface
endtask
Serial Interface
endinterface
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Using Different Interfaces
typedef logic [31:0] typedef logic [31:0]
data_type; data_type;

bit clk; bit clk;

always #100 clk = !clk; always #100 clk = !clk;

parallel channel(clk); serial channel(clk);

send s(clk, channel); send s(clk, channel);
receive r(clk, channel); receive r(clk, channel);

module send(input bit clk,

send interface i);
receive
data_type d;
Module inherits
parallel
serial
interface ...
communication
i.write(d); method from
endmodule interface

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Conventional Verification
Strategy
• Pre- tbA tbB • Testbench reuse
Integration problems
• tbA and tbB separate
Test A B
Subblocks in
isolation

• Complex
• Post- tbS interconnect
Integration S • Hard to create tests
to check all signals
Need to check A B • Slow, runs whole
interconnect,
structure (missing design even if only
wires, twisted structure is tested
busses) as well as
functionality

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 SystemVerilog Verification
Strategy
• Interfaces provide
• Pre- tbI
tbA tbB
reusable
Integration I I
components
I
• tbA and tbB are
A B ‘linked’
Test interface
in isolation • Interface is an
executable spec
tbS • Wiring up is simple
and not error
S
• Post-Integration prone
A I
B • Interfaces can
contain protocol
checkers and
coverage counters
Protocol bugs
already flushed out

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SystemVerilog Interfaces: The
Key to Design Exploration
• Interfaces Encapsulate
Data and How Data Move
Between Blocks
• Design Exploration is All
About Looking at
Alternatives BlkA BlkB

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SystemVerilog Interfaces: The
Key to Design Exploration
• Interfaces Encapsulate
Data and How Data Move
Between Blocks
• Design Exploration is All
About Looking at
Alternatives BlkA BlkB
• Interfaces Should
Support Multiple Layers
of Abstraction for both
“Send” and “Receive”
– Shield BlockA from
Abstraction Changes in
BlockB

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