Com binational Logic

149
CAB
HS1
D1
Bo1
HS2
D2
Bo2
Bout
D if fe re nce
Fig. 4.11 (a)

D 1 a n d B 01 a r e o u t p u t s o f f i r s t h a l f s u bt r a c t o r ( H S I )

D 2 a n d B 02 a r e o u t p u t s o f s e c o n d h a l f s u b t r a c t o r ( H S 2)

A, B and C are inputs of full subtractor.

Difference and Bovt are outputs of ful l subtractor.

4.1.3 Code Converters

In the previous study of codes, coding was defined as the use of groups of bits to
represent items of information that are multivalued. Assigning each item of information a
unique combination of bits makes a transformation of the original information. This we
recognize as information being processed into another form. Moreover, we have seen that
there are many coding schemes exist. Different digital systems may use different coding
schemes. It is sometimes necessary to use the output of one system as the input to other.
Therefor a sort of code conversion is necessary between the two systems to make them
com pati bl e for the same inform at ion.
 ‘A code converter is a combinational logic circuit that changes data presented in one type
of binary code to another type of binary code.’ A general block diagram of a code converter is
shown in Fig. 4.12.

Code
Converter
Code X
Code Y
Fig. 4.12 Code conerter
To understand the design procedure; we will take a specific example of 4-bit Binary to
Gray code conversion.
1. The block diagram of a 4-bit binary to gray code converter is shown in Fig. 4.13.
4 -bit
bina ry
input
Binary
to
Gray
Code
Converter
B3

B2 B1 B0

G3

G2 G1 G0

4 -bit
Gary
Code
Output
F i g. 4. 1 3
I f h a s f o u r i n p ut s ( B 3 B 2 B 1 B 0) r e p r e s e n t i n g 4 - b i t b i n a r y n u m b e r s a n d f o u r o u t p u t s
(G 3 G 2 G 1 G 0) representing 4-bit gray code.
150 S w i t c h i n g T h e o r y
2. Trut h tabl e for bi nary to gray code converters.
Bi nary Inputs
Gray code Outputs
B3
B2
B1
B0
G3
G2
G1
G0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
0
0
1
1
0
0
1
0
1
0
1
1
1
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
0
1
0
0
0
1
1
0
0
1
0
0
1
1
1
0
1
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
0
0
1
0
1
0
1
1
0
1
1
0
1
1
1
1
1
0
1
0
0
1
1
1
1
1
1
0
0
0
3 . N o w w e s o l v e a l l t h e g r a y o u t p u t s d i s t a n t l y w i t h r e s p e c t t o b i n a r y i n p u t s F r om t h e
t ruth t able; the logic expressi ons for the gray code outputs can be wri tten as

G 3 = S (8, 9, 10, 11, 12, 13, 14, 15)

G 2 = Σ (4, 5, 6, 7, 8, 9, 10, 11)
G 1 = Σ (2, 3, 4, 5, 10, 11, 12, 13)

G 0 = Σ (1, 2, 5, 6, 9, 10, 13, 14).

The above expressions can be simplified using K-map
Map for G 3:
F rom t he octet, we get
G 3 = B 3
Map for G 2:
From the two quads, we get
G 2 = B 3' B 2 + B 3 B 2'
= B 3 ⊕ B 2.
1
1
1
1
00
01
11
10
01
00
B B
1 0
B B
3 2
1
1
1
1
11
10
1
1
1
1
00
01
11
10
01
00
B B
1 0
B B
3 2
1
1
1
1
11
10
Com binational Logic
151
Map for G 1:
From the two quads, we get
G 1 = B 2 B 1' + B 2' B 1
= B 2⊕ B 1
Map for G 0:
From the two quads, we get
G 0 = B 1'B 0 + B 1B 0'
= B 1 ⊕ B 0.
4. Now the above expressions can be implemented using X-OR gates to yield the
disired code converter circuit shown in Fig. 4.14.
B0
B1
B2
B3

G0 G1 G2

G3
Binary
Input
Gray
Output
F i g. 4. 1 4
Let us see one more example of XS-3 to BCD code converter.
1. The block diagram of an XS-3 to BCD code converter is shown in Fig. 4.15.
I t h a s f o u r i n p u t s ( E 3, E 2, E 1, E 0) r e p r e s e n t i n g 4 b i t X S - 3 n um b e r a n d f o u r o u t p u t s
(B 3B 2 B 1 B 0) representing 4-bit BCD code.
4 bit
XS-3
Input
Excess-3
to
BCD
code
converter
E3

E2 E1 E0

B3

B2 B1 B0

4 -bit
BCD
Coded
Output
F i g. 4. 1 5
2. Truth Table for XS-3 to BCD code converter.

XS-3 codes are obtained from BCD code by adding 3 to each coded number. Moreo- ver 4
binary variables may have 16 combinations, but only 10 are listed. The six not listed are don’t
care-combinations (since in BCD codes, we use only to members
1
1
1
1
00
01
11
10
01
00
B B
1 0
B B
3 2
1
1
1
1
11
10
1
1
1
1
00
01
11
10
01
00
B B
1 0
B B
3 2
1
1
1
1
11
10
152 S w i t c h i n g T h e o r y

viz. 0, 1, 2, ....9). Since they will never occur, we are at liberty to assign to the output variable
either a 1 or a 0, whichever gives a simpler circuit. In this particu- l ar exam pl e, the unused i/ o
com bi nati ons are list ed below the t ruth t able.

Min
E xcess-3
BCD
Decim al
Term s
Inputs
Out puts
Equivalent
E3
E2
E1
E0
B3
B2
B1
B0
m3
0
0
1
1
0
0
0
0
0
m4
0
1
0
0
0
0
0
1
1
m5
0
1
0
1
0
0
1
0
2
m6
0
1
1
0
0
0
1
1
3
m7
0
1
1
1
0
1
0
0
4
m8
1
0
0
0
0
1
0
1
5
m9
1
0
0
1
0
1
1
0
6
m1 0
1
0
1
0
0
1
1
1
7
m1 1
1
0
1
1
1
0
0
0
8
m1 2
1
1
0
0
1
0
0
1
9
Unused I/Ps
Out puts
m0
0
0
0
0
x
x
x
x
m1
0
0
0
1
x
x
x
x
m2
0
0
1
0
x
x
x
x
m1 3
1
1
0
1
x
x
x
x
m1 4
1
1
1
0
x
x
x
x
m1 5
1
1
1
1
x
x
x
x
* XS-3 is also a class of BCD codes.
3. Now we sol ve all t he BCD output s. F rom t he t ruth t able, the l ogi c expressions for
t he BC D coded outputs can be wri tten as :
B3 =Σ (m11 , m12 ), d (m0, m1, m2, m13 , m14 , m15 )

B2 =Σ (m7, m8, m9, m10 ), d (m0, m1, m2, m13 , m14 , m15 )

B1 =Σ (m5, m6, m9, m10 ), d (m0, m1, m2, m13 , m14 , m15 )

B0 =Σ (m4, m6, m8, m10 , m12 ), d (m0, m1, m2, m13 , m14 , m15 ).

These expressions can be simplified using k-map →

1
00
01
11
10
01
00
E E
1 0
E E
3 2
1
X
X
X
11
10
X
X
X
Map f or B 3→
1
00
01
11
10
01
00
E E
1 0
E E
3 2
1
X
X
X
11
10
X
X
X
Map f or B 2→
1
1
⇒ B 3 = E 3 E 2 + E 3E 1E 0
⇒ B 2 = E 2' E 0' + E 2 E 1 E 0