Physical Design Methodology Best Practices

NANOMETER AND RTL-DOWN CLOSURE

Aurangzeb Khan
Simplex Solutions, Inc.

IEEE DATC Electronic Design Processes Workshop

Monterey, CA

April 9-10, 2001

Simplex Solutions, Inc. ©2001 – All Rights Reserved 1 IEEE DATC EDP; April 9-10, 2001
 SOC design opportunities & challenges
n First-to-Market & Volume SOCs àBusiness Success
2
‘00 Mfg. Lifecycle
u No market … for a 2nd to market 1.5

Norm. #
'96 Mfg. Lifecycle
u 3-months late = $500M loss 1
0.5
0

21

27
1
3

12
15
18

24
9
6
Time (Months)

n Limited design capacity

u Competitive new products roadmap
u Customize products
u Access new processes first
u Multiple sourcing

n Rapid increase in design complexity

Simplex Solutions, Inc. ©2001 – All Rights Reserved 2 IEEE DATC EDP; April 9-10, 2001
VLSI à SOC: Rapid increase in design complexity
n 0.5um à0.18um Data I/O *
n 5x5 mm2 à 21.7x21.3 mm2
n ~0.8 à 287.5M transistors 32 Mb 32 Mb 32 Mb 32 Mb
n 3LM à 6LM eDRAM eDRAM eDRAM eDRAM
n ~50 à 150 MHz (#>500MHz)
#

Microprocessor Interface

Distribution

Distribution
Data I/O
Power

Power
Synthesized Blocks

#: Cirrus Logic, Inc. IC, 3Ci™ 32 Mb 32 Mb 32 Mb 32 Mb

*: Sony Computer Entertainment, Inc. &
Sony Corporation Graphics eDRAM eDRAM eDRAM eDRAM
Synthesizer®I-32. Copyright 2000
Sony Computer Entertainment, Inc. Data I/O
ISSCC2001, 9.6

Simplex Solutions, Inc. ©2001 – All Rights Reserved 3 IEEE DATC EDP; April 9-10, 2001
 VLSI à SOC: Hierarchical design approach
n SOC Design = IP block creation + block integration
Time-to-Market Time-to-Volume
1000

duc
ts n Enable concurrent engineering
ro
eP
ltipl
n Reduce development complexity
Mu
Chip Design Complexity

SOC
n Simplify program management
100 gy
eth
odolo
n Leverage proven IP blocks
edM e Higher Cost
nc us
En
ha
Re u Improve TTM, TTV and quality
IP
ce
ur

u Reduce technical, schedule risks

so
Re

Digital
al
ion

n Leverage platform infrastructure

A

10
dit
Ad

VLSI
Higher Leverage

y
u Verification, Validation
log
odo
eth
nal M
tio
en
onv
C
1
0 6 9 12 15
Chip Development Time

Simplex Solutions, Inc. ©2001 – All Rights Reserved 4 IEEE DATC EDP; April 9-10, 2001
 Top-level SOC design methodology
Design Specs SOC Functional Partitioning

I/O, power, clock, test

Analog FE Fnl., Si. Fnl. Top-level uP porting, RAM, ROM I/O Design, PLL, Clock
Design Design Design Verification optimization Ckt. Design SI Design

Fn., Fn., .subckt, .subckt, .subckt,

GDS2 GDS2 GDS2 GDS2 GDS2

Top-level + HDC silicon design

Reqmts. ERC, DRC, LVS n “Black-box” models

Tape-out

n Functional design à hierarchical

n Electrical / physical design à hierarchical
n IP leverage; Customer-specific design
Simplex Solutions, Inc. ©2001 – All Rights Reserved 5 IEEE DATC EDP; April 9-10, 2001
 Block-level design methodology
Design Specs VHDL Design
n Architectural optimization (timing)
Constraints
n Inter-group buses, bandwidth
Synthesis
Lib.+SWLM n Clock, SI, test; validation

Lib.+CWLM
Floor-planning n Custom WLM (or better)
n Power, clock, test reqmts. added
Formal Synthesis
n Critical blocks (e.g., ECC)
Power, clock, SI, I/O n Top-, block-specific CWLM-based
(or better)
Pre-layout Timing n With added constraints
P&R, testability n Top, block clock design
n I/O driver, padring design
Post-layout timing n Noise minimization, isolation
n Power distribution (Internal, I/O)
Fnl., pwr., SI ECO n Board-level timing, SI
Reqmts. ERC, DRC, LVS n Scan stitching, re-ordering
n Full RC back-annotation
Tape-out n Hierarchical “black-box” models

Simplex Solutions, Inc. ©2001 – All Rights Reserved 6 IEEE DATC EDP; April 9-10, 2001
 Sony Computer Entertainment: GS ®I-32
n Enhanced architecture: 8x higher eDRAM vs. PS®2 GS ®
Data I/O n Performance
u eDRAM Bandwidth = 48 GB/s
eDRAM eDRAM eDRAM eDRAM u Buses >2K bits wide
u Render 75M polygons/s
Microprocessor Interface

n SOC integration
u 280M + 7.5M transistors
Distribution

Distribution
Data I/O
u 21.7 x 21.3 mm2
Power

Power
Synthesized Blocks
n Scale
u >400K components
l 11 blocks, 31K-218K gates
l >68K flip-flops
eDRAM eDRAM eDRAM eDRAM
u >500K signal nets

Data I/O l >2K nets >10 mm. long

ISSCC2001 9.6 n 0.18 um, 6-metal CMOS
Simplex Solutions, Inc. ©2001 – All Rights Reserved 7 IEEE DATC EDP; April 9-10, 2001
 Design approach
n Fully-hierarchical design: Netlist to tape-out in 10 weeks

n Design challenges
RTL, Synthesis u Power distribution
u Clock architecture
FP, S, C, P&R FP, S, C, P&R
Concurrent u Timing design
Timing, SI, V Design Timing, SI, V l Load modeling
l Delay calculation
Parallel Verification (0...N) u Signal Integrity
Tape-out l Buffer insertion
FP: Floorplan l Crosstalk
S: Synthesis
C: Clock
P&R: Place-&-Route
SI: Signal Integrity
V: ERC, DRC, LVS

Simplex Solutions, Inc. ©2001 – All Rights Reserved 8 IEEE DATC EDP; April 9-10, 2001
 Accurate fully-hierarchical delay calculation
n Fully-hierarchical block-based timing analysis
u Analyze large designs (scalable capacity)

u Enable concurrent design

u Faster timing convergence, verification (STA)

n Signal paths traverse hierarchy

u Block inputs with ~0 – 2 mm. metal à RC delay

A B C D S
SET
Q
A B C D
L
SET
S Q

CL
R Q

IC B1
CLR
R Q

IC B1
CLR

n Model block boundary pin input RC as C L

n CL à timing inaccuracies when RC significant
Simplex Solutions, Inc. ©2001 – All Rights Reserved 9 IEEE DATC EDP; April 9-10, 2001
 Accurate fully-hierarchical timing
n CL over-estimates RC delay
C eff(50%) u Latent hold time defects
u Setup à overdriven
RC CLB1
n ECSM (Ceff(50%) ) fits SPICE at
threshold
Voltage (V)

A B
Ceff(50%) n ECSM à ~2% correlation to
SPICE for complex topologies
A B C D B1 1.56
CL 1.54 +2%
IC

Delay (ns)
1.52
A B C D B1' 1.50
1.48 ECSM
SPICE
IC 1.46
1.43 1.48 1.53
Time (ns) Delay (ns)
Simplex Solutions, Inc. ©2001 – All Rights Reserved 10 IEEE DATC EDP; April 9-10, 2001
 Signal integrity
33% n Insert buffers ~1.5 - 2.5 mm.
Inc. Delay (%)

0.25 u Bound timing uncertainty

23%
u Reduce total delay
13%
0.15 A B
3%
0.5 1.5 X mm.

Wire Length (mm.) A B

12 X/2 mm. X/2 mm.

(0.5mm. norm )

10 w/o buffer

n Address impact in Static Timing

8
Delay

6
4 Analysis
2 w/ 1 buffer u Reduce setup time margin
u Bounded hold time margin
0
0.5 2.5
Wire Length (mm.)

Simplex Solutions, Inc. ©2001 – All Rights Reserved 11 IEEE DATC EDP; April 9-10, 2001
 IC design à design methodology, technology
n Hierarchical (mixed-signal) design
u Fully-hierarchical timing: Enhance concurrent design

n Power distribution
n Clocking architecture
n New design technology
u Nonlinear delay calculation technology
u Black-box, gray-box modeling
u Signal integrity
l RC transmission line effects
l Crosstalk management
l Buffer insertion
n 0.15um – 0.13um work
u Technology validation, signal integrity, RLC, substrate, others

n Focus on silicon engineering: First silicon success

Simplex Solutions, Inc. ©2001 – All Rights Reserved 12 IEEE DATC EDP; April 9-10, 2001
 Related reading
n A. Khan, et. al., “A 150 MHz Graphics Rendering Processor with 256Mb Embedded
DRAM,” Digest of Technical Papers, pp. 150-151, 442, International Solid State
Circuits Conference, February 5-7, 2001, San Francisco
n S. Nassif, “Delay Variability: Sources, Impacts and Trends,” pp. 369-69, Digest of
Technical Papers, International Solid State Circuits Conference, February 2000
n A. Khan, “Design Challenges in Cirrus Logic, Inc. 3Ci™ System-on-a-Chip
Development,” SOC Design Seminar, Stanford University, May 1999
n S. Nemazie, A. Khan, et. al., “260 Mb/s Mixed-Signal Single-Chip Integrated System
Electronics for Magnetic Hard Disk Drives,” Digest of Technical Papers, pp. 42-43,
443, and Slide Supplement 1999 to the Digest of Technical Papers, pp. 44-45,
International Solid State Circuits Conference, February 15-17, 1999, San Francisco
n R. Baird, et. al., “A Mixed-Signal 120Msample/s PRML Solution for DVD Systems,”
Digest of Technical Papers, pp. 38-39, 442, and Slide Supplement 1999 to the Digest
of Technical Papers, pp. 40-41, 378 International Solid State Circuits Conference,
February 15-17, 1999, San Francisco
n S. Naffziger, “Design Methodologies for Interconnects in GHz+ ICs,” International
Solid State Circuits Conference Short Course, February 1999
n “Semiconductor Perspectives: Top Ten Stories of 1998," Int’l. Data Corp., 1/99

Simplex Solutions, Inc. ©2001 – All Rights Reserved 13 IEEE DATC EDP; April 9-10, 2001
 Acknowledgments; Copyright notice
n We greatly appreciate the support of:
u Cirrus Logic, Inc.
u Sony Computer Entertainment, Inc.
u Sony Corporation Semiconductor Network Company
u Sony Kihara Research Center, Inc.

n Registered trademarks and copyright material of

Cirrus Logic, Inc., Sony Computer Entertainment, Inc.
and Sony Corporation used with permission
n All rights are reserved by the respective companies
u No part of this material may be used without the prior written
consent of Cirrus Logic, Inc., Sony Computer Entertainment,
Inc., Sony Corporation and Simplex Solutions, Inc.

Simplex Solutions, Inc. ©2001 – All Rights Reserved 14 IEEE DATC EDP; April 9-10, 2001