Computer Organization & Architecture

Lecture #15

A View of Computer Function and Interconnection

Interconnections Structures

A computer consists of a set of components or modules (processor, memory, I/O)

that communicate with each other. A computer is a network of modules. There
must be paths for connecting these modules. The collection of paths connecting the
various modules is called the interconnection structure.

• Memory
o Consists of N words of equal length
o Each word assigned a unique numerical address (0, 1, …, N-1)
o A word of data can be read or written
o Operation specified by control signals
o Location specified by address signals

• I/O Module
o Similar to memory from computers viewpoint
o Consists of M external device ports (0, 1, …, M-1)
o External data paths for input and output
o Sends interrupt signal to the processor
• Processor
o Reads in instructions and data
o Writes out data after processing
o Uses control signals to control overall operation of the system
o Receives interrupt signals

The preceding list defines the data to be exchanged. The interconnection structure
must support the following types of transfers:

• Memory to processor: processor reads an instruction or a unit of data from

memory.
• Processor to memory: processor writes a unit of data to memory.
• I/O to processor: processor reads data from an I/O device via an I/O module.
• Processor to I/O: processor sends data to the I/O device via an I/O module.
• I/O to or from memory: an I/O module is allowed to exchange data directly
with memory, without going through the processor, using direct memory access
(DMA).

Over the years, a number of interconnection structures have been tried. By far the
most common is the bus and various multiple-bus structures.

Bus Interconnection

A bus is a communication pathway connecting two or more devices. Multiple

devices can be connected to the same bus at the same time. Typically, a bus
consists of multiple communication pathways, or lines. Each line is capable of
transmitting signals representing binary 1 or binary 0. A bus that connects major
computer components (processor, memory, I/O) is called a system bus.
Bus Structure

Typically, a bus consists of 50 to hundreds of separate lines. On any bus the lines
are grouped into three main function groups: data, address, and control. There may
also be power distribution lines for attached modules.

• Data lines
o Path for moving data and instructions between modules.
o Collectively are called the data bus.
o Consists of: 8, 16, 32, 64, etc… bits – key factor in overall system
performance
• Address lines
o Identifies the source or destination of the data on the data bus.
ƒ CPU needs to read an instruction or data from a given memory
location.
o Bus width determines the maximum possible memory capacity for the
system.
ƒ 8080 has 16 bit addresses giving access to 64K address
• Control lines
o Used to control the access to and the use of the data and address lines.
o Transmits command and timing information between modules.

Typical control lines include the following:

• Memory write: causes data on the bus to be written to the addressed memory
location.
• Memory read: causes data from the addressed memory location to be placed
on the bus.
• I/O write: causes data on the bus to be output to the addressed I/O port.
• I/O read: causes data from the addressed I/O port to be placed on the bus.
• Transfer ACK: indicates that data have been from or placed on the bus.
• Bus request: indicates that a module needs to gain control of the bus.
• Bus grant: indicates that a requesting module has been granted control of the
bus.
• Interrupt request: indicates that an interrupt is pending.
• Interrupt ACK: indicates that the pending interrupt has been recognized.
• Clock: used to synchronize operations.
• Reset: initializes all modules.

What does a bus look like?

• Parallel lines on a circuit board.

• Ribbon cables.
• Strip connectors of a circuit board.
o PCI, AGP, PCI Express, SCSI, etc…
• Sets of wires.

Multiple-Bus Hierarchies

If a great number of devices are connected to the bus, performance will suffer.

• Propagation delays
o Long data paths mean that coordination of the bus use can adversely
affect performance.
• If aggregate data transfer approaches capacity
o Increasing data rate or making the bus wider may help.

Most computer systems use multiple buses, generally laid out in a hierarchy.
The traditional bus architecture shown in the previous figure is reasonably efficient
but begins to break down as higher and higher performance is seen in the I/O
devices. In response to these growing demands, a common approach taken by
industry is to build a high-speed bus that is closely integrated with the rest of the
system, requiring only a bridge between the processor’s bus and the high-speed
bus. This arrangement is sometimes known as a mezzanine architecture. The figure
below shows an example of using this approach:

Elements of Bus Design

Bus Type

• Dedicated
o Separate data and address lines
• Multiplexed
o Shared lines
o Address valid or data valid control line
o Advantage
ƒ Fewer lines – saves space, lower cost
o Disadvantage
ƒ More complex control
ƒ Potential reduction in performance
Method of Arbitration

Because only one unit at a time can successfully transmit over the bus, some
method of arbitration is needed.

• Centralized
o Bus controller of arbiter is responsible for allocating time on the bus
o May be part of processor or may be separate
• Distributed
o Each module may claim control of the bus
o Each module contains access control logic

Timing

Timing refers to the way in which events are coordinated of the bus.

• Synchronous
o Events determined by clock signals
o Control bus includes a clock line
o A single 1-0 is a bus cycle
o Usually synched on leading edge
o Usually a single cycle for an event
• Asynchronous
o One event on a bus follows and depends on the occurrence of a previous
event

Synchronous timing is simpler to implement and test. However, it is less flexible

that asynchronous timing.

Bus width

The width of the data bus has an impact on system performance: The wider the
data bus, the greater the number of bits transferred at one time.

The width of the address bus has an impact on system capacity: The wider the
address bus, the greater the range of locations that can be referenced.

Data Transfer Type

• Multiplexed
o Single shared bus for both addresses and data
o Bus first used to specify an address
o Bus then used to transfer data
• Dedicated
o Separate buses for both address and data
o The address is specified on the address bus and remains while data
transferred
o The data is transferred on the data bus
PCI

• Peripheral Component Interconnection

• 1990 Intel released to public domain
• 66 MHz
• 528 Mbytes/sec

Figure (a) shows a typical use of PCI in a single-processor system. Figure (b)
shows a typical use of PCI in a multiprocessor system. Notice that more than one
PCI configuration may be used.
Bus Structure

• 49 mandatory signal lines – see Table 3.3

o System lines
ƒ clock and reset
o Address & data lines
ƒ 32 multiplexed for address and data
ƒ Interrupt and validation
o Interface control lines
o Arbitration lines
ƒ Not shared
ƒ Directly connected to PCI bus arbiter
o Error reporting lines
• 51 optional signal lines – see Table 3.4
o Interrupt lines
ƒ Not shared
ƒ Directly connected to interrupt controller
o Cache support lines
o 64 bit bus extension lines
ƒ 32 additional multiplexed for address and data
ƒ 2 lines that enable two PCI devices to agree to use 64 bit
o JTAG/boundary scan lines
ƒ For testing procedures

PCI Commands

• Transactions between an initiator (master) and a target

o Master claims bus
o Master determines type of transaction
o Address phase
o One or more data phases

Data Transfers

Every data transfer on the PCI bus is a single transaction consisting of one address
phase and one or more data phases.
Shown below is the timing for the read transaction.

a) Bus master begins transaction by asserting FRAME and placing address

information of AD. FRAME is asserted until the initiator is ready to complete
the last data phase.
b) Target device recognizes its address.
c) The initiator ceases driving the AD bus. The initiator designates which AD lines
are to be used for transfer (1 to 4 bytes). The initiator asserts IRDY to indicate it
is ready for the first data item.
d) Selected target asserts DEVSEL to indicate that it is ready. Target places
requested data on the AD lines and asserts TRDY to indicate that valid data is
on the bus.
e) The initiator reads the data and changes the byte enable lines as needed in
preparation for the next read.
f) The target deasserts TRDY to indicate time is needed to prepare for the second
block of data for transmission.
g) Target places the third data item on the bus. The initiator is not ready to read the
data item and deasserts IRDY.
h) The initiator knows that the third data transfer is the last and deasserts FRAME
to signal the target that this is the last data transfer. The initiator asserts IRDY
to signal it is ready to complete the third transfer.
i) The initiator deasserts IRDY, returning the bus to the idle state. The Target
deasserts TRDY and DEVSEL.
Arbitration

• Centralized
• Synchronous

Shown below is an example where devices A and B are arbitrating for the bus.

a) A asserts REQ-A.
b) B asserts REQ-B.
c) The arbiter asserts GNT-A to grant A bus access.
d) Master A finds IRDY and TRDY deasserted, indicating that the bus is idle.
Master A asserts FRAME and places the address information on the bus. It
continues to assert REQ-A, because it has a second transaction to perform.
e) The arbiter samples all REQ lines and grants the bus to B. The arbiter asserts
GNT-B and deasserts GNT-A. B waits until the bus is idle before it can use it.
f) A deasserts FRAME to indicate that the last data transfer is in progress. A puts
data on the bus and signals the target with IRDY. The target then reads the data.
g) B finds IRDY and FRAME deasserted and takes control of the bus by asserting
FRAME. B deasserts REQ-B, because it will only perform one transfer.

Notice that arbitration can take place at the same time that the current bus master is
performing a data transfer. Therefore, no bus cycles are lost in performing
arbitration. This is referred to as hidden arbitration.