ANNEXURE-V

SPECIAL MANPOWER DEVELOPMENT PROGRAMME FOR VLSI DESIGN &

RELATED SOFTWARE (SMDP) – ONGOING PROJECT OF DIT.

During the IX Plan, Department of Information Technology aimed to increase India's share of
global VLSI design market from about 0.5% to about 5.0%. Considering the availability of
quality human resource for achieving this target as the key catalyst, DIT started in the year
1998 a “Special Manpower Development Programme in the area of VLSI Design and related
Software” involving 19 institutions (7 Resource Centres (RCs) and 12 Participating
Institutions (PIs)) with an outlay of Rs.14.99 crores for a duration of 5 years. The main
activities of the project are: Instruction Enhancement Programme (IEP) for training faculty of
PIs, Training of laboratory technicians, Setting up of VLSI design laboratories, Development
of Learning Materials (LMs) on various topics, Teaching of various courses on VLSI design
and related software at: B.E/B.Tech level (Type-IV manpower); M.E/M.Tech level in the
areas of Electronics, Communications, Computer Science, Instrumentation etc (Type-III
manpower); M.E/M.Tech in VLSI design & Microelectronics (Type-II manpower); Ph.D in
various aspects of VLSI design and related software (Type-I manpower).

The details of LM/IEP topics, names of institutions (RCs & PIs) are given below:

List of Learning Material/IEP Topics being developed under the Special Manpower
Development Programme in the area of VLSI Design and related Software.

A. Theory Courses

Basic Electives
B1 VLSI Fabrication Technology E1 Mixed Signal IC Design Analysis
B2 Semiconductor Devices & Modeling E2 VLSI System & Architecture
B3 Introduction to Digital VLSI E3 Reconfigurable Computing
B4 VLSI Subsystem Design E4 VLSI Testing & Testability
B5 Analog IC Design E5 System Hardware Design
B6 Circuit Simulation & Timing E6 Hardware Software Co-design
Analysis
B7 High Level VLSI Design E7 Low-Power Design Techniques
B8 Combinatorial Algorithms for VLSI E8 VLSI Interconnect Analysis
CAD
E10 Advanced System Architecture

B. Laboratory Course Material

L1 Physical Design Lab. (Combination of Design Lab. and Layout & Extraction Lab)
L2 High Level Design Lab. - VDHL based Design & Simulation
L3 High Level Design Lab. - Veirlog based Design & Simulation
L4 FPGA based Design Lab
L5 Process Technology Lab
L6 VLSI Subsystem Design Lab.
L7 Device Modeling Lab.
L8 Analog Design Lab.

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List of Institutions involved in the Special Manpower Development Programme in the area of
VLSI Design & related software.

Institutions

Twelve institutions called Participating Institutions (PIs) for implementation of the project
and seven institutions who have knowledge in this field to act as Resource Centres (RCs) for
conducting IEPs for training of the faculty of the 12 PIs, and for development of Learning
Materials (LMs) were selected in consultation with MHRD, UGC and AICTE. These are:

Resource Centres (RCs)

1. IIT Madras, Chennai

2. IIT Delhi
3. IIT Kanpur
4. IIT Kharagpur
5. IIT Bombay, Mumbai
6. IISc Bangalore
7. CEERI Pilani

Participating Institutions (PIs)

North

1. Institute of Technology, BHU, Varanasi (Uttar Pradesh)

2. IIT Roorkee (Uttaranchal)
3. Thapar Institute of Engineering. & Technology, Patiala (Punjab)

South

4. KREC, Surathkal (Karnataka)

5. REC Warangal (Andhra Pradesh)
6. PSG College of Technology, Coimbatore (Tamil Nadu)

West

7. MREC, Jaipur (Rajasthan)

8. VREC, Nagpur (Maharashtra)
9. Shri GS Institute of Technology & Science, Indore (M.P.)

East

10. Bengal Engineering College, Howrah (West Bengal)

11. Jadavpur University, Calcutta (West Bengal)
12. REC, Rourkela (Orissa)

The duration of the on-going programme has been extended by one-year upto 31st March
2004.

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Proposed Special Manpower Development Programme for VLSI Design & Related
Software (SMDP) –Phase-II.

DIT has set up a Working Group having members from MHRD, UGC, AICTE, academic
institutions, R&D laboratories and industry associations to workout the second phase of the
Special Manpower Development Programme in the area of VLSI Design & related software.

TCS-IIT Bombay Report: A report prepared by TCS & IIT Bombay “Promoting
Microelectronics Education – The Indian Imperative” estimates the demand as 4000-5000
microelectronics engineers to address the business opportunities. For this the report suggests
to initiate M.Tech (Microelectronics) courses. A model syllabus for the M Tech level course
has been presented in the report. The report has also listed 44 institutions excluding IITs and
IISc where the M.Tech course could be initiated

The Working Group set up by DIT for SMDP Phase II in its first meeting held on 05.06.2003
discussed inter-alia the TCS-IIT Bombay report and concluded that about 1000
engineers/year having M.E./M.Tech qualifications (Type II & III) should be aimed for the
present which could be further increased if required based on the actual situation on the
ground. Accordingly, Working Group has suggested starting the next phase of SMDP
involving the following institutions subject to institutions’ willingness to participate in the
programme and to start the M.Tech programme within stipulated time:

Resource Centres (RCs)

1. IIT Madras *
2. IIT Delhi *
3. IIT Kanpur *
4. IIT Kharagpur *
5. IIT Bombay *
6. IISc Bangalore *
7. CEERI Pilani *

Participating Institutes (PIs)

A IITs

1. IIT Roorkee *
2. IIT Guwahati

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 B. Regional Engineering Colleges/NITs at the following locations

1. Warangal *
2. Surathkal *
3. Tiruchirapalli
4. Rourkela, Orissa *
5. Motilal Nehru, REC, Allahabad
6. Dr.B.R.Ambedkar, REC, Jalandhar
7. Surat
8. Nagpur *
9. Hamirpur
10. Silchar
11. Kurukshetra
12. Calicut
13. Jaipur *
14. Durgapur
15. Bhopal
16. Srinagar
17. Jamshedpur

Other Phase I – PIs

1. Bengal Engineering College (Deemed University) Sibpur, West Bengal *

2. Jadavpur University, Kolkata *
3. GS Inst.of Tech. and Science, Indore *
4. Thapar Institute of Technology, Patiala *
5. IT, BHU *
6. PSG College of Engineering, Coimbatore *

* Covered under DIT’s on-going SMDP programme

DIT has also approved providing grant-in-aid to CDAC Mohali, for starting M.Tech in VLSI
Design, subject to AICTE approval & university affiliation.

The Annual plan allocation of DIT for the FY 2003-04 to service the ongoing project as well
as to initiate the next phase of the project is Rs. 3.5 crorers. Expenditure incurred during the
current financial year is Rs.8.69 lakhs.

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