Key idea

sequential circuit is d e f
• combination circuit plus memory (state) u
a combinational
• flip flops are its memory (one per bit) b v flip
circuit
c w flops
• output is function of inputs + current state
describe it using
Counters and registers
x y z
• truth table, boolean functions or logic diagram
– for combinational part (truth table, boolean function, logic diagram)
Lecture 6 — § 2.4-2.6 – inputs are external inputs plus flop-flop outputs u = g(a,b,c,d,e,f)
Computer Science 218 – outputs are external outputs plus flip-flop inputs v = h(a,b,c,d,e,f)
– one boolean function for each output in terms of all inputs w= i(a,b,c,d,e,f)
x = j(a,b,c,d,e,f)
Mike Feeley
• finite state machine y = k(a,b,c,d,e,f)
– for sequential part z = l(a,b,c,d,e,f)
– finite state machine
– lists all possible states (memory settings)
– describes how current input and state determine external output and next state

Designing a sequential circuit Designing a sequential circuit (II)

x=0 Q(t) in Q(t+1) flip-flop inputs
example: a two-bit counter 3. get boolean functions A B x A B JA KA JB KB
00 • for 0 0 0 0 0 0 x 0 x
1. draw a state diagram x=0
x=1 x=1 – flip-flop inputs and external outputs 0 0 1 0 1 0 x 1 x
0 1 0 0 1 0 x x 0
2. draw excitation table 01 11 x=0 • in terms of 0 1 1 1 0 1 x x 1
• left hand columns x=1 x=1 – flip-flop outputs and external inputs 1 0 0 1 0 x 0 0 x
– all combinations of current state + input => next state 10 • using k-maps 1 0 1 1 1 x 0 1 x
• right hand columns x=0 1 1 0 1 1 x 0 x 0
Bx JA Bx JB 1 1 1 0 0 x 1 x 1
– one flip flop for each state variable (e.g., A,B)
– column for each flip-flop input, from excitation table A 00 01 11 10 A 00 01 11 10
0 0 0 1 0 0 0 1 x x
Q(t) in Q(t+1) flip-flop inputs 1 x x x x 1 0 1 x x
A B x A B JA KA JB KB Q(t) Q(t+1) J K x
JA = Bx JB = x J Q A
0 0 0 0 0 0 x 0 x 0 0 0 x KB
Bx KA Bx >C
0 0 1 0 1 0 x 1 x 0 1 1 x
1 0 x 1 A 00 01 11 10 A 00 01 11 10 K
0 1 0 0 1 0 x x 0
1 1 x 0 0 x x x x 0 x x 1 0
0 1 1 1 0 1 x x 1
1 0 0 1 0 1 x x 1 0 J Q B
1 0 0 1 0 x 0 0 x
KA = Bx KB = x clock >C
1 0 1 1 1 x 0 1 x K
1 1 0 1 1 x 0 x 0 4. draw logic diagram
1 1 1 0 0 x 1 x 1 3 4
Now you try ... Basic register
implement a 2-bit grey-code counter stores a multi-bit data word I0 D
>C
Q A0

• an encoding where successive numbers differ by exactly one bit • essentially a group of flip flops
• here is a three-bit grey code sequence starting at zero 000 • one flip flop for each bit
001 I1 D Q A1
draw the 011 on each clock rising/falling edge >C
• state diagram 010 • value of I is captured and available as A
110
• excitation table 111 • if clear → 0, flip flops reset A to 0
101 I2 D Q A2
• boolean functions limitations? >C
100
• circuit diagram • only holds A for one clock cycle
here is the excitation table for a JK flop flop Q
I3 D A3
Q(t) Q(t+1) J K clock >C
0 0 0 x
0 1 1 x
1 0 x 1 clear
1 1 x 0

5 6

Parallel-load register Parallel-load register (II)

load load
D flip flop makes it tricky Q
D Q A0
D A0
• unlike JK, it doesn’t hold value >C
load S Y D Q A0
>C I0 2x1
I0 I0 >C
mux
• its gone on next clock I0 I1

add load input Q D Q A1 S Y D Q A1

D A1 2x1
• if 0, A doesn’t change I1 >C I1 >C I0
mux
>C
I1 I1
– feed A back into FF input
• if 1, A=I S Y D Q A2
D Q A2 2x1
– fin I into FF input D Q A2 I0 >C
>C mux
>C I2 I2 I1
I2
can you make it simpler?
S Y D Q A3
2x1
Q I0 >C
D Q A3
D A3 mux
>C
I3 I1
I3 >C I3
clock clock
clock
clear clear

7 8
Shift register Bidirectional shift register
register that can shift value to left or right two-bit mode input
M0 S0
1 0 0 1 ←1 0→ 0 0 1 1
• 00 – no change M1 S1
I0 4x1 Y D Q A0
0 0 0 1 1 • 01 –!shift left serial in I1 mux
1 0 0 1 1 I2
>C
• 10 –!shift right I0 I3

uses • 11 –!parallel load (A=I) S0

S1
• serialize data for “long-distance” transmission I0 4x1 Y D Q A1
I1 mux >C
– n-bit data transmitted one bit at a time in n cycles shift left I2
I1 I3
1 0 0 1 ←1
• multiply or divide an integer by two
S0
simple unidirectional shift register shift right
S1
I0 4x1 Y D Q A2
I1 mux >C
A3 A2 A1 A0 0→ 0 0 1 1 serial in I2
I2 I3
serial in D Q D Q D Q D Q serial out clock
>C >C >C >C

clock

what’s missing? 9 10

Binary n-bit counter ... One-bit counter

d flip flop
we could draw state machine any value of n one-bit-couter(L) (A,U) excitation table
• L = conjunction of all lower-order bits Q(t) Q(t+1) D
000 0 0 0
– L=1 iff all lower-order bits are one 0 1 1
001 111
• U = conjunction of this bit and L 1 0 0
– input to L of next bit 1 1 1
010 110
state diagram, excitation table, function and logic
011 101
cur next FF
100 L=0 / U=0 D Q A
state in state out in L
>C
A L A U Di
• but this requires new design for each value of n 0 0 0 0 0
0 0 1 1 0 1
• is there a generic design that makes changing n easy/incremental? L=1 / U=0 L=1 / U=1 1 0 1 0 1
1 1 0 1 0
design a state machine for each bit 1
U
Di
• then compose them L
0 1
L=0 / U=0 A Di = A L
• what is the rule for switching a bit? switch when lower-order bits are all 1 0 0 1 L 1-bit A
1 1 0 U = AL > C count U
– based on lower-order bits draw the state diagram for one bit ...
11 12
Now a 3-bit counter N-bit counter with parallel load
using we get
A0 A1 A2
mode input
L 1-bit A
1 L 1-bit A L 1-bit A L 1-bit A
• 00 – no change
> C count U
> C count U > C count U > C count U • 01 – increment
clock
• 10 – load
• 11 –!clear
add mux to one-bit counter
I
S0 A
D Q A
L S1 U
>C M0 S0
M1 S1 I 1-bit
I0 4x1 Y D Q A L count
L I1 mux >C
I2 >C
0 I3

L 1-bit A
13 > C count U U 14

3-bit counter with parallel load

I0 I1 I2
A0 A1 A2
S0 A S0 A S0 A
S1 U S1 U S1 U
I 1-bit I 1-bit I 1-bit
L count L count L count
>C >C >C

clock

15