Chapter 1

Introductory Chapter

 Introduction:
In most computing tasks, the number of output bits is relatively small
compared to the number of input bits. For example, in a decision problem, the output
is only one bit (yes or no) and the input can be as large as desired. However,
computational tasks in digital signal processing, communication, computer graphics,
and cryptography require that all of the information encoded in the input be preserved
in the output. Some of those tasks are important enough to justify adding new
microprocessor instructions to the HP PA-RISC (MAX and MAX-2), Sun SPARC
(VIS), PowerPC (AltiVec), IA-32 and IA-64 (MMX) instruction sets In particular,
new bit-permutation instructions were shown to vastly improve performance of
several standard algorithms, including matrix transposition and DES, as well as two
recent cryptographic algorithms Twofish and Serpent. Bit permutations are a special
case of reversible functions, that is, functions that permute the set of possible input
values. For example, the butterfly operation (x,y) → (x+y,x−y) is reversible but is not
a bit permutation. It is a key element of Fast Fourier Transform algorithms and has
been used in application-specific Xtensa processors from Tensilica. One might expect
to get further speed-ups by adding instructions to allow computation of an arbitrary
reversible function. The problem of chaining such instructions together provides one
motivation for studying reversible computation and reversible logic circuits, that is,
logic circuits composed of gates
computing reversible functions.

Reversible circuits are also interesting because the loss of information

associated with irreversibility implies energy loss. Younis and Knight showed that
some reversible circuits can be made asymptotically energy-lossless as their delay is
allowed to grow arbitrarily large. [Excerpt from "Asymptoticay Zero Energy Split-
Level Charge Recovery Logic" : Younis & Knight :
Power dissipation in conventional CMOS primarily occurs during device
switching. One component of this dissipation is due to charging and discharging the
gate capacitances through conducting, but slightly resistive, devices. We note here

1
that it is not the charging or the discharging of the gate that is necessarily dissipative,
but rather that a small time is allocated to perform these operations. In conventional
CMOS, the time constant associated with charging the gate through a similar
transistor is RC, where R is the ON resistance of the device and C its capacitance.
However, the cycle time can be, and usually is, much longer than RC. An obvious
conclusion is that energy consumption can be reduced by spreading the transitions
over the whole cycle rather than "squeezing" it all inside one RC.
To successfully spread the transition over periods longer than RC, we insist
that two conditions apply throughout the operation of our circuit. Firstly, we forbid
any device in our circuit from turning ON while a potential difference exists across it.
Secondly, once the device is switched ON, the energy transfer through the device
occurs in a controlled and gradual manner to prevent a potential from developing
across it. These conditions place some interesting restrictions on the way we usually
perform computations. To perform a non-dissipative transition of the output, we must
know the state of the output prior to and during this output transition. Stated more
clearly, to non-dissipatively reset the state of the output we must at all times have a
copy of it. The only way out of this circle is to use reversible logic. It is this
observation that is the core of our low energy charge recovery logic.

Currently, energy losses due to irreversibility are dwarfed by the overall power
dissipation, but this may change if power dissipation improves. In particular,
reversibility is important for nanotechnologies where switching devices with gain are
difficult to build.

Finally, reversible circuits can be viewed as a special case of quantum circuits

because quantum evolution must be reversible. Classical (non-quantum) reversible
gates are subject to the same “circuit rules,” whether they operate on classical bits or
quantum states. In fact, popular universal gate libraries for quantum computation
often contain as subsets universal gate libraries for classical reversible computation.
While the speed-ups which make quantum computing attractive are not available
without purely quantum gates, logic synthesis for classical reversible circuits is a first
step toward synthesis of quantum circuits. Moreover, algorithms for quantum
communications and cryptography often do not have classical counterparts because

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they act on quantum states, even if their action in a given computational basis
corresponds to classical reversible functions on bit-strings.

Quantum circuits require complete reversibility. Quantum circuits and

algorithms offer additional benefits in terms of asymptotic runtime.
While purely quantum gates are necessary to achieve quantum
speed-up, variants of conventional reversible gates are also
commonly used in quantum algorithms. For example, the textbook
implementation of Grover's quantum search algorithm uses many
NCT (NOT, CNOT, and TOFFOLI) gates. Hence, efficient synthesis
with such gates is an important step toward quantum computation.
Toffoli showed that the NCT gate library is universal for the
synthesis of reversible boolean circuits. This has been recently
extended to show that all even permutations can be synthesized
with no temporary storage lines, and that odd permutations require
exactly one extra line. Optimal circuits for all three-bit reversible
functions can be found in several minutes by dynamic
programming. This algorithm also synthesizes optimal fourbit
circuits reasonably quickly, but does not scale much further. More
scalable constructive synthesis algorithms tend to produce
suboptimal circuits even on three bits, which suggests iterative
optimization based on local search.

 How All It Came?

Question :What will be the difficulties when we will try to build
classical computers (Turing machines) on the atomic scale?
Answer : One of the toughest problems to scale down
computers is the dissipated heat that is difficult to remove.

Physical limitations placed on computation by heat dissipation

were studied for many years [3]. The usual digital computer program
frequently performs operations that seem to throw away information about the
computer's history, leaving the machine in a state whose immediate predecessor is
ambiguous. Such operations include erasure or overwriting of data, and entry into a

3
portion of the program addressed by several different transfer instructions. In other
words, the typical computer is logically irreversible - its transition function (the
partial function that maps each whole-machine state onto its successor, if the state has
a successor) lacks a single-valued inverse.
Landauer [ 3 ] has posed the question of whether logical irreversibility is an
unavoidable feature of useful computers, arguing that it is, and has demonstrated the
physical and philosophical importance of this question by showing that whenever a
physical computer throws away information about its previous state it must generate a
corresponding amount of entropy. Therefore, a computer must dissipate at least kTln2
of energy (about 3 X 10-21 joule at room temperature) for each bit of information it
erases or otherwise throws away.
In his classic 1961 paper [3, Appendix A], Rolf Landauer
attempted to apply thermodynamic reasoning to digital computers.
Paralleling the fruitful distinction in statistical physics between
macroscopic and microscopic degrees of freedom, he noted that
some of a computer’s degrees of freedom are used to encode the
logical state of the computation, and these ”information bearing”
degrees of freedom (IBDF) are by design sufficiently robust that,
within limits, the computer’s logical (i.e. digital) state evolves
deterministically as a function of its initial value, regardless of small
fluctuations or variations in the environment or in the computer’s
other non-information-bearing degrees of freedom (NIBDF). While a
computer as a whole (including its power supply and other parts of
its environment), may be viewed as a closed system obeying
reversible laws of motion (Hamiltonian or, more properly for a
quantum system, unitary dynamics), Landauer noted that the logical
state often evolves irreversibly, with two or more distinct logical
states having a single logical successor.
Therefore, because Hamiltonian/unitary dynamics conserves
(fine-grained) entropy, the entropy decrease of the IBDF during a
logically irreversible operation must be compensated by an equal or
greater entropy increase in the NIBDF and environment.

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 This is Landauer’s principle. Typically the entropy increase
takes the form of energy imported into the computer, converted to
heat, and dissipated into the environment. So, what is the solution?
At this juncture Bennett[4] showed : An irreversible computer can always be
made reversible by having it save all the information it would otherwise throw away.
For example, the machine might be given an extra tape (initially blank) on which it
could record each operation as it was being performed, in sufficient detail that the
preceding state would be uniquely determined by the present state and the last record
on the tape. However, as Landauer pointed out, this would merely postpone the
problem of throwing away unwanted information, since the tape would have to be
erased before it could be reused. It is therefore reasonable to demand of a useful
reversible computer that, if it halts, it should have erased all its intermediate results,
leaving behind only the desired output and the originally furnished input. (The
machine must be allowed to save its input-otherwise it could not be reversible and still
carry out computations in which the input was not uniquely determined by the
output.) General-purpose reversible computers (Turing machines) satisfying these
requirements indeed exist, and they need not be much more complicated than the
irreversible computers on which they are patterned. Computations on a reversible
computer take about twice as many steps as on an ordinary one and may require a
large amount of temporary storage.
At this time Tomasso Toffoli (1980) showed that there exists a
reversible gate which could play a role of a universal gate for
reversible circuits. These two simultaneously have lead to the
exploration in the field of Reversible Logic Gates and Circuits.
In recent years, reversible computing system design is
attracting a lot of attention. Reversible computing is based on two
concepts: logic reversibility and physical reversibility. A
computational operation is said to be logically reversible if the
logical state of the computational device before the operation of the
device can be determined by its state after the operation i.e., the
input of the system can be retrieved from the output obtained from
it. Irreversible erasure of a bit in a system leads to generation of
energy in the form of heat. An operation is said to be physically

5
reversible if it converts no energy to heat and produces no entropy.
Landauer has shown that for every bit of information lost in logic
computations that are not reversible, kTlog2 joules of heat energy is
generated, where k is Boltzmann’s constant and T the absolute
temperature at which computation is performed. The amount of
energy dissipation in a system increases in direct proportion to the
number of bits that are erased during computation. Bennett showed
that kTln2 energy dissipation would not occur, if a computation were
carried out in a reversible way. Reversible computation in a system
can be performed if the system is composed of reversible gates.
Two conditions must be satisfied for reversible computation

The first Condition :

for any deterministic device to be reversible its input and output
must be uniquely retrievable from each other.
- this is called logical reversibility.

The second Condition :

the device can actually run backwards, i.e., in another term it can
be said that each operation converts no energy to heat and
produces no entropy.
- this is called physical reversibility.
- Second Law of Thermodynamics guarantees that no heat is
dissipated.

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 Chapter 2
Reversible Gates and Circuits: Details Analysis

 Background :
In conventional (irreversible) circuit synthesis, one typically starts with a
universal gate library and some specification of a Boolean function. The goal is to
find a logic circuit that implements the Boolean function and minimizes a given cost
metric, e.g., the number of gates or the circuit depth. At a high level, reversible circuit
synthesis is just a special case in which no fanout is allowed and all gates must be
reversible.

 Definitions:
Definition 1: A gate is reversible if the (Boolean) function it computes is bijective.

If arbitrary signals are allowed on the inputs, a necessary condition for

reversibility is that the gate have the same number of input and output wires. If it has
k input and output wires, it is called a k×k gate, or a gate on k wires. We will think of
the mth input wire and the mth output wire as really being the same wire. Many gates
satisfying these conditions have been examined in the literature. We will consider a
specific set defined by Toffoli.

Definition 2 A k-CNOT is a (k+1)×(k+1) gate. It leaves the first k inputs

unchanged, and inverts the last iff all others are 1. The unchanged lines are
referred to as control lines.

Clearly the k-CNOT gates are all reversible. The first three of these have
special names. The 0- CNOT is just an inverter or NOT gate, and is denoted by N. It
performs the operation (x)→(x XOR 1). The 1-CNOT, which performs the operation
(y,x)→(y,x XOR y) is referred to as a Controlled-NOT, or CNOT (C). The 2-CNOT
is normally called a TOFFOLI (T) gate, and performs the operation (z,y,x)→(z,y,x
XOR yz). We will also be using another reversible gate, called the SWAP (S) gate. It
is a 2×2 gate which exchanges the inputs; that is, (x,y)→(y,x). One reason for
choosing these particular gates is that they appear often in the quantum computing
context, where no physical “wires” exist, and swapping two values requires non-

7
trivial effort. We will be working with circuits from a given, limited-gate library.
Usually, this will be the CNTS gate library, consisting of the CNOT, NOT, and
TOFFOLI, and SWAP gates.

Definition 3 A well-formed reversible logic circuit is an acyclic combinational logic

circuit in which all gates are reversible, and are interconnected without fanout.

As with reversible gates, a reversible circuit has the same number of input and
output wires; again we will call a reversible circuit with n inputs an n × n circuit or
a circuit on n wires. We draw reversible circuits as arrays of horizontal lines
representing wires. Gates are represented by vertically-oriented symbols. For
example, in the following Figure, we see a reversible circuit drawn in the notation
introduced by Feynman. The symbols inverters and the • symbols represent
controls. A vertical line connecting a control to an inverter means that the inverter is
only applied if the wire on which the control is set carries a 1 signal. Thus, the gates
used are, from left to right, TOFFOLI, NOT, TOFFOLI, and NOT.

Figure 1

How to represent a reversible circuit truth table?

Since we will be dealing only with bijective functions, i.e., permutations, we
represent them using the cycle notation where a permutation is represented by disjoint
cycles of variables. For example, the truth table in Figure 2 is represented by (2,3)

8
(6,7) because the corresponding function swaps 010 (2) and 011 (3), and 110 (6) and
111 (7). The set of all permutations of n indices is denoted Sn, so the set of bijective
functions with n binary inputs is S2n . We will call (2,3)(6,7) CNT-constructible since
it can be computed by a circuit with gates from the CNT gate library.
Let us take another example. Here is the figure of a Toffoli's
Gate and its corresponding truth table.

Figure 2: Toffoli's Gate

a, b and c are the three inputs to the gate and the

corresponding output lines are X, Y and Z respectively. The
corresponding functions computed are as following :
X=a
Y=b
Z = c XOR ab
Truth Table for Toffoli's Gate

a b c x y z

0 0 0 0 0 0

0 0 1 0 0 1

0 1 0 0 1 0

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 1

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 1 1 1 1 1 0

From the truth table of Toffoli’s gate it is clear that it is a

reversible gate. There exists a one-to-one mapping from the input
vectors to the output vectors. More over, the output is balanced.
Here the truth table can be represented by (6,7) only. Another
example as follows:
Consider the following truth table of any reversible circuit.

Truth Table of an arbitrary Reversible Circuit

From the previous discussion, we can represent the truth table

as the following disjoint cycle of variables : (2,4),(3,6,5).

How to encode a reversible circuit?

In electronic design automation, it is common to represent
logic circuits as graphs or hypergraphs. However, the regularity and
ordering intrinsic to reversible circuits facilitate a more compact
array-based representation (encoding) that is also more convenient.
In conventional circuit representations, all connections between
individual gates are enumerated, and each gate stores indices of its

10
incident connections. However, in a reversible circuit, one can
distinguish a small number of wires going all the way through the
circuit. In our encoding of a reversible circuit, those indices are
maintained at individual gates, and the gates are stored in an array
in an arbitrarily chosen topological order. Overlaid on this array is a
redundant adjacency data structure (a graph) that allows one to
look up the neighbors of a given gate. This representation is faithful;
it is also convenient because each range in the array represents a
valid sub-circuit. However, not every valid sub-circuit is represented
by a range. In particular, any set of gates in a circuit that form an
anti-chain (with respect to the partial ordering) will be ordered,
obscuring the fact that any subset is a valid subcircuit.

Let us encode the following reversible circuit as follows :

Figure 3

To encode the circuit in the above figure, we number wires top-down from 0
to 3.
Then the gates can be written as following :
T(2,3;1)T(0,1;3)C(3;2)C(1;2)C(3;0)T(0,2;1)N(2)

Definition 4. Let L be a (reversible) gate library. An L-circuit is a circuit composed

only of gates from L. A permutation π 2 S2n is L-constructible if it can be
computed by an n×n L-circuit.

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 Following figure 4a indicates that the circuit in Figure 1 is equivalent to one
consisting of a single C gate. Pairs of circuits computing the same function are very
useful, since we can substitute one for the other.

Figure 4

On the right, we see similarly that three C gates can be used to replace the S
gate appearing in the middle circuit of Figure 4b. If allowed by the physical
implementation, the S gate may itself be replaced with a wire swap. This, however, is
not possible in some forms of quantum computation. Figure 4 therefore shows us that
the C and S gates in the CNTS gate library can be removed without losing
computational power. We will still use the CNTS gate library in synthesis to reduce
gate counts and potentially speed up synthesis. This is motivated by Figure 4, which
shows how to replace four gates with one C gate, and thus up to 12 gates with one S
gate.

Temporary Storage:

12
 Figure 5

Figure 5 illustrates the meaning of “temporary storage”. The top n−k lines
transfer n−k signals, collectively designated Y, to the corresponding wires on the
other side of the circuit. The signals Y are arbitrary, in the sense that the circuit K
must assume nothing about them to make its computation. Therefore, the output on
the bottom k wires must be only a function of their input values X and not of the
“ancilla” bits Y, hence the bottom output is denoted f (X). While the signals Y must
leave the circuit holding the same values they entered it with, their values may be
changed during the computation as long as they are restored by the end. These wires
usually serve as an essential workspace for computing f (X). An example of this can
be found in Figure 4a: the C gate on the right needs two wires, but if we simulate it
with two N gates and two T gates, we need a third wire. The signal applied to the top
wire emerges unaltered.

Definition 5. Let L be a reversible gate library. Then L is universal if for all k and
all permutations π Є S2K , there exists some l such that some L-constructible
circuit computes π using l wires of temporary storage.

The concept of universality differs in the reversible and irreversible cases in two
important ways. First, we do not allow ourselves access to constant signals during the
computation, and second, we synthesize whole permutations rather than just functions with
one output bit.

Representing Circuits by Graphs: One can model gates in a reversible

circuit by vertices, and wires by directed edges (more than one edge may
connect two vertices). If the gates are reversible, each vertex must have
as many edges entering as leaving. Since no feedback is allowed, such
graphs must be acyclic. The graph of a reversible circuit can be viewed as
a partial ordering of gates: for gates G; H in C, we say G >C H (or
equivalently H <C G) if there exists a non-trivial path from H to G in the
graph representing C. When C is clear from the context, we write G > H.

 Discussion:

13
Some of the major problems with reversible logic synthesis are :
i) Fan-outs are not allowed
ii) Feedback from gate outputs to inputs are not permitted

A logic synthesis technique using reversible gate should have the

following features:
i) Use minimum number of garbage outputs
ii) Use minimum input constants
iii) Keep the length of cascading gates minimum
iv) Use minimum number of gates

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Some special types of Reversible Gates:

K-CNOT Gate:
K=0:
The 0-CNOT is just an inverter or NOT gate, and is denoted by N.
It performs the operation (x) → (x XOR 1).

K=1:
The 1-CNOT, performs the operation (y,x) →(y,x XOR y).
It is referred as a controlled-NOT or CNOT or C.

K=2:
The 2-CNOT is normally called a TOFFOLI (T) gate.
It performs the operation (z,y,x) → (z,y,x XOR yz).

SWAP Gate :
We will also be using another reversible gate, called the SWAP (S)
gate.
It is a 2×2 gate which exchanges the inputs; that is, (x,y) → (y,x).

Toffoli's Gate:
In Toffoli Gate, all the inputs from 1 to (n-1) are passed as
outputs. The nth output is controlled by 1 to (n-1) inputs. When all
the inputs from 1 to (n-1) are 1s, the nth input is inverted and
passed as output else original signal is passed. A 3-input, 3-output
Toffoli gate is shown in Fig 6.

Figure 6: 3x3 Toffoli's Gate

The inputs ‘a’ and ‘b’ are passed as first and second output
respectively. The third output is controlled by ‘a’ and ‘b’ to invert
‘c’. The truth table has been shown before.

15
Fredkin's Gate:
The Fredkin gate is shown in the Fig 7. Here the input ‘a’ is
passed as first output. Inputs b and c are swapped to get the second
and third output which is controlled by ‘a’. Thus two inputs can be
swapped by controlling the swap using another input in Fredkin
Gate.

Figure 7: 3x3 Fredkin's Gate

The truth table is as follows :

a b c x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Truth Table for a 3x3 Fredkin's Gate

The functions computed by the outputs of Fredkin’s Gate can

be interpreted as follows :
X=a
Y = if a then c else b
Z = if a then b else c
Every boolean function can be interpreted by 3x3 Fredkin’s
gate (shown in Figure 8).

16
Figure 8

17
 Chapter 3
A Family of Logical Fault Models for Reversible Circuits

 Introduction:
The reversibility of computation has long been studied as a means to reduce or
even eliminate the power consumed by computation. Of particular interest is a type of
reversible computing known as quantum computing, which fundamentally changes
the nature of computation by basing it on quantum mechanics rather than classical
physics.

Many physical implementations of quantum circuits have been suggested,

although a practical quantum computer has yet to be built. Quantum state
representations include photon polarization and electron spin. Such states are fragile
and error-prone due to their nanoscale dimensions, extremely low energy levels, and
tendency to interact with the environment (decoherence). Hence, it is expected that
efficient testing and fault-tolerant design methods will be essential for the successful
implementation of quantum circuits. Because of the complexity of their normal and
faulty behavior modes, the testing problems posed by general quantum circuits are
very challenging.

Since all its gates are reversible, each group of gates in a reversible circuit is
also reversible. Hence, any arbitrary state can be justified on each gate. For example,
if the values (1111) must be applied to the rightmost 3-CNOT gate of Figure 9 for test
purposes, there is a unique input vector that is easily obtained by backward simulation
(1101 in this case). Furthermore, propagation of a fault effect is trivial: if a logic 1
value is replaced by a logic 0 (or vice versa) due to a fault, this will result in a
different value at the output of the circuit.

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 Figure 9

 Trapped-Ion Technology:

Nielsen and Chuang cite four abilities of a technology as necessary for

quantum computation. The technology must:
(1) robustly represent quantum information;
(2) perform a universal set of unitary transformations;
(3) prepare accurate initial states; and
(4) measure the output results.
In the following, we will briefly review how these four issues are addressed in the
trapped-ion technology.

Qubit representation: The internal state of an ion serves as the qubit representation;
the ground state (|g>) represents |0>, while the excited state (|e0>) represents |1>. In
trapped-ion technology, ions are confined in an ion trap, i.e. between electrodes, some
of which are grounded (have a static potential) while others are driven by a fast

19
oscillating voltage. The Los Alamos group used the Ca+ ions with 42S1/2 as the ground
state and 32D5/2 as the excited state.

.
Unitary transformations: These operations rotate state vectors without changing
their length, which implies reversibility. In the trapped-ion technology, ions interact
with laser pulses of certain duration and frequency. Qubits interact via a shared
phonon (quantum of vibrational energy) state. CNOT functionality has been
experimentally demonstrated for the trapped-ion technology (as well as for NMR
technology).

Initialization: Trapped ions are brought into their motional ground state |00 . . . 0>
using Doppler and sideband cooling.

Measurement: The state of a single ion is determined by exciting an ion via a laser
pulse and measuring the resulting fluorescence.

Figure 10 illustrates the gate implementation in trapped-ion technology required for

the circuit in Figure 9. The circuit has four wires a, b, c and d, so four ions (qubits)
are used. Since the input vector is (1010), the qubits a and c are set to the state |1_ and
the qubits b and d are set to |0> in the beginning.

The leftmost (2-CNOT) gate is implemented by a laser pulse (or a sequence

thereof) applied to qubits a, b and c. Their interaction results in the state of qubit b
being changed from |0> to |1>. This is shown in the upper right of Figure 10.
Similarly, the second (1-CNOT) gate corresponds to a pulse that changes the state of
qubit c from |1> to |0>. The third gate does not result in a state change on the target
qubit d due to a logic-0 value at one of its control inputs (c); consequently, the third
pulse does not change the state of qubit d.

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 Figure 10

 Fault Models
Next we introduce several fault models that are mainly motivated by the ion-
trap quantum computing technologies discussed in the preceding section. The basic
assumptions are that qubits are represented by the ion state, gates correspond to
external pulses which control the interactions of the qubits, and the gate operations are
error prone. The fault models proposed are the single missing gate fault (SMGF), the
repeated-gate fault (RGF), the multiple missing gate fault (MMGF) and the partial
missing-gate fault (PMGF) models.

Single Missing-Gate Fault Model

A single missing-gate fault (SMGF) corresponds to the missing-gate fault. It is
defined as a complete disappearance of one CNOT gate from the circuit. The physical
justification for a SMGF is that the pulse(s) implementing the gate operation is (are)
short, missing, misaligned or mistuned. Figure 11 shows the circuit from Figure 9
with an SMGF: the first (2-CNOT) gate is missing. The resulting changes in logical

21
values are shown in the format “faultfree value/faulty value”. It can be seen that the
fault effect is observable on wires b and c. The right part of Figure 11 suggests how
the pulse corresponding to the first gate is too weak to change the value on qubit b
from |0_ to |1_. The detection condition for an MGF is that a logic 1 value be applied to
all the control inputs of the gate in question; the values on the target input as well as the
values on the wires not connected to the gate are arbitrary. The number of possible SMGFs is
equal to the number of gates in the circuit. The followings are the characterization of
SMGFs:.

Figure 11

Theorem 1 (Properties of SMGFs) Consider a reversible circuit consisting of N

CNOT gates.
1. There is always a complete SMGF test set of _N/2_ or fewer vectors.
2. There are circuits for which the minimal complete SMGF test set has
exactly _N/2_ vectors.
3. By adding one extra wire and several 1-CNOT gates, every circuit can be
transformed such that the resulting circuit retains its original functionality but has a
complete SMGF test set consisting of one test vector. The transformation can be done
for any test vector, but there is a unique test vector leading to minimal overhead
(number of required extra 1-CNOT gates). SMGFs corresponding to the added gates
are also covered by that test vector

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Repeated-Gate Fault Model

A repeated-gate fault (RGF) is an unwanted replacement of a CNOT gate by

several instances of the same gate. The physical justification for an RGF is the
occurrence of long
or duplicated pulses. Figure 12 (left) shows the circuit from Figure 9 with a duplicated
first gate. It can be seen that the fault effect is identical to that of the SMGF (Figure
11). Figure 12 (right) illustrates the double transition on qubit b first from |0> to 1|>, and
then back to |0> due to a long or duplicated pulse. As a generalization, the following theorem
holds:

Figure 12

Theorem 2 (Properties of RGFs) Consider an RGF that replaces a gate by k instances

of the same gate.
1. If k is even, the effect of the RGF is identical to the effect of the SMGF with
respect to the same gate.
2. If k is odd, the fault is redundant, i.e., it does not change the function of the
circuit.

Multiple Missing-Gate Fault Model

This model assumes that gate operations are disturbed for several consecutive
cycles, so that several consecutive gates are missing from a circuit. An example
involving two missing gates is shown in Figure 13 (left). Note that the MMGF
definition does not match our usual understanding of a multiple fault, which implies
that several distinct single faults are present in the same time. We also restrict
multiple faults to one or more consecutive gates. Hence for the circuit from Figure 13
(left), removing the middle and the rightmost gate yields a valid MMGF, but
removing the leftmost and the rightmost gates does not. This fault model is justified

23
by the assumption that the laser implementing gate operations is more likely to be
disturbed for a period of time exceeding one gate operations than to be disturbed for a
short time, then perform error-free, and then be disturbed again. Clearly, SMGFs are a
subset of the MMGFs. In an N-gate circuit, the number of possible MMGFs is N(N +
1)/2, a quadratic function of N, whereas the corresponding number of multiple
SMGFs is exponential in N.

Figure 13
It has been proven for stuck-at faults in reversible circuits that a complete
single fault test set covers all multiple faults. This is not true for SMGFs and MMGFs,
however, despite the restriction that the missing gates must be consecutive. This is
demonstrated by the two-gate circuit fragment shown in Figure 13 (right). The SMGF
corresponding to the left (3-CNOT) gate requires the test vector (111X) for detection,
where X stands for “don’t care”. The SMGF for the second (2-CNOT) gate requires
(X11X), so the optimal SMGF test set consists of one test vector, e.g., (1110).
However, this vector does not detect the MMGF defined by removal of both gates,
although it is a complete SMGF test set. The MMGF is not redundant, as vector
(011X) detects it. Furthermore, as every SMGF is also an MMGF, the vector (111X)
also must be included in any complete MMGF test set. Hence, the optimal size of a
complete MMGF test set is two. We have seen above that the size of the optimal test
set for SMGFs is one. Hence, a complete SMGF test set does not cover all MMGFs.

Partial Missing-Gate Fault Model

A partial missing-gate fault is a result of partially misaligned or mistuned gate
pulses. It turns a k-CNOT gate into a k'-CNOT gate, with k' < k. We call k − k' the
order of a PMGF. Figure 14 shows a first-order PMGF affecting the third control

24
input of the rightmost gate, and the weak pulse that fails to make c interact with a, b
and d. An SMGF can be seen as a 0-order PMGF.

Figure 14

Theorem 3 (Properties of PMGFs)

1. A k-CNOT requires k test vectors to detect all firstorder PMGFs and k + 1
vectors if the SMGFs must also be detected.
2. Anm-order PMGF dominatesmfirst-order PMGFs, i.e. it is detected by any
test vector that detects one of the first-order PMGFs.

25
 Chapter 4
Testable Reversible Gates.

 Introduction:
The currently available reversible gates can be used to implement arbitrary
logic functions; however, the testing of such circuits has not been addressed in
literature. The testing of reversible logic gates can be a problem because the levels of
logic can be significantly higher than in standard logic circuits.
Here two reversible logic gates, R1 and R2 that can be used in pairs to design
testable reversible logic circuits, are introduced. The first gate R1 is used for
implementing arbitrary functions while the second gate R2 is employed to incorporate
online testability features into the circuit. Gates R1 and R2 are shown in Figures and
the corresponding truth tables of the gates are shown. A third gate R is also introduced
R3 that is used to construct two pair two rail checker. In the next two sections we will
discuss these three gates.

Gate R:
The reversible gate R is shown in Fig 15 and its truth table is
shown. Gate R differs from gates R1 and R2 in gate width. Gate
width of R1 and R2 is 4, while that of R is 3. In other words, R is 3
input-3output reversible gate, while R1 and R2 are 4 input-4 output
reversible gates. The testability feature is not incorporated in gate
R, as it will be used as the basic block for implementing the two pair
two-rail checker.

.
Fig.15 Gate R

26
 From the truth table, it can be verified that the input pattern corresponding to a
particular output pattern can be uniquely determined. The new gate can be used both
to invert and duplicate a signal.

Gate R is a universal gate and its universality is shown in Fig. 16. The signal
duplication function can be obtained by setting the input b to 0, as shown in Fig.
16(b). The EXOR function is available at the output “l” of the new gate. The AND
function is obtained by connecting the input c to 0, the output is obtained at the
terminal n, as shown in Fig. 16(c). The implementation of a NAND gate is shown in
Fig. 16(d). An OR gate is realized by connecting two new reversible gates, as shown
in the Fig. 16(e).

Figure 16. (a) New reversible-logic gate R. (b) Signal duplication. (c) AND gate. (d) NAND gate. (e) OR
gate.

Gates R1 and R2 (reversible gates with built-in testability):

27
 Here, we are introducing R1 and R2 that can be used in pairs to design testable
reversible logic circuits. The first gate R1 is used for implementing arbitrary functions
while the second gate R2 is employed to incorporate online testability features into the
circuit. Gates R1 and R2 are shown in Fig. 17(a); and the corresponding truth tables of
the gates are shown in the preceeding tables. From the truth tables, it can be verified
that the input pattern corresponding to a particular output pattern can be uniquely
determined.

Truth Tables for Gates R1 and R2

28
Figure 17

29
 Gate R1 can implement all Boolean functions and during a normal operation,
the input p is set to 0. The OR and the EXOR functions can be simultaneously
implemented on R1 [Fig. 17(b)]. The EXNOR function and the NAND function are
obtained by setting input c to 1 [Fig. 17(c)]. The NOR function can be obtained by
cascading two R1 gates [Fig. 17(d)]. An AND gate also requires the cascading of two
gates [Fig. 17(e)]. R1 can transfer a signal at input a to output u by setting the input c
to 0.

Gate R2 is used to transfer the input values at d, e, and f to outputs x, y, and z;

it also generates the parity of the input pattern at output s. The output s of the gate is
the complement of the input r if all other inputs of the gate remain unchanged. For
example, if input defr = 1000 is changed to 1001, the output of the gate will change
from 1000 to 1001. During a normal operation, the input r is set to 1.

 Reversible Gates With a Built-in Testability:

A testable logic block can be formed by cascading R1 and R2, as shown in
Fig. 18. In this configuration, gate R2 is used to check online whether there is a fault
in R1 or in itself. If R1 is fault free, its parity output q and the parity output s of R2
should be complementary; otherwise, the presence of a fault is assumed. Thus, during
a normal operation, the presence of a fault in the logic block can be detected.

Figure 18: Testable Block

 Two-pair two-rail checker:

A two-pair two-rail checker is constructed using gate R, as shown in Fig. 19.
The two-pair rail checker is composed of eight R gates. The error checking functions
of the two pair rail checker are as follows:

30
 e1 =x0y1 + y0x1
e2 =x0x1 + y0y1

The fault-free checker will produce the complementary output at e1 and e2 if

the inputs are complementary; otherwise, they will be identical. The block diagram of
the testable block along with the two-pair rail checker is shown in Fig. 20. The
outputs q and s of one testable block forms the input x0 and y0 for the two-pair rail
checker, and the outputs of another testable block forms the input x1 and y1. Thus, the
testable blocks constructed using gates R1 and R2 are tested using the two-pair rail
checker. .

31
 Figure 19: Two-pair two rail checker

The next figure [Fig. 20] shows the block diagram of the testable block along
with the two-pair rail checker shown in Fig. 19.

Figure 20: Testable block embedded with the two-pair two-rail checker

 Synthesis of the reversible logic circuits:

A sum of products (SOP) expression can be synthesized using reversible logic

by converting the SOP expression into a NAND–NAND form. Each testable NAND
block is implemented by cascading gates R1 and R2. Fig. 21 shows the
implementation of (ab)'. If a variable appears more than once in an expression, then a
signal duplication gate will be required. Note that fanouts are not allowed in the
reversible-logic design.

32
 Figure 21 : NAND Gate using R1 and R2

The NAND block based implementation of function F = ab+cd is given below:

1) ab = ( (ab)’)’= (1 XOR ab)’, cd = ( (cd)’)’= (1 XOR ab)’

2) ab + cd = ((ab).(cd))’= ((1 XOR ab).(1 XOR cd))’

The implementation of the function is shown in Fig 22. The number of signal
duplication blocks used instead of fan-outs, depends on the number of times the
variable appears in the function. For example, the number of blocks required to
implement fan out of variable that appears 6 times as “a”, and 3 times as its
complement “ a’ ” is shown in Fig 23. Several MCNC Benchmark functions were
implemented using the above approach. The testable gate count, garbage outputs and
number of checkers are shown in the following Table.

Figure 22: Reversible NAND block implementation for the function ab+cd

33
 Figure 23: Signal Duplication

 CMOS realization of the proposed reversible logic gates:

The transistor level design of the three reversible logic gates are realized in
CMOS. Fig. 24 shows the transistor level design of the gate R. Since an EXOR
functionality is needed for implementing the output functions of the reversible gates,
an efficient four-transistor EXOR function design has been chosen to implement the
transistor level design.

34
 Figure 24: CMOS implementation of gate R

Gate R was implemented using 12 transistors. The implementation of gate R1

is shown in Fig. 25. It took 26 transistors to implement the design. Fig. 26 shows the
four inputs and one output of the reversible gate R2. As the first three output of the
gate are just the direct wire connection from input, the input d, e, and f of the gate can
be used as the output.

35
 Figure 25: CMOS implementation of gate R1

Figure 26: CMOS implementation of gate R2

All the gates (R, ,R1, and R2) can be combined to form a reversible cell, which
minimizes the number transistors by a count of four as a function a XOR c needed by
gate R and gate R1 are shared. Thus, the cell can be implemented with a total of 46
transistors (Fig. 27).

36
Figure 27: Reversible Cell

37
 Estimation of Power:

The implementation of the full adder using the reversible gate R has been
compared with that implemented using the Fredkin Gate. The design implemented
using the proposed gate is found to be more efficient; it requires fewer gates, fewer
garbage outputs, and consumes less power. The power analysis has been made using
Xilinx ISE version 6.1. The full adder with propagate was implemented at the
behavioral level [VHSIC (very high speed integrated circuit) hardware description
language (VHDL)] using the Fredkin gate, the proposed gates, and the Toffoli gate.
The following Table shows the comparison of the designs using these gates.
.

38
 The following Table (in the next page) shows the number of gates, garbage
outputs, and the power estimation of several benchmark circuits implemented in
VHDL using reversible gate R, testable gate R1/R2, and the Fredkin and Toffoli gates.

39
 Chapter 5
BCD ADDER
A one digit BCD adder adds two BCD numbers and produces the BCD sum after the
required correction which is according to the rules for BCD addition.
.

Fig.28 Block Diagram of BCD Adder

Figure illustrates three parts of a BCD adder: 4-bit binary adder, over 9 detection unit
and correction unit. The first part is a binary adder which performs addition on two
four-bit BCD digits and a one-bit carry input. In the second part, the over-9-detector
recognizes if the result of the first part is more than 9 or not. Finally, in the third part,
if the output of detector (P flag) is '1', the sum is added by 6, else do nothing. A
conventional BCD adder is shown in Fig. .

40
 Fig.29 Irreversible BCD Adder

The 4-bit binary adder is cascade of 4 FAs (4-bit carry-propagate adder). The
detection part in Fig. 2 is constructed by using two AND gates (A1, A2) and one OR
gate. The correction unit adds ‘0’ to the binary number if the binary result is less than
10 and adds 6 to the binary result if it is more than 9. A binary full adder is a basic
circuit for designing binary arithmetic units such as n-bit binary adder, subtractor and
multiplier. In the same sense a BCD adder/subtractor is a basic circuit for designing
BCD arithmetic units such as BCD n-digit adder/ subtractor BCD multiplier and so
on.
Fig shows the 4 bit parallel adder constructed using HNG gates which can also be
constructed using TSG or MKG gates

Fig.30 Reversible 4bit parallel adder

REVERSIBLE IMPLEMENTATION OF ONE DIGIT BCD ADDER

The reversible BCD adder/subtractor can be used as a basic circuit for constructing
the other reversible BCD arithmetic circuits. For example, by cascading n blocks of
this circuit, an n digit BCD adder and subtractor can be assembled. Some works are
also done on BCD multiplication which can be extended to reversible form by using
the proposed BCD adder.

The proposed BCD adder circuit uses one such 4 bit parallel adder and is called as
adder-1 in this proposal. The total number of garbage outputs generated from the
reversible parallel adder is equal to eight. The overflow detection uses one SCL gate.

41
This does not produce any garbage outputs. Also the second adder which should add
six in order to correct and convert the sum to BCD sum need not be a 4bit parallel
adder but instead it can be constructed using one Peres gate, one HNG gate and one
Feynman gate.

Fig.31 Reversible BCD Adder

The New gate is used to add S1 with Cout to produce final ∑1 and a carry which is
given to one HNG gate used as a full adder to produce final ∑2. Then the final sum bit
∑3 is obtained by using one Feynman gate. So the BCD sum is ∑3∑2∑1∑0.The
complete BCD adder is as shown in the above fig.
The proposed circuit uses a total number of 8 reversible gates consisting of five HNG
gates, one Peres gate, one Feynman gate and one SCL gate. The number of garbage
outputs in the proposed design is 10. The total delay of the BCD adder is calculated in
terms of the gate delays. If the delay taken to produce the final BCD sum is ηsum then
for a single BCD adder block the total delay is given by, ηsum= ηadder1 +
ηcorrection+ ηadder2
Where ηadder1 = total delay in the 4bit reversible parallel adder.
ηcorrection = delay in generating the Cout.
ηadder2 = delay in generating the final BCD sum.
From the implementation it can be seen that
ηadder1 = 4 HNGs, ηcorrection = 1 SCLG
ηadder2 = 1PG + 1 HNG + 1 FG.
Therefore ηsum= 8 gate delays.

42
 Chapter 6
CONCLUSION AND FUTURE WORK
The design is very useful for the future computing techniques like
ultra low power digital circuits and quantum computers. It is shown
that the proposal is highly optimized in terms of number of
reversible logic gates, number of garbage outputs and the delay
involved. Because of these optimization parameters the overall cost
of
the circuit will be reduced. The design method definitely useful for
the construction of future computer and other computational
structures. Alternate optimization methods are under investigation
as a future work.

43
 (Appendix A)
Irreversibility and Heat Generation
The search for faster and more compact computing circuits leads directly to
the question: What are the ultimate physical limitations on the progress in this
direction? In practice the limitations are likely to be set by the need for access to each
logical element. At this time, however, it is still hard to understand what physical
requirements this puts on the degrees of freedom which bear information. The
existence of a storage medium as compact as the genetic one indicates that one can go
very far in the direction of compactness, at least if we are prepared to make sacrifices
in the way of speed and random access.
Without considering the question of access, however, we can show, or at least
very strongly suggest, that information processing is inevitably accompanied by a
certain minimum amount of heat generation. In a general way this is not surprising.
Computing, like all processes proceeding at a finite rate, must involve some
dissipation. Our arguments, however, are more basic than this, and show that there is
a minimum heat generation, independent of the rate of the process. Naturally the
amount of heat generation involved is many orders of magnitude smaller than the heat
dissipation in any practically conceivable device. The relevant point, however, is that
the dissipation has a real function and is not just an unnecessary nuisance. The much
larger amounts of dissipation in practical devices may be serving the same function.
The conclusion about dissipation can be anticipated in several ways, and our
major contribution will be a tightening of the concepts involved, in a fashion which
will give some insight into the physical requirements for logical devices. The simplest
way of anticipating our conclusion is to note that a binary device must have at least
one degree of freedom associated with the information. Classically a degree of
freedom is associated with kT of thermal energy. Any switching signals passing
between devices must therefore have this much energy to override the noise. This
argument does not make it clear that the signal energy must actually be dissipated.
An alternative way of anticipating the conclusions is to refer to the arguments
by Brillouin and earlier authors, as summarized by Brillouin in his book, Science and

44
Information Theory, to the effect that the measurement process requires a dissipation
of the order of kT. The computing process, where the setting of various elements
depends upon the setting of other elements at previous times, is closely akin to a
measurement. It is difficult, however, to argue out this connection in a more exact
fashion. Furthermore, the arguments concerning the measurement process are based
on the analysis of specific and the specific models involved in the measurement
analysis are rather far from the kind of mechanisms involved in data processing.
In short, it can be said : The information-bearing degrees of freedom of a
computer interact with the thermal reservoir represented by the remaining degrees of
freedom. This interaction plays two roles. First of all, it acts as a sink for the energy
dissipation involved in the computation. This energy dissipation has an unavoidable
minimum arising from the fact that the computer performs irreversible operations.
Secondly, the interaction acts as a source of noise causing errors. In particular thermal
fluctuations give a supposedly switched element a small probability of remaining in
its initial state, even after the switching force has been applied for a long time. It is
shown, in terms of two simple models, that this source of error is dominated by one of
two other error sources:
1) Incomplete switching due to inadequate time allowed for switching.
2 ) Decay of stored information due to thermal fluctuations.

It is, of course, apparent that both the thermal noise and the
requirements for energy dissipation are on a scale which is entirely
negligible in present-day computer components. Actual devices
which are far from minimal in size and operate at high speeds will
be likely to require a much larger energy dissipation to serve the
purpose of erasing the unnecessary details of the computer's past
history.

45
 REFERENCES

1. "Asymptoticay Zero Energy Split-Level Charge Recovery

Logic" : Younis & Knight.
2. Phys. : L. Szilard (1929)
3. Irreversibility and the Heat Generation in the Computing
Process : R. Landauer (1961)
4. Logical Reversibility of Computation : C.H. Bennett (1973)
5. Notes on the history of reversible computation : C. H.
Bennett
6. Synthesis of Reversible Logic Circuits : Shende, Prasad,
Marcov & Hayes
7. Reversible Computing : Alexis De Vos (1999)
8. Reversible & Endoreversible computing : Alexis De Vos
(1995)
9. Conservative Logic : E. Fredkin & T. Toffoli (1981)
10. Fault Testing of Reversible Circuits :Patel, Hayes &
Marcov
11. Analyzing Fault Models for Reversible Logic Circuits : J.
Zhong & J. Muzio
12. The Physical Implementation of Quantum Computation :
David P. DiVincenzo

46