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VLSI Principles
Lecture 3
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
MOS voltage levels
Case 1: NMOS discharges capacitor
Initially: Vout = Vcc (capacitor fully charged)
VGS of NMOS = Vcc
What is final Vout?
Vout Vcc
G D
Vcc Cload
S Vout
time
NMOS remains on since VGS > VT
Final output voltage Vout = 0 V
Value at source (=0) is transferred to the drain (output)….completely
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
MOS voltage levels
Case 2: NMOS charges capacitor
Initially: Vout = 0
Initial VGS of NMOS = Vcc
What is final Vout?
Vcc
Vcc
G D
Vcc
S Vout
Vout Vcc-VT
Cload
time
NMOS remains on until VGS = VT
Final output voltage Vout = Vcc – VT
Value at drain (=1) not transferred completely to the source (output)….
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
MOS voltage levels
Repeat for PMOS:
Case 1: PMOS discharging capacitor
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
Switch Behavior of NMOS and PMOS
To establish a path
between “a” and
“b”, both g1 AND g2
must be ON
To establish a path
between “a” and
“b”, at least g1 OR
g2 must be ON
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
NAND Gate
A 2 NMOS 2 PMOS
PUN transistors must
B transistors must
be in series….
Y be in parallel….
A
PDN
B
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
CMOS NAND Implementation
De Morgan’s Law…..
Y=AB=A+B
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
CMOS 3-input NAND Implementation
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
NOR Gate
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
CMOS 3-input NOR Implementation
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
Combinational Logic
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
Compound Gates
Y= A.B + C.D Needs 20 transistors….
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
Compound Gates Y= A.B + C.D
Need 8 transistors
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
Compound Gates
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
Pass Transistors
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
Transmission Gates: Pass Transistors in Parallel
Both 0 and 1 passed strongly
s
s
Double Rail Logic: both the control input and its complement is required
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
Tristate Buffer
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
Tristate Buffer
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
Transmission Gate as Tristate Buffer
Non-restoring:
input-signal
will slowly
degrade over
a number of
stages
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
Tristate Buffer as Inverter
Restoring: O/P is
directly connected
to Vdd or GND
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
Multiplexer (MUX)
Connects one of n inputs to the output….
Used as data selectors…encoders
4:1 MUX
2:1 MUX
A
A 22 B Y
21 Y inputs C
inputs B
1 output
D
s2 2 Select signals
1 Select signal s1
s
Y = As +Bs’ Y = As1s2 + +Bs1s2’ + Cs1’s2 + Ds1’s2’
2n −1 mk is a minterm of the
In general, 2n inputs will have n select signals Y = ∑ mk I k n control variable and
Ik is the corresponding
k =0 data input 24
Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
Multiplexer (MUX)
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
Non-restoring MUX
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
Inverting and Restoring MUX
S/S = 0/1
D0 = 0: Y =1=D0
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
A 4:1 MUX
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
Static CMOS Summary
In static circuits at every point in time (except when switching)
the output is connected to either GND or VDD via a low
resistance path.
fan-in of n (or n-inputs) requires 2n (n N-type + n P-type) devices
Non-ratioed logic: gates operate independent of PMOS or
NMOS sizes (since no conflict between pull-up and pull-down
networks)
No path ever exists between Vdd and GND: low static power
Fully-restored logic: (NMOS passes “0” only and PMOS passes
“1” only
Gates must be INVERTING: Y = X, so that X=1 (NMOS pull-
down network is “ON”) for Y=0 (node is fully discharged)
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
Latches
CLK=1: D to Q
CLK=0:Holds
state of Q
As long as
CLK remains
high: D to Q
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee
Flip-Flops
Combines two latches:
One +ve sensitive (slave) and one –ve
sensitive latch (master)
Edge Triggered FF or Master-Slave FF Master Slave
QM
CLK=0: D to QM
QM
QM = D
Slave holds previous value
of Q
CLK=1: master can’t sample
input and holds value of D
Slave opens and QM=(D) =Q
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Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee