Performance is important
 Phase noise can limit wireless transceiver performance
 Jitter can be a problem for digital processors
The standard analog PLL implementation is
problematic in many applications
 Analog building blocks on a mostly digital chip pose
design and verification challenges
 The cost of implementation is becoming too high …
Can digital phaselocked loops offer
excellent performance with a lower
cost of implementation?
M.H. Perrott 2
Just Enough PLL Background …
What is a PhaseLocked Loop (PLL)?
ref(t) ref(t)
out(t) out(t)
e(t) v(t) e(t) v(t)
ref(t)
div(t)
e(t) v(t)
Fout = N Fref
ref(t) e(t) Analog v(t) out(t)
Phase
Detect Loop Filter
VCO
div(t) Sepe and Johnston
Divider US Patent (1968)
N
Use digital counter structure to divide VCO frequency
 Constraint: must divide by integer values
Use PLL to synchronize reference and divider output
Output frequency is digitally controlled
M.H. Perrott 5
FractionalN Frequency Synthesizers
KingsfordSmith
ref(t) US Patent (1974)
div(t) Wells
US Patent (1984)
e(t) v(t)
Fout = M.F Fref
ref(t) e(t) Analog v(t) out(t)
Phase
Detect Loop Filter
Riley
VCO US Patent (1989)
div(t) Divider JSSC ‘93
ref(t)
div(t)
e(t) v(t)
Fout = M.F Fref
ref(t) e(t) Analog v(t) out(t)
Phase
Detect Loop Filter
VCO
div(t) Divider
ref(t) out(t)
Phase Analog
Detect Loop Filter
VCO
div(t) Divider
Average of
ref(t)
error(t)
div(t)
error(t)
phase error
ref(t) out(t)
Phase Analog
Detect Loop Filter
VCO
div(t) Divider
Charge
Vout
error(t) Pump
Icp
Cint
ref(t) out(t)
Phase Analog
Detect Loop Filter
VCO
Divider
ref(t) out(t)
Phase Analog
Detect Loop Filter
VCO
Divider
M.H. Perrott 13
Classical TimetoDigital Converter
detector
output
1 e[k]
0
0
ref(t) phase error
tq[k]
output
1 Gain
Δtdel phase T 1
e[k]
error[k] 2π Δtdel
time error
Analog
Control
Varactor
Varactor
DAC
Varactor
Varactor
Digital
Control
Binary Array
Coarse
Control
1x 2x 4x 2 nx
Varactor
Varactor
Unit Element Array
Fine
1x 1x 1x 1x
Control
out(t)
Coarse Initial T
Control Frequency ref(t)
Varactor
Varactor
Tuning
Fine
Control
in[k] Digital
DividebyK Digital Σ−Δ Loop
Modulator Filter
Varactor
Digital
Control
Phase noise
 Same as for
conventional Quantization qraw[k] Phase
VCO Noise Noise
(tank Q, etc.) z=ej2πfTc
Hntf(z)
Quantization noise f f
q[k]
from dithering
Φout(t)
 See Section 3 in[k]
M Tc
2πKv
s
of Supplemental
Slides s=j2πf
M.H. Perrott 21
Modeling
Overall Digital PLL Model
TDC DCO
TDCreferred DCOreferred
Noise Noise
S tq(e j2πfT) S Φn(f)
20 dB/dec
f f
tq[k] TDC Loop Φn(t)
Gain Filter DTCT
Φref[k] 1 e[k] Φout(t)
T 2πKv
Δtdel H(z) T
2π s
z=ej2πfT s=j2πf
Φdiv[k] Divider
CTDT
1 1
N T
TDCreferred noise
DCOreferred noise
M.H. Perrott 24
Introduce a Parameterizing Function
tq[k] TDC Loop Φn(t)
Gain Filter DTCT
Φref[k] 1 e[k] Φout(t)
T 2πKv
Δtdel H(z) T
2π s
TDCreferred noise
DCOreferred noise
M.H. Perrott 26
Key Observations
tq[k] TDC Loop Φn(t)
Gain Filter DTCT
Φref[k] 1 e[k] Φout(t)
T 2πKv
Δtdel H(z) T
2π s
TDCreferred noise
Lowpass with a DC
gain of 2πN
DCOreferred noise
Highpass with a high
frequency gain of 1
x(t) y(t)
CT CT H(f)
x[k] y[k]
DT DT H(ej2πfT)
x[k] y(t)
DT CT H(f)
CT CT
DT DT
DT CT
M.H. Perrott 28
Phase Noise Calculation
TDCreferred DCOreferred
Noise Noise TDC noise
S tq(e j2πfT) S Φn(f)
20 dB/dec
 DT to CT calculation
f f
 Dominates PLL phase
tq[k] Φn(t) noise at low frequency
offsets
2πN G(f) 1G(f)
fo fo
DCO noise
 CT to CT calculation
Φout(t)  Dominates PLL phase
2
noise at high frequency
1
2πN G(f) S tq(e j2πfT) offsets
T
2
1 G(f) S Φn(f)
dBc/Hz
f
fo
M.H. Perrott 29
Example Calculation for Delay Chain TDC
2πN G(f)
Inverter delay = Δtdel = 20 ps fo
2
1 2 Δtdel
2πN G(f)
S Φout(f) T 12
tdc
f
fo
M.H. Perrott 30
CAD Tools
Closed Loop PLL Design Approach
OpenLoop
Design A(f)
G(f) =
ClosedLoop Approach OpenLoop 1+A(f) ClosedLoop
Performance Characteristics Transfer
Specifications A(f) A(f) Function
{f o, type, order} {K,f p,f z, ...} G(f) G(f)
A(f) =
1G(f)
M.H. Perrott 33
Calculated Phase Noise Spectrum with 500 kHz BW
Output Phase Noise of Synthesizer
60
Detector Noise
VCO Noise
70 Total Noise
110
120
130
DCO Noise
140
150
160
3 4 5 6 7
10 10 10 10 10
Frequency Offset (Hz)
TDC noise too high for GSM mask with 500 kHz PLL bandwidth
M.H. Perrott 34
Change PLL Bandwidth to 100 kHz
Key PLL parameters:
 G(f): 100 kHz BW, Type = 2, 2 order rolloff
nd
M.H. Perrott 35
Calculated Phase Noise Spectrum with 100 kHz BW
Output Phase Noise of Synthesizer
60
Detector Noise
VCO Noise
70 Total Noise
110
DCO Noise
120
130
140
150
160
3 4 5 6 7
10 10 10 10 10
Frequency Offset (Hz)
 Where:
M.H. Perrott 38
Verify Calculations Using C++ Behavioral Modeling
1 D Q
CppSim Module Schematic
R
Description
Name  Hierarchical
Inputs, Outputs description of
R Parameters
1 D Q Code system
topology
PFD
Charge Loop Code blocks
Pump Filter
 Specification
of module
Divider
behavior
CppSim Module
Description
using
Σ−Δ
Name templated
Modulator
Inputs, Outputs C++ code
Parameters
Code
http://www.cppsim.com
M.H. Perrott 40
How Do We Improve TDC Performance?
ref(t)
Delay2 Delay2 Delay2
Logic
Coarse Fine
e[k] e[k]
Ramakrishnan, Balsara
VLSID ‘06 Delay  Delay2
ref(t)
Logic
Coarse Fine
e[k] e[k]
Simplified view of: Lee, Abidi
VLSI 2007 Delay
in(t) D Q out(t)
ref(t)
Time Latch
in(t)
Amplifier Δtin Δtin
out(t)
ref(t) ref(t)
ref(t)
in(t) in(t)
out(t) out(t)
Δtout Δtout
M.H. Perrott
 Time difference at input is amplified at output 47
Interpolating timetodigital converter
Tq
M.H. Perrott 48
An OscillatorBased TDC
Phase Error[1] Phase Error[2]
Ring Oscillator
Vdd div(t)
ref(t)
Osc(t)
Reset
ref(t) Counter Count[k]
Logic Count[k]
div(t) Register
e[k]
e[k] 3 3
Output e[k] corresponds to the number of oscillator
edges that occur during the measurement time window
Advantages
 Extremely large range can be achieved with compact area
M.H. Perrott
 Quantization noise is scrambled across measurements 49
A Closer Look at Quantization Noise Scrambling
Phase Error[1] Phase Error[2]
Ring Oscillator
Vdd div(t)
ref(t)
Osc(t)
Reset
ref(t) Counter Count[k]
Logic Count[k]
Quant. q[1] q[3]
div(t) Register Error[k]
q[0] q[2]
e[k]
e[k] 3 3
Quantization error occurs at beginning and end of each
measurement interval
As a rough approximation, assume error is uncorrelated
between measurements
M.H. Perrott
 Averaging of measurements improves effective resolution 50
Deterministic quantizer error vs. scrambled error
M.H. Perrott 51
Proposed GRO TDC Structure
A Gated Ring Oscillator (GRO) TDC
Phase Error[1] Phase Error[2]
Ring Oscillator
div(t)
Enable
ref(t)
Osc(t)
Reset
ref(t) Counter Count[k]
Logic Count[k]
Quant. q[1] q[2]
div(t) Register Error[k]
q[0] q[1]
e[k]
e[k] 3 4
Enable ring oscillator only during measurement intervals
 Hold the state of the oscillator between measurements
Quantization error becomes first order noise shaped!
 e[k] = Phase Error[k] + q[k] – q[k1]
M.H. Perrott
 Averaging dramatically improves resolution! 53
Improve Resolution By Using All Oscillator Phases
Phase Error[1] Phase Error[2]
Ring Oscillator
div(t)
Enable
ref(t)
Osc.
Reset Phases(t)
ref(t) Counters
Logic
div(t) Count[k]
Register Count[k]
e[k]
Quant. q[1] q[2]
Helal, Straayer, Wei,
Error[k] q[0] q[1]
Perrott VLSI 2007
e[k] 11 10
Raw resolution is set by inverter delay
Effective resolution is dramatically improved by averaging
M.H. Perrott 54
GRO TDC Also Shapes Delay Mismatch
Enable
Measurement 1
Enable
Measurement 2
Enable
Measurement 3
Enable
Measurement 4
(a) (b)
Vo 4 Vo 1 M2
Vo 3 Vo 2 Enable M1
M.H. Perrott 56
GRO Prototype
enable
15 Stage Gated Ring Oscillator
En S Q enable(t)
Dis R
enable
Straayer,
Perrott Logic error[k]
M.H. Perrott 57
Measured GRO Results Confirm Noise Shaping
enable
15 Stage Gated Ring Oscillator
Variable enable(t)
S Q
Delay R
enable
40
10
10
M.H. Perrott 61
Proposed multipath gated ring oscillator
Reset
Start Counters
Logic
Stop Count[k]
Register Helal, Straayer, Perrott
e[k] VLSI 2007
Start
Enable 47stage
Timing Gated Ring
Stop Generation Oscillator
Z147
CLK
State
Register
Start
1 2 3 4 5 6 7
Stop
Measurement
Cells
Enable
CLK Out
Adder
Straayer et al., VLSI 2008
70
80 278.8
90 1.2ps
Ideal variance of
50Msps quantizer
Noise of 80fsrms in 1MHz BW with 1ps steps
100 278.6
104 105 106 107 0 40 80 120 160 200
Frequency (Hz) µs)
Time (µ
(a) (b)
Div
N/N+1
Frequency Mbit ΔΣ
1bit
Selection Modulator
Quantization Output
Noise Spectrum Spectrum
Noise
Frequency
Selection
Fout
ΔΣ PLL dynamics
Increasing PLL bandwidth increases impact of ΔΣ
fractionalN noise
M.H. Perrott
 Cancellation offers a way out! 70
Previous Analog Quantization Noise Cancellation
Frequency tuning:
 Use a small 1X varactor to minimize noise sensitivity
 Use another 16X varactor to provide moderate range
 Use a fourbit capacitor array to achieve 3.34.1 GHz range
M.H. Perrott 76
DigitallyControlled Oscillator with Passive DAC
1X varactor minimizes
noise sensitivity
16X varactor provides
moderate range
A fourbit capacitor
Goals of 10bit DAC array covers 3.34.1GHz
 Monotonic
 Minimal active circuitry and no transistor bias currents
M.H. Perrott
 Fullsupply output range 77
Operation of 10bit Passive DAC (Step 1)
Issues:
 GRO range must span entire reference period during
initial lockin
M.H. Perrott 80
Proposed Divider Structure
Divide value
=N0+N1+N2+N3
Step 1: reset
Step 2: frequency acquisition
 Vc(t) varies
 Vf(t) is held at midpoint
Step 3: steadystate lock conditions
 Vc(t) is frozen to take quantization noise away

M.H. Perrott
ΔΣ quantization noise cancellation is enabled
83
FinePath Loop Filter
Accumulator
firstorder 1
IIR
Gain 1z1
1α
K2
1αz1 Gain
K1
M.H. Perrott
 Consists of accumulator plus feedforward path 85
Same Technique Poses Problems for CoarseTune
M.H. Perrott 86
Fix: Leverage the Divider as a Signal Path
Φdiv[k] s=j2πf
Divider
CTDT
Kc 2π z1 1
1z1 T
1
Nnom
0.13μm CMOS
Active area: 0.95 mm2
Chip area: 1.96 mm2
VDD: 1.5V
Current:
 26mA (Core)
 7mA (VCO output
buffer at 1.1V)
GROTDC:
 2.3mA
 157X252 um2
M.H. Perrott 89
Power Distribution of Prototype IC
Divider
DAC
1.4mW
(3%) 2.8mW Ref. Buffer
(6%)
3.0mW
(7%)
3.4mW GROTDC
(7%)
21.0mW
VCO (46%) 6.8mW
(15%)
Digital
7.7mW
(17%)
Suppresses
quantization
noise by
more than
15 dB
Achieves
204 fs
(0.27 degree)
integrated
noise (jitter)
Reference
spur: 65dBc
M.H. Perrott 91
Calculation of Phase Noise Components
−40
VCO Noise
Finepath ΣΔ Quantization Noise
−60 Fine−tune DAC Thermal
Coarse−tune DAC Thermal
Divider Noise (1% left)
−80 GRO Noise
Ref Noise
Close−loop Noise
−100
dBc/Hz
−120
−140
−160
−180
3 4 5 6 7
10 10 10 10 10
foffset
50
Integer boundary
55 (50MHz•73)
Spur (dBc)
60
65
70
16.2us
75
3.62 3.63 3.64 3.65 3.66 3.67
frequency (GHz)
Tested from 3.620 GHz to 3.670 GHz at intervals of 1 MHz
 Worst spurs observed close to integerN boundary
(multiples of 50 MHz)
42dBc worst spur observed at 400kHz offset from boundary
M.H. Perrott 93
Conclusions
out(t)
div(t)
ref(t)
e[k]
5
cnt[k]
4
M.H. Perrott 98
FractionalN Synthesizer Approach (Fout = 4.25Fref )
5
N[k] 4
out(t)
div(t)
ref(t)
e[k]
www.cppsim.com
M.H. Perrott 104
Supplemental Slides
out(t)
Coarse Initial T
Control Frequency ref(t)
Varactor
Varactor
Tuning
Fine
Control
in[k] Digital
DividebyK Digital Σ−Δ Loop
Modulator Filter
1
k m m t t
Tc Tc
Input to the DCO is supplied by the loop filter
 Clocked at 1/T (i.e., reference frequency)
Switched capacitors are dithered by Σ−Δ at a higher rate
 Clocked at 1/T = M/T
c
 Held at a given setting for duration T c
qraw[k]
2πKv Φout(t)
in[k] M Tc
Hstf(z)
f f s
0 1/MTc 0 1/Tc
z=ej2πfTc s=j2πf
Upsampler and zeroorder hold correspond to discrete and
continuoustime sinc functions, respectively
Σ−Δ has signal and noise transfer functions (Hstf(z), Hntf(z))
 Note: var(q
M.H. Perrott
raw[k]) = 1/12 (uniformly distributed from 0 to 1)
108
Simplification of the DCO Model
M Tc
2πKv Φout(t)
in[k] M Tc
Hstf(z)
f f s
0 1/MTc 0 1/Tc
z=ej2πfTc s=j2πf
Focus on low frequencies for calculations to follow
 Assume sinc functions are relatively flat at the low
frequencies of interest
Upsampler is approximated as a gain of M
Zeroorder hold is approximated as a gain of Tc
Assume Hstf(z) = 1
M.H. Perrott
 True for Σ−Δ structures such as MASH (ignoring delays) 109
Further Simplification of DCO Model
Quantization qraw[k] Phase
Noise Noise
z=ej2πfTc
Hntf(z)
f q[k] f
in[k] Φout(t)
2πKv
M Tc
s
s=j2πf
DT to CT spectral calculation:
 w = 2π(153 kHz)
p
 w = 2π(10 kHz)
z
1 1
N T
At low frequencies (i.e., sT << 1), we can use the first
order term of a Taylor series expansion to approximate
 Where:
Note:
Tdco= T/N
*
* Typically implemented by gain normalization circuit
M.H. Perrott 118