Tutorial on

Digital Phase-Locked Loops

CICC 2009
Michael H. Perrott
September 2009

Copyright © 2009 by Michael H. Perrott

 Why Are Digital Phase-Locked Loops Interesting?

ƒ Performance is important
- Phase noise can limit wireless transceiver performance
- Jitter can be a problem for digital processors
ƒ The standard analog PLL implementation is
problematic in many applications
- Analog building blocks on a mostly digital chip pose
design and verification challenges
- The cost of implementation is becoming too high …
Can digital phase-locked loops offer
excellent performance with a lower
cost of implementation?

M.H. Perrott 2
Just Enough PLL Background …
 What is a Phase-Locked Loop (PLL)?

ref(t) ref(t)
out(t) out(t)
e(t) v(t) e(t) v(t)

ref(t) e(t) Analog v(t) out(t)

Phase
Detect Loop Filter
VCO de Bellescize
Onde Electr, 1932

ƒ VCO efficiently provides oscillating waveform with

variable frequency
ƒ PLL synchronizes VCO frequency to input reference
frequency through feedback
- Key block is phase detector
ƒ Realized as digital gates that create pulsed signals
M.H. Perrott 4
 Integer-N Frequency Synthesizers

ref(t)
div(t)
e(t) v(t)
Fout = N Fref
ref(t) e(t) Analog v(t) out(t)
Phase
Detect Loop Filter
VCO
div(t) Sepe and Johnston
Divider US Patent (1968)

N
ƒ Use digital counter structure to divide VCO frequency
- Constraint: must divide by integer values
ƒ Use PLL to synchronize reference and divider output
Output frequency is digitally controlled
M.H. Perrott 5
 Fractional-N Frequency Synthesizers
Kingsford-Smith
ref(t) US Patent (1974)
div(t) Wells
US Patent (1984)
e(t) v(t)
Fout = M.F Fref
ref(t) e(t) Analog v(t) out(t)
Phase
Detect Loop Filter
Riley
VCO US Patent (1989)
div(t) Divider JSSC ‘93

Nsd[k] Σ−Δ N[k] M.F

Modulator

ƒ Dither divide value to achieve fractional divide values

- PLL loop filter smooths the resulting variations
Very high frequency resolution is achieved
M.H. Perrott 6
 The Issue of Quantization Noise

ref(t)
div(t)
e(t) v(t)
Fout = M.F Fref
ref(t) e(t) Analog v(t) out(t)
Phase
Detect Loop Filter
VCO
div(t) Divider

Nsd[k] Σ−Δ N[k] M.F

Modulator
Σ−Δ Quantization Noise
ƒ Limits PLL bandwidth
ƒ Increases linearity requirements of
phase detector f
M.H. Perrott 7
Striving for a Better PLL Implementation
 Analog Phase Detection

1 D Q error(t) phase error

ref(t)
ref(t)
reset
1 D Q div(t)
div(t)
Reg
error(t)

ref(t) out(t)
Phase Analog
Detect Loop Filter
VCO
div(t) Divider

ƒ Pulse width is formed according to phase difference

between two signals
ƒ
M.H. Perrott
Average of pulsed waveform is applied to VCO input
9
 Tradeoffs of Analog Approach

Phase Detector Signals Phase Detector

Characteristic

Average of
ref(t)

error(t)
div(t)

error(t)
phase error

ref(t) out(t)
Phase Analog
Detect Loop Filter
VCO
div(t) Divider

ƒ Benefit: average of pulsed output is a continuous, linear

function of phase error
ƒ Issue: analog loop filter implementation is undesirable
M.H. Perrott 10
 Issues with Analog Loop Filter

Charge
Vout
error(t) Pump
Icp

Cint

ref(t) out(t)
Phase Analog
Detect Loop Filter
VCO
Divider

ƒ Charge pump: output resistance, mismatch

ƒ Filter caps: leakage current, large area
M.H. Perrott 11
 Going Digital …

ref(t) out(t)
Phase Analog
Detect Loop Filter
VCO
Divider

ref(t) Time out(t)

Digital
-to- Loop Filter
Digital
DCO Staszewski et. al.,
Divider TCAS II, Nov 2003

ƒ Digital loop filter: compact area, insensitive to leakage

ƒ Challenges:
- Time-to-Digital Converter (TDC)
M.H. Perrott
- Digitally-Controlled Oscillator (DCO) 12
 Outline of Talk

ƒ Overview of Key Blocks (TDC and DCO)

ƒ Modeling & CAD Tools
ƒ High Performance TDC design
ƒ Quantization Noise Cancellation
ƒ DCO based on an efficient passive DAC structure
ƒ Divider Design
ƒ Loop Filter Design
ƒ Prototype with measured Results

M.H. Perrott 13
 Classical Time-to-Digital Converter

Delay Delay Delay Delay

div(t)
div(t) 1
1
D Q D Q D Q 1 e[k]
0
Reg Reg Reg
e[k] 0
ref(t) ref(t)

ref(t) Time out(t)

Digital
-to- Loop Filter
Digital
DCO
div(t) Divider

ƒ Resolution set by a “Single Delay Chain” structure

- Phase error is measured with delays and registers
ƒ Corresponds to a flash architecture
M.H. Perrott 14
 Impact of Limited Resolution and Delay Mismatch
Delay varies due to mismatch
Phase Detector
div(t) 1 Characteristic
1

detector
output
1 e[k]
0
0
ref(t) phase error

ref(t) Time out(t)

Digital
-to- Loop Filter
Digital
DCO
div(t) Divider
ƒ Integer-N PLL
- Limit cycles due to limited resolution (unless high ref noise)
ƒ Fractional-N PLL
- Fractional spurs due to non-linearity from delay mismatch
M.H. Perrott 15
 Modeling of TDC

Phase Detector quantization

Characteristic error
TDC
detector

tq[k]
output

1 Gain
Δtdel phase T 1
e[k]
error[k] 2π Δtdel
time error

ref(t) Time out(t)

Digital
-to- Loop Filter
T Digital
reference DCO
period div(t) Divider

ƒ Phase error converted to time error by scale factor: T/2π

ƒ TDC introduces quantization error: tq[k]
ƒ TDC gain set by average delay per step: Δtdel
M.H. Perrott 16
 A Straightforward Approach for Achieving a DCO

Analog
Control

Varactor

Varactor
DAC

ref(t) Time out(t)

Digital
-to- Loop Filter
Digital
DCO Ferriss ISSCC 2007
div(t) Divider Hsu ISSCC 2008

ƒ Use a DAC to control a conventional LC oscillator

- Allows the use of an existing VCO within a digital PLL
M.H. Perrott
- Can be applied across a broad range of IC processes 17
 A Much More Digital Implementation

Varactor

Varactor
Digital
Control

ref(t) Time out(t)

Digital
-to- Loop Filter
Digital
DCO Staszewski et. al.,
div(t) Divider TCAS II, Nov 2003

ƒ Adjust frequency in an LC oscillator by switching in a

variable number of small capacitors
M.H. Perrott
- Most effective for CMOS processes of 0.13u and below 18
 Leveraging Segmentation in Switched Capacitor DCO

Binary Array
Coarse
Control
1x 2x 4x 2 nx
Varactor

Varactor
Unit Element Array
Fine
1x 1x 1x 1x
Control

ƒ Similar in design as segmented capacitor DAC structures

- Binary array: efficient control, but may lack monotonicity
- Unit element array: monotonic, but complex control
ƒ Coarse and fine control segmentation of DCO
- Coarse control: active only during initial frequency tuning
(leverage binary array)
- Fine control: controlled by PLL feedback (leverage unit
element array to guarantee monotonicity)
M.H. Perrott 19
 Leveraging Dithering for Fine Control of DCO

out(t)
Coarse Initial T
Control Frequency ref(t)
Varactor

Varactor
Tuning

Fine
Control
in[k] Digital
Divide-by-K Digital Σ−Δ Loop
Modulator Filter

T c=T/M DCO TDC out

ƒ Increase resolution by Σ−Δ dithering of fine cap array
ƒ Reduce noise from dithering by
- Using small unit caps in the fine cap array
- Increasing the dithering frequency (defined as 1/T ) c
ƒ We will assume 1/Tc = M/T (i.e. M times reference frequency)
M.H. Perrott 20
 Calculation of Noise Spectrum: Switched Cap DCO
Varactor

Varactor
Digital
Control

ƒ Phase noise
- Same as for
conventional Quantization qraw[k] Phase
VCO Noise Noise
(tank Q, etc.) z=ej2πfTc
Hntf(z)
ƒ Quantization noise f f
q[k]
from dithering
Φout(t)
- See Section 3 in[k]
M Tc
2πKv
s
of Supplemental
Slides s=j2πf
M.H. Perrott 21
Modeling
 Overall Digital PLL Model
TDC DCO
TDC-referred DCO-referred
Noise Noise
S tq(e j2πfT) S Φn(f)
-20 dB/dec
f f
tq[k] TDC Loop Φn(t)
Gain Filter DT-CT
Φref[k] 1 e[k] Φout(t)
T 2πKv
Δtdel H(z) T
2π s
z=ej2πfT s=j2πf
Φdiv[k] Divider
CT-DT
1 1
N T

ƒ TDC and DCO-referred noise influence overall phase noise

according to associated transfer functions to output
ƒ Calculations involve both discrete and continuous time
M.H. Perrott 23
 Key Transfer Functions
tq[k] TDC Loop Φn(t)
Gain Filter DT-CT
Φref[k] 1 e[k] Φout(t)
T 2πKv
Δtdel H(z) T
2π s

Φdiv[k] z=ej2πfT s=j2πf

CT-DT
1 1
N T

ƒ TDC-referred noise

ƒ DCO-referred noise

M.H. Perrott 24
 Introduce a Parameterizing Function
tq[k] TDC Loop Φn(t)
Gain Filter DT-CT
Φref[k] 1 e[k] Φout(t)
T 2πKv
Δtdel H(z) T
2π s

Φdiv[k] z=ej2πfT s=j2πf

CT-DT
1 1
N T

ƒ Define open loop transfer function A(f) as:

ƒ Define closed loop parameterizing function G(f) as:

- Note: G(f) is a lowpass filter with DC gain = 1

M.H. Perrott 25
 Transfer Function Parameterization Calculations

ƒ TDC-referred noise

ƒ DCO-referred noise

M.H. Perrott 26
 Key Observations
tq[k] TDC Loop Φn(t)
Gain Filter DT-CT
Φref[k] 1 e[k] Φout(t)
T 2πKv
Δtdel H(z) T
2π s

Φdiv[k] z=ej2πfT s=j2πf

CT-DT
1 1
N T

ƒ TDC-referred noise
Lowpass with a DC
gain of 2πN
ƒ DCO-referred noise
Highpass with a high
frequency gain of 1

How do we calculate the output phase noise?

M.H. Perrott 27
 Spectral Density Calculations

x(t) y(t)
CT CT H(f)

x[k] y[k]
DT DT H(ej2πfT)

x[k] y(t)
DT CT H(f)

ƒ CT CT

ƒ DT DT

ƒ DT CT

M.H. Perrott 28
 Phase Noise Calculation
TDC-referred DCO-referred
Noise Noise ƒ TDC noise
S tq(e j2πfT) S Φn(f)
-20 dB/dec
- DT to CT calculation
f f
- Dominates PLL phase
tq[k] Φn(t) noise at low frequency
offsets
2πN G(f) 1-G(f)
fo fo
ƒ DCO noise
- CT to CT calculation
Φout(t) - Dominates PLL phase
2
noise at high frequency
1
2πN G(f) S tq(e j2πfT) offsets
T
2
1- G(f) S Φn(f)
dBc/Hz

f
fo
M.H. Perrott 29
 Example Calculation for Delay Chain TDC

ƒ Ref freq = 1/T = 50 MHz, Δtdel

2

Out freq = 3.6 GHz S tq(e j2πfT)

12
f
tq[k]

2πN G(f)
ƒ Inverter delay = Δtdel = 20 ps fo

2
1 2 Δtdel
2πN G(f)
S Φout(f) T 12
tdc
f
fo

ƒ Note: G(f) = 1 at low offset frequencies

M.H. Perrott 30
CAD Tools
 Closed Loop PLL Design Approach
Open-Loop
Design A(f)
G(f) =
Closed-Loop Approach Open-Loop 1+A(f) Closed-Loop
Performance Characteristics Transfer
Specifications |A(f)| A(f) Function
{f o, type, order} {K,f p,f z, ...} G(f) G(f)
A(f) =
1-G(f)

Proposed Closed Loop Design Approach Lau and Perrott,

DAC, June 2003
ƒ Classical open loop approach
- Indirectly design G(f) using bode plots of A(f)
ƒ Proposed closed loop approach
- Directly design G(f) by examining impact of its
specifications on phase noise (and settling time)
- Solve for A(f) that will achieve desired G(f)
Implemented in PLL Design Assistant Software
http://www.cppsim.com
M.H. Perrott 32
 Evaluate Phase Noise with 500 kHz PLL Bandwidth
ƒ Key PLL parameters:
- G(f): 500 kHz BW, Type II, 2 order rolloff
nd

- TDC noise: -94.7 dBc/Hz

- DCO noise: -153 dBc/Hz at 20 MHz offset (3.6 GHz carrier)

M.H. Perrott 33
 Calculated Phase Noise Spectrum with 500 kHz BW
Output Phase Noise of Synthesizer
-60
Detector Noise
VCO Noise
-70 Total Noise

-80 GSM Mask

Overall PLL (Referenced to
-90 Phase Noise 3.6 GHz carrier)
L(f) (dBc/Hz)

-100 TDC Noise

-110

-120

-130
DCO Noise
-140

-150

-160
3 4 5 6 7
10 10 10 10 10
Frequency Offset (Hz)

TDC noise too high for GSM mask with 500 kHz PLL bandwidth
M.H. Perrott 34
 Change PLL Bandwidth to 100 kHz
ƒ Key PLL parameters:
- G(f): 100 kHz BW, Type = 2, 2 order rolloff
nd

- TDC noise: -94.7 dBc/Hz

- DCO noise: -153 dBc/Hz at 20 MHz offset (3.6 GHz carrier)

M.H. Perrott 35
 Calculated Phase Noise Spectrum with 100 kHz BW
Output Phase Noise of Synthesizer
-60
Detector Noise
VCO Noise
-70 Total Noise

-80 GSM Mask

Overall PLL (Referenced to
-90 Phase Noise 3.6 GHz carrier)
L(f) (dBc/Hz)

-100 TDC Noise

-110
DCO Noise
-120

-130

-140

-150

-160
3 4 5 6 7
10 10 10 10 10
Frequency Offset (Hz)

GSM mask is met with 100 kHz PLL bandwidth

M.H. Perrott 36
 Loop Filter Design using PLL Design Assistant

ƒ PLL Design Assistant allows fast loop filter design

- See Section 4 of Supplemental Slides
ƒ Assumption: Type = 2, 2nd order rolloff

- Where:

ƒ PLL Design Assistant provides the

values of K, wp = 2πfp, wz = 2πfz
M.H. Perrott 37
 Example Digital Loop Filter Calculation
ƒ Assumptions
- Ref freq (1/T) = 50 MHz, Out freq = 3.6 GHz (so N = 72)
- Δt = 20 ps, K = 12 kHz/unit cap
del v
- 100 kHz bandwidth, Type = 2 , 2 order rolloff
nd

M.H. Perrott 38
 Verify Calculations Using C++ Behavioral Modeling

1 D Q
CppSim Module ƒ Schematic
R
Description
Name - Hierarchical
Inputs, Outputs description of
R Parameters
1 D Q Code system
topology
PFD
Charge Loop ƒ Code blocks
Pump Filter
- Specification
of module
Divider
behavior
CppSim Module
Description
using
Σ−Δ
Name templated
Modulator
Inputs, Outputs C++ code
Parameters
Code

ƒ Behavioral environment allows efficient architectural

investigation and validation of calculations
- Fast simulation speed is essential for design investigation
M.H. Perrott 39
 CppSim – A Fast C++ Behavioral Simulator

http://www.cppsim.com
M.H. Perrott 40
How Do We Improve TDC Performance?

Two Key Issues:

• TDC resolution
• Mismatch
 Motivation
TDC-referred DCO-referred
Noise Noise ƒ PLL bandwidth
S tq(e j2πfT) S Φn(f)
-20 dB/dec
dramatically influences
relative impact of TDC
f f
tq[k] Φn(t) and VCO noise

2πN G(f) 1-G(f) Want high PLL

fo fo bandwidth?
Need low
TDC Noise
Φout(t)

Low PLL Bandwidth High PLL Bandwidth

DCO TDC
Noise Noise
dBc/Hz TDC
dBc/Hz
Noise DCO
Noise
f f
fo fo
M.H. Perrott 42
 Improve Resolution with Vernier Delay Technique
Delay Delay Delay Delay
div(t)
div(t) 1
1
D Q D Q D Q 1 e[k]
0
Reg Reg Reg
e[k] 0
ref(t) ref(t)
Delay
Vernier div(t) 1
Delay Delay Delay 1
div(t) 1 e[k]
0
D Q D Q D Q 0
ref(t)
Reg Reg Reg
Effective
ref(t) resolution:
Delay2 Delay2 Delay2
e[k] Delay-Delay2
Delay2
M.H. Perrott 43
 Issues with Vernier Approach

ƒ Mismatch issues are more severe than the single delay

chain TDC
- Reduced delay is formed as difference of two delays
ƒ Large measurement range requires large area
- Initial PLL frequency acquisition may require a large range
Delay
Vernier div(t) 1
Delay Delay Delay 1
div(t) 1 e[k]
0
D Q D Q D Q 0
ref(t)
Reg Reg Reg
Effective
ref(t) resolution:
Delay2 Delay2 Delay2
e[k] Delay-Delay2
Delay2
M.H. Perrott 44
 Two-Step TDC Architecture Allows Area Reduction
Single Delay Chain Vernier
Delay Delay Delay

Delay Delay Delay

div(t)
Mux
D Q D Q D Q
D Q D Q D Q
Reg Reg Reg
Reg Reg Reg

ref(t)
Delay2 Delay2 Delay2
Logic
Coarse Fine
e[k] e[k]
Ramakrishnan, Balsara
VLSID ‘06 Delay - Delay2

ƒ Single delay chain provides

coarse resolution Delay
ƒ (Folded) Vernier provides
fine resolution
M.H. Perrott 45
 Two-Step TDC Using Time Amplification
Single Delay Chain Time Single Delay Chain
Amplifier

Delay Delay Delay Delay Delay Delay

div(t)
Mux
D Q D Q D Q D Q D Q D Q

Reg Reg Reg Reg Reg Reg

ref(t)
Logic
Coarse Fine
e[k] e[k]
Simplified view of: Lee, Abidi
VLSI 2007 Delay

ƒ Single delay chain provides Amplification

coarse and fine resolution Delay of Time

ƒ Time amplification is used

to improve resolution
M.H. Perrott 46
 Leveraging Metastability to Create a Time Amplifier

in(t) D Q out(t)
ref(t)
Time Latch
in(t)
Amplifier Δtin Δtin
out(t)
ref(t) ref(t)
ref(t)
in(t) in(t)

out(t) out(t)

Δtout Δtout

Simplified view of: Abas, et al., Electronic Letters, Nov 2002

(note that actual implementation uses SR latch)

ƒ Metastability leads to progressively slower output

transitions as setup time on latch is encroached upon

M.H. Perrott
- Time difference at input is amplified at output 47
 Interpolating time-to-digital converter

Tq

Delay Delay Delay Start 1

Start 1
1
1 Out
Stop
Registers Tstop 1
1
0
Out
Stop
Henzler et al., ISSCC 2008 Tin

ƒ Interpolate between edges to achieve fine resolution

ƒ Cyclic approach can also be used for large range

M.H. Perrott 48
 An Oscillator-Based TDC
Phase Error[1] Phase Error[2]
Ring Oscillator
Vdd div(t)

ref(t)

Osc(t)

Reset
ref(t) Counter Count[k]

Logic Count[k]
div(t) Register
e[k]
e[k] 3 3
ƒ Output e[k] corresponds to the number of oscillator
edges that occur during the measurement time window
ƒ Advantages
- Extremely large range can be achieved with compact area
M.H. Perrott
- Quantization noise is scrambled across measurements 49
 A Closer Look at Quantization Noise Scrambling
Phase Error[1] Phase Error[2]
Ring Oscillator
Vdd div(t)

ref(t)

Osc(t)

Reset
ref(t) Counter Count[k]

Logic Count[k]
Quant. q[1] q[3]
div(t) Register Error[k]
-q[0] -q[2]
e[k]
e[k] 3 3
ƒ Quantization error occurs at beginning and end of each
measurement interval
ƒ As a rough approximation, assume error is uncorrelated
between measurements
M.H. Perrott
- Averaging of measurements improves effective resolution 50
 Deterministic quantizer error vs. scrambled error

ƒ Deterministic TDC do not provide inherent scrambling

ƒ For oversampling benefit, TDC error must be scrambled!
ƒ Some systems provide input scrambling (ΔΣ fractional-N PLL),
while some others do not (integer-N PLL)

M.H. Perrott 51
Proposed GRO TDC Structure
 A Gated Ring Oscillator (GRO) TDC
Phase Error[1] Phase Error[2]
Ring Oscillator
div(t)
Enable
ref(t)

Osc(t)

Reset
ref(t) Counter Count[k]

Logic Count[k]
Quant. q[1] q[2]
div(t) Register Error[k]
-q[0] -q[1]
e[k]
e[k] 3 4
ƒ Enable ring oscillator only during measurement intervals
- Hold the state of the oscillator between measurements
ƒ Quantization error becomes first order noise shaped!
- e[k] = Phase Error[k] + q[k] – q[k-1]
M.H. Perrott
- Averaging dramatically improves resolution! 53
 Improve Resolution By Using All Oscillator Phases
Phase Error[1] Phase Error[2]
Ring Oscillator
div(t)
Enable
ref(t)

Osc.
Reset Phases(t)
ref(t) Counters
Logic

div(t) Count[k]
Register Count[k]
e[k]
Quant. q[1] q[2]
Helal, Straayer, Wei,
Error[k] -q[0] -q[1]
Perrott VLSI 2007
e[k] 11 10
ƒ Raw resolution is set by inverter delay
ƒ Effective resolution is dramatically improved by averaging
M.H. Perrott 54
 GRO TDC Also Shapes Delay Mismatch
Enable

Measurement 1

Enable

Measurement 2

Enable

Measurement 3

Enable

Measurement 4

ƒ Barrel shifting occurs through delay elements across

different measurements
- Mismatch between delay elements is first order shaped!
M.H. Perrott 55
 Simple gated ring oscillator inverter-based core
Enabled Ring Oscillator Disabled Ring Oscillator

(a) (b)

Enable Delay Element

Gate the oscillator by switching Enable M4
the inverter cores to the Vo n-1
M3
power supply Vo 5
Vo n
Vo i-1 Vo i

Vo 4 Vo 1 M2

Vo 3 Vo 2 Enable M1

M.H. Perrott 56
 GRO Prototype
enable
15 Stage Gated Ring Oscillator
En S Q enable(t)
Dis R

enable

Straayer,
Perrott Logic error[k]

ƒ GRO implemented as a custom

0.13 μm CMOS IC

M.H. Perrott 57
 Measured GRO Results Confirm Noise Shaping

enable
15 Stage Gated Ring Oscillator
Variable enable(t)
S Q
Delay R

enable

40

30 Input variable Harmonics due Logic error[k]

delay signal to nonlinearity of
20 variable delay
Amplitude (dB)

10

-10

-20 Noise shaped

quant. noise
-30
0.01 0.1 1 10 100
Frequency (MHz)
M.H. Perrott 58
 Measured deadzone behavior of inverter-based GRO

ƒ Deadzones were caused by errors in gating the oscillator

ƒ GRO “injection locked” to an integer ratio of FS
ƒ Behavior occurred for almost all integer boundaries, and
some fractional values as well
ƒ Noise shaping benefit was limited by this gating error
M.H. Perrott 59
 Next Generation GRO: Multi-path oscillator concept

Single Input Multiple Inputs

Single Output Single Output

ƒ Use multiple inputs for each delay element instead of one

ƒ Allow each stage to optimally begin its transition based on
information from the entire GRO phase state
ƒ Key design issue is to ensure primary mode of oscillation
M.H. Perrott 60
 Multi-path inverter core

Lee, Kim, Lee

JSSC 1997

Mohan, et. al.,

CICC 2005

M.H. Perrott 61
 Proposed multi-path gated ring oscillator

Hsu, Straayer, Perrott

ISSCC 2008

ƒ Oscillation frequency near 2GHz with 47 stages…

ƒ Reduces effective delay per stage by a factor of 5-6!
ƒ Represents a factor of 2-3 improvement compared to previous
multi-path oscillators
M.H. Perrott 62
 A simple measurement approach…
N-Stage Gated Ring Oscillator
Enable

Reset
Start Counters
Logic

Stop Count[k]
Register Helal, Straayer, Perrott
e[k] VLSI 2007

ƒ 2 counters per stage * 47 stages = 94 counters each at 2GHz

ƒ Power consumption for these counters is unreasonable

Need a more efficient way to measure the multi-path GRO

M.H. Perrott 63
 Count Edges by Sampling Phase

ƒ Calculate phase from:

- A single counter for coarse phase information (keeps track of
phase wrapping)
- GRO phase state for fine count information
ƒ 1 counter and N registers Æ much more efficient
M.H. Perrott 64
 Proposed Multi-Path Measurement Structure

ƒ Multi-path structure leads to ambiguity in edge position

ƒ Partition into 7 cells to avoid such ambiguity
ƒ Requires 7 counters rather than 1, but power still OK 65
M.H. Perrott
 Prototype 0.13μm CMOS multi-path GRO-TDC

Start
Enable 47-stage
Timing Gated Ring
Stop Generation Oscillator
Z1-47
CLK
State
Register
Start
1 2 3 4 5 6 7
Stop
Measurement
Cells
Enable

CLK Out
Adder
Straayer et al., VLSI 2008

ƒ Two implemented versions:

- 8-bit, 500Msps
- 11-bit, 100Msps version
ƒ 2-21mW power consumption depending on input duty cycle
M.H. Perrott 66
 Measured noise-shaping of multi-path GRO
65,536 pt. FFT
(Hanning window + 20x averaging) TDC Output after 1MHz LPF
-40 279.2
Input of
1.2pspp
-50
Power Spectral Density

Filtered TDC Output

-60 279.0
(dB ps2/Hz)

-70

-80 278.8

-90 1.2ps
Ideal variance of
50-Msps quantizer
Noise of 80fsrms in 1MHz BW with 1ps steps
-100 278.6
104 105 106 107 0 40 80 120 160 200
Frequency (Hz) µs)
Time (µ
(a) (b)

ƒ Data collected at 50Msps

ƒ More than 20dB of noise-shaping benefit
ƒ 80fsrms integrated error from 2kHz-1MHz
ƒ Floor primarily limited by 1/f noise (up to 0.5-1MHz)
M.H. Perrott 67
 Measured deadzone behavior for multi-path GRO

ƒ Only deadzones for outputs that are multiples of 2N

- 94, 188, 282, etc.
- No deadzones for other even or odd integers, fractional output
ƒ Size of deadzone is reduced by 10x
M.H. Perrott 68
The Issue of Quantization Noise Due to
Divider Dithering
 The Nature of the Quantization Noise Problem

Ref PFD Loop

Filter Out

Div
N/N+1

Frequency M-bit ΔΣ
1-bit
Selection Modulator
Quantization Output
Noise Spectrum Spectrum
Noise
Frequency
Selection
Fout

ΔΣ PLL dynamics
ƒ Increasing PLL bandwidth increases impact of ΔΣ
fractional-N noise
M.H. Perrott
- Cancellation offers a way out! 70
 Previous Analog Quantization Noise Cancellation

ƒ Phase error due to ΔΣ is predicted by accumulating

ΔΣ quantization error
ƒ Gain matching between PFD and D/A must be precise
Matching in analog domain limits performance
M.H. Perrott 71
 Proposed All-digital Quantization Noise Cancellation

Hsu, Straayer, Perrott

ISSCC 2008

ƒ Scale factor determined by simple digital correlation

ƒ Analog non-idealities such as DC offset are completely
eliminated
M.H. Perrott 72
 Details of Proposed Quantization Noise Cancellation

ƒ Correlator out is accumulated

and filtered to achieve scale factor
- Settling time chosen to be around
10 us
ƒ See analog version of this
technique in Swaminathan et.al.,
ISSCC 2007
M.H. Perrott 73
 Proposed Digital Wide BW Synthesizer

ƒ Gated-ring-oscillator (GRO) TDC achieves low in-band

noise
ƒ All-digital quantization noise cancellation achieves low
out-of-band noise
ƒ Design goals:
- 3.6-GHz carrier, 500-kHz bandwidth
M.H. Perrott
- <-100dBc/Hz in-band, <-150 dBc/Hz at 20 MHz offset 74
 Overall Synthesizer Architecture

Note: Detailed behavioral simulation model available at

http://www.cppsim.com
M.H. Perrott 75
 Dual-Port LC VCO

ƒ Frequency tuning:
- Use a small 1X varactor to minimize noise sensitivity
- Use another 16X varactor to provide moderate range
- Use a four-bit capacitor array to achieve 3.3-4.1 GHz range
M.H. Perrott 76
 Digitally-Controlled Oscillator with Passive DAC

ƒ 1X varactor minimizes
noise sensitivity
ƒ 16X varactor provides
moderate range
ƒ A four-bit capacitor
ƒ Goals of 10-bit DAC array covers 3.3-4.1GHz
- Monotonic
- Minimal active circuitry and no transistor bias currents
M.H. Perrott
- Full-supply output range 77
 Operation of 10-bit Passive DAC (Step 1)

ƒ 5-bit resistor ladder; 5-bit switch-capacitor array

ƒ Step 1: Capacitors Charged
- Resistor ladder forms V = M/32•V and V = (M+1)/32•V ,
L DD H DD
where M ranges from 0 to 31
- N unit capacitors charged to V , and (32-N) unit capacitors
H
charged to VL
M.H. Perrott 78
 Operation of 10-bit Passive DAC (Step 2)

ƒ Step 2: Disconnect Capacitors from Resistors, Then

Connect Together
- Achieves DAC output with first-order filtering
- Bandwidth = 32• C /(2π•C )•50MHz
u load
ƒ Determined by capacitor ratio
ƒ Easily changed by using different Cload
M.H. Perrott 79
 Now Let’s Examine Divider …

ƒ Issues:
- GRO range must span entire reference period during
initial lock-in
M.H. Perrott 80
 Proposed Divider Structure

Divide value
=N0+N1+N2+N3

ƒ Resample reference with 4x division frequency

M.H. Perrott
- Lowers GRO range to one fourth of the reference period
81
 Proposed Divider Structure (cont’d)

ƒ Place ΔΣ dithered edge away from GRO edge

M.H. Perrott
- Prevents extra jitter due to divide-value dependent delay
82
 Dual-Path Loop Filter

ƒ Step 1: reset
ƒ Step 2: frequency acquisition
- Vc(t) varies
- Vf(t) is held at midpoint
ƒ Step 3: steady-state lock conditions
- Vc(t) is frozen to take quantization noise away
-
M.H. Perrott
ΔΣ quantization noise cancellation is enabled
83
 Fine-Path Loop Filter

ƒ Equivalent to an analog lead-lag filter

- Set zero (62.5kHz) and first pole (1.1MHz) digitally
- Set second pole (3.1MHz) by capacitor ratio
ƒ
M.H. Perrott
First-order ΔΣ reduces in-band quantization noise
84
 Linearized Model of PLL Under Fine-Tune Operation

Accumulator
first-order 1
IIR
Gain 1-z-1
1-α
K2
1-αz-1 Gain
K1

TDC Loop DAC

Gain Filter ΔΣ Gain DT-CT VCO
Φref[k] 1 e[k] V Φout(t)
T 2πKv
Δtdel H(z) 1 T
2π 2B s

Φdiv[k] z=ej2πfT s=j2πf

divider CT-DT
1 1
Nnom T

ƒ Standard lead-lag filter topology but implemented in

digital domain

M.H. Perrott
- Consists of accumulator plus feedforward path 85
 Same Technique Poses Problems for Coarse-Tune

ƒ DAC thermal noise impacts

performance due to the
higher coarse VCO gain
- Can we somehow lower
the DAC bandwidth?

M.H. Perrott 86
 Fix: Leverage the Divider as a Signal Path

ƒ Bypass to divider for feed-

forward path allows coarse
DAC bandwidth to be
dramatically reduced!
M.H. Perrott 87
 Linearized Model of PLL Under Coarse-Tune Operation
TDC first-order DAC
Gain IIR Accum. Gain DT-CT VCO
Φref[k] 1 e[k] 1-α V Φout(t)
T 1 1 2πKvc
Δtdel 4 T
2π 1-αz-1 1-z-1 64 2B s

Φdiv[k] s=j2πf
Divider
CT-DT

Kc 2π z-1 1
1-z-1 T

1
Nnom

ƒ Routing of signal path into Sigma-Delta controlling

the divider yields a feedforward path
- Adds to accumulator path as both signals pass back
through the divider
- Allows reduction of coarse DAC bandwidth
ƒ Noise impact of coarse DAC on VCO is substantially
lowered
M.H. Perrott 88
 Die Photo of Prototype

ƒ 0.13-μm CMOS
ƒ Active area: 0.95 mm2
ƒ Chip area: 1.96 mm2
ƒ VDD: 1.5V
ƒ Current:
- 26mA (Core)
- 7mA (VCO output
buffer at 1.1V)

GRO-TDC:
- 2.3mA
- 157X252 um2

M.H. Perrott 89
 Power Distribution of Prototype IC

Divider
DAC
1.4mW
(3%) 2.8mW Ref. Buffer
(6%)
3.0mW
(7%)
3.4mW GRO-TDC
(7%)
21.0mW
VCO (46%) 6.8mW
(15%)
Digital
7.7mW
(17%)

VCO Pad Buffer

Total Power: 46.1mW
ƒ Notice GRO and digital quantization noise
cancellation have only minor impact on power
(and area)
M.H. Perrott 90
 Measured Phase Noise at 3.67GHz

ƒ Suppresses
quantization
noise by
more than
15 dB
ƒ Achieves
204 fs
(0.27 degree)
integrated
noise (jitter)
ƒ Reference
spur: -65dBc

M.H. Perrott 91
 Calculation of Phase Noise Components

−40
VCO Noise
Finepath ΣΔ Quantization Noise
−60 Fine−tune DAC Thermal
Coarse−tune DAC Thermal
Divider Noise (1% left)
−80 GRO Noise
Ref Noise
Close−loop Noise
−100
dBc/Hz

−120

−140

−160

−180
3 4 5 6 7
10 10 10 10 10
foffset

ƒ See wideband digital synthesizer tutorial available at

http://www.cppsim.com
M.H. Perrott 92
 Measured Worst Spurs over Fifty Channels

-50
Integer boundary
-55 (50MHz•73)
Spur (dBc)

-60

-65

-70
16.2us
-75
3.62 3.63 3.64 3.65 3.66 3.67
frequency (GHz)
ƒ Tested from 3.620 GHz to 3.670 GHz at intervals of 1 MHz
- Worst spurs observed close to integer-N boundary
(multiples of 50 MHz)
ƒ -42dBc worst spur observed at 400kHz offset from boundary
M.H. Perrott 93
 Conclusions

ƒ Digital Phase-Locked Loops look extremely promising

for future applications
- Very amenable to future CMOS processes
- Excellent performance can be achieved
ƒ Analysis of digital PLLs is similar to analog PLLs
- PLL bandwidth is often chosen for best noise performance
ƒ TDC (or Ref) noise dominates at low frequency offsets
ƒ DCO noise dominates at high frequency offsets
ƒ Behavioral simulation tools such as CppSim allow
architectural investigation and validation of calculations
ƒ TDC structures are an exciting research area
- Ideas from A-to-D conversion can be applied
Innovation of future digital PLLs will involve joint
circuit/algorithm development
M.H. Perrott 94
 Supplemental Slides

Section 1: Digital Fractional-N Frequency

Synthesizers
 A First Glance at Fractional-N Signals (Fout = 4.25Fref )
5
N[k] 4
out(t)
div(t)
ref(t)
e[k]

ref(t) Time e[k] out(t)

Digital
-to- Loop Filter
Digital
DCO
div(t) Divider
N[k]

ƒ Constant divide value of N = 4 leads to frequency error

- Phase error accumulates in unbounded manner
M.H. Perrott 96
 TI Approach to Fractional Division

out(t)
div(t)
ref(t)
e[k]
5
cnt[k]
4

ref(t) Time e[k] out(t)

Phase Digital
-to- Reg Unwrap Loop Filter
Digital Staszewski
DCO
cnt[k] et. al.,
Reg Reg count
Re-time reset TCAS II, Nov
ref(t) div(t) 2003
signal

ƒ Wrap e[k] by feeding delay chain in TDC with out(t)

ƒ Counter provides information of when wrapping occurs
M.H. Perrott 97
 Key Issues

ref(t) Time e[k] out(t)

Phase Digital
-to- Reg Unwrap Loop Filter
Digital
DCO
cnt[k]
Reg Reg count
Re-time reset
ref(t) div(t)
signal

ƒ Counter, re-timing register, and delay stages of TDC

must operate at very high speeds
- Power consumption can be an issue
ƒ Calibration of TDC scale factor required to achieve
proper unwrapping of e[k]
- Can be achieved continuously with relative ease
ƒ See Staszewski et. al, JSSC, Dec 2005

M.H. Perrott 98
 Fractional-N Synthesizer Approach (Fout = 4.25Fref )
5
N[k] 4
out(t)
div(t)
ref(t)
e[k]

ref(t) Time e[k] out(t)

Digital
-to- Loop Filter
Digital
DCO
div(t) Divider
4.25 N[k]
Accum

ƒ Accumulator guides the “swallowing” of VCO cycles

- Average divide value of N = 4.25 is achieved in this case
M.H. Perrott 99
 The Accumulator as a Phase “Observer”

ƒ Accumulator residue corresponds to an estimate of the

instantaneous phase error of the PLL
- Fractional value (i.e., 0.25) yields the slope of the residue
ƒ Carry out signal is asserted when the phase error
deviation (i.e. residue) exceeds one VCO cycle
- Carry out signal accurately predicts when a VCO cycle
should be “swallowed”

ref(t) Time e[k] out(t)

Digital
-to- Loop Filter
Digital
DCO
div(t) Divider
N.Frac = 4.25 Carry Out Residue
Accum Frac
=0.25
Carry
Out
M.H. Perrott 100
 Improve Dithering Using Sigma-Delta Modulation
ƒ Provides improved noise performance over
accumulator-based divide value dithering
- Dramatic reduction of spurious noise
- Noise shaping for improved in-band noise
- Maintains bounded phase error signal
ƒ Digital Σ−Δ fractional-N synthesizer architecture is
directly analogous to analog Σ−Δ fractional-N synth.

ref(t) Time e[k] out(t)

Digital
-to- Loop Filter
Digital
DCO
div(t) Σ−Δ Quantization
Divider Noise
Nsd[k] N[k]
Σ−Δ Modulator M.F
f

M.H. Perrott 101

 Model of Digital Σ−Δ Fractional-N PLL
TDC DCO
TDC-referred DCO-referred
Noise Noise
S tq(e j2πfT) S Φn(f)
-20 dB/dec
f f
tq[k] TDC Loop Φn(t)
Gain Filter DT-CT
Φref[k] 1 e[k] Φout(t)
T 2πKv
Δtdel H(z) T
2π s
z=ej2πfT s=j2πf
Φdiv[k] Divider CT-DT
1 1
Σ−Δ Quantization Nnom T
Noise
S q(e j2πfT ) n[k] -1
2π z
1-z-1 z=ej2πfT
f

ƒ Divider model is expanded to include the impact of

M.H. Perrott
divide value variations 102
 Transfer Function View of Digital Σ−Δ Fractional-N PLL
TDC-referred DCO-referred
Noise Noise ƒ Σ−Δ quantization
S tq(e j2πfT) S Φn(f) -20 dB/dec noise now
impacts the
f f
Σ−Δ Quantization tq[k] Φn(t)
overall PLL phase
Noise noise
S q(e j2πfT )
fo
2πNnomG(f)
fo
1-G(f) - High PLL
f bandwidth will
T G(f) increase its
n[k] -1
2π z impact
1-z-1 fo Φout(t)
z=ej2πfT
ƒ Digital PLL
1 2
2πNnomG(f) S tq(e j2πfT) implementation
T
2 simplifies
1- G(f) S Φn(f)
quantization noise
dBc/Hz 2
1 2πT G(f) S (e j2πfT) cancellation
T 1-e -j2πfT q
See: Hsu, Straayer, Perrott
f
fo JSSC Dec 2008 for details
M.H. Perrott 103
 For More Information on Digital Fractional-N PLLs

ƒ Check out the CppSim tutorial:

- Design of a Low-Noise Wide-BW 3.6GHz Digital Σ−Δ Fractional-N
Frequency Synthesizer Using the PLL Design Assistant and CppSim

www.cppsim.com
M.H. Perrott 104
Supplemental Slides

Section 2: DCO Modeling

 Leveraging Dithering for Fine Control of DCO

out(t)
Coarse Initial T
Control Frequency ref(t)
Varactor

Varactor
Tuning

Fine
Control
in[k] Digital
Divide-by-K Digital Σ−Δ Loop
Modulator Filter

T c=T/M DCO TDC out

ƒ Increase resolution by Σ−Δ dithering of fine cap array
ƒ Reduce noise from dithering by
- Using small unit caps in the fine cap array
- Increasing the dithering frequency (defined as 1/T ) c
ƒ We will assume 1/Tc = M/T (i.e. M times reference frequency)
M.H. Perrott 106
 Time-Domain Modeling of the DCO
Digital Σ−Δ Zero-Order Frequency
Upsampler Modulator Hold to Phase
in[k] insd[m] inq[m] 1 incap(t) fcap(t) Φout(t)
M Σ−Δ t Kv 2π
0 Tc

in[k] insd[m] inq[m] incap(t) Φout(t)

1
k m m t t
Tc Tc
ƒ Input to the DCO is supplied by the loop filter
- Clocked at 1/T (i.e., reference frequency)
ƒ Switched capacitors are dithered by Σ−Δ at a higher rate
- Clocked at 1/T = M/T
c
- Held at a given setting for duration T c

ƒ Fine cap element value determines Kv of VCO

M.H. Perrott
- Units of Kv are Hz/unit cap
107
 Frequency Domain Modeling of DCO
Digital Σ−Δ Zero-Order Frequency
Upsampler Modulator Hold to Phase
in[k] insd[m] inq[m] 1 incap(t) fcap(t) Φout(t)
M Σ−Δ t Kv 2π
0 Tc

qraw[k]

Upsampler Digital Σ−Δ Hntf(z) Zero-Order Conversion

by M Modulator Hold to Phase

2πKv Φout(t)
in[k] M Tc
Hstf(z)
f f s
0 1/MTc 0 1/Tc
z=ej2πfTc s=j2πf
ƒ Upsampler and zero-order hold correspond to discrete and
continuous-time sinc functions, respectively
ƒ Σ−Δ has signal and noise transfer functions (Hstf(z), Hntf(z))
- Note: var(q
M.H. Perrott
raw[k]) = 1/12 (uniformly distributed from 0 to 1)
108
 Simplification of the DCO Model

M Tc

Digital Σ−Δ qraw[k]

Modulator
Upsampler 1 Hntf(z) Zero-Order Conversion
by M Hold to Phase

2πKv Φout(t)
in[k] M Tc
Hstf(z)
f f s
0 1/MTc 0 1/Tc
z=ej2πfTc s=j2πf
ƒ Focus on low frequencies for calculations to follow
- Assume sinc functions are relatively flat at the low
frequencies of interest
ƒ Upsampler is approximated as a gain of M
ƒ Zero-order hold is approximated as a gain of Tc
ƒ Assume Hstf(z) = 1

M.H. Perrott
- True for Σ−Δ structures such as MASH (ignoring delays) 109
 Further Simplification of DCO Model
Quantization qraw[k] Phase
Noise Noise
z=ej2πfTc
Hntf(z)
f q[k] f
in[k] Φout(t)
2πKv
M Tc
s
s=j2πf

ƒ Proper design of DCO will

DCO-Referred
yield quantization noise Noise
S Φn(f)
that is below that of the
intrinsic phase noise (set f
by tank Q, etc.) Φn(t)
- Assume q[k] = 0 for in[k]
DT-CT
2πKv
Φout(t)
simplified model T
s
ƒ Note that T = MTc
s=j2πf
M.H. Perrott 110
 Supplemental Slides

Section 3: Derivation of VCO Quantization Noise

Due to Capacitor Dithering
 Calculation of Quantization Noise from Cap Dithering
Quantization qraw[k] Phase
Noise Noise
z=ej2πfTc
Hntf(z)
f q[k] f
in[k] Φout(t)
2πKv
M Tc
s
s=j2πf

ƒ DT to CT spectral calculation:

-S qraw(f) = 1/12 since qraw[k] uniformly distributed from 0 to 1

-H ntf(z) is often 1-z (first order) or (1-z ) (second order)
-1 -1 2

M.H. Perrott 112

 Example Calculation for DCO Quantization Noise

ƒ Assumptions (Out freq = 3.6 GHz)

- Dithering frequency is 200 MHz (i.e., 1/T = 200e6)
c
- Σ−Δ has first order shaping (i.e., H (z) = 1 - z )
ntf
-1

- Fine cap array yields 12 kHz/unit cap (i.e., K = 12e3)

v

ƒ At a frequency offset of f = 20 MHz:

Below the phase noise (-153 dBc/Hz at 20 MHz) in the example

M.H. Perrott 113
 Supplemental Slides
Section 4: Derivation of Discrete-Time Loop Filter
Parameterization based on Continuous-Time
Specifications
 Transfer Function Design using PLL Design Assistant

ƒ PLL Design Assistant assumes continuous-time open

loop transfer function Acalc(s):

ƒ Above parameters are calculated

based on the desired closed loop
PLL bandwidth, type, and order of
rolloff (which specify G(s))
ƒ For 100 kHz bandwidth, type = 2,
2nd order rolloff, we have:
- K = 3.0x1010

- w = 2π(153 kHz)
p
- w = 2π(10 kHz)
z

M.H. Perrott 115

 Continuous-Time Approximation of Digital PLL
tq[k] TDC Loop Φn(t)
Gain Filter DT-CT
Φref[k] 1 e[k] Φout(t)
T 2πKv
Δtdel H(z) T
2π s

Φdiv[k] z=esT CT-DT s=j2πf

1 1
N T

ƒ At low frequencies (i.e., |sT| << 1), we can use the first
order term of a Taylor series expansion to approximate

ƒ Resulting continuous-time approximation of open

loop transfer function of digital PLL:

M.H. Perrott 116

 Applying PLL Design Assistant to Digital PLL Design

ƒ Given the continuous-time approximation of A(s), we

then leverage the PLL Design Assistant calculation:

- Also note that:

ƒ Given the above, we obtain:

M.H. Perrott 117

 Simplified Form for Digital Loop Filter (Type II PLL)

ƒ From previous slide:

ƒ Simplified form with type = 2 (assume order = 2)

- Where:

Note:
Tdco= T/N
*
* Typically implemented by gain normalization circuit
M.H. Perrott 118