Integrity of Power for better

performance of high speed designs

S. Lakshminarayanan
Technical Lead
HCL Technologies
www.hcl.in
 Agenda for discussion

 Introduction
 Structure of PDN
 Target Impedance
 Simplified Concept of PI
 Case Study
 Conclusion

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Introduction

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Power Delivery some thoughts
 Why to think of PI… ?
 Power consumption of chips
 Noise margin available

 Does all boards need PI?

 If not, How to select?

 Does it affects SI?

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Rise time Vs Power Delivery
Rise Time < 2 x Propagation Time
V = C/√Er
Tp = Distance / Velocity
PD = 1/V
= √Er/C
Tp = 81 cm x (2.3) / 300x10^6
= 4.15 ns (For one way trip)
TD = X * √Er/C

2Tp = 8.30 ns (For two way trip)

Now if Tr is 20% of the Time Period

then,
T = 8.3 / 0.2
= 41.5 ns
= 24 MHz

“Short time to deliver high current requirement”

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Requirements of PDN

● Worst-case peak-to-peak transient noise

● Resonance-free construction

● Uniform stress distribution

● Cost

● Size (area, component height)

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Structure of PDN

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Structure of PDN

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Low impedance path

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Target Impedance

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 FFT Plot

S.No Frequency dBA A Z

1 600 11.92221155 3.945577494 0.012672416

2 1200 -301.9085483 8.02736E-16 6.2287E+13

3 1800 1.206646793 1.149032571 0.043514867

4 2400 -304.3245978 6.07813E-16 8.22621E+13

5 3000 -5.802742401 0.512699484 0.097523016

6 3600 -307.2438012 4.3432E-16 1.15122E+14

7 4200 -13.43353921 0.21297226 0.23477236

8 4800 -314.4586642 1.89263E-16 2.64182E+14

9 5400 -25.91717322 0.050598931 0.988163175

10 6000 -349.1444803 3.4896E-18 1.43283E+16

11 6600 -30.07829834 0.031338996 1.59545633

12 7200 -317.72411 1.29955E-16 3.84747E+14

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Mathematical Model
Frequency Vs Current

4.5
4
3.5
Current (Amps)

3
2.5
2
1.5
1
0.5
0
0 1000 2000 3000 4000 5000
Frequency (MHz)
Frequency Vs Impedance

1.8
1.6
Impedance (Ohms) 1.4
1.2
1
0.8
0.6
0.4
0.2
0
0 1000 2000 3000 4000 5000 6000 7000
Frequency (MHz)

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Adaptive Slope range

Harmonics Vs Amplitude
Frequency dBA
15
1 11.922212 10
5

Amplitude (dBA)
3 1.2066468 0
5 -5.8027424 -5 0 2 4 6 8 10 12
-10
7 -13.433539 -15
-20
9 -25.917173 -25
-30
11 -30.078298
-35
Harmonics

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Power plane Impedance

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 PI - Simple definition

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Concept of current Bucket
Typical PDS charge storage areas include on-chip capacitors, on-
package capacitors, PCB ceramic and bulk capacitors, and capacitors
associated with the VRM.

Bucket analogy for power integrity and capacitor placement

Water Well
Water Tank
Bucket 1 Bucket 2
Bucket 3 Bucket 4

Switching
Bulck Mid Frequency High Frequency
Regulator IC / Chip
Capacitors Capacitors Capacitors

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Case Study

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Image Card - DC drop results

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Image Card – Impedance results
Voltage Tolerance Load Dynamic Target
Current Current Impedance
S.No Rail Name Volts % Amps Amps Ohms
1 ASIC_CORE 1.00 5 4.2 2.1 0.023809524
2 DDR3 1.50 5 0.3 0.15 0.5
3 ASIC_IO 2.50 5 1.3 0.65 0.192307692

Requirements

Board Dimension

Impedance curve of 1V

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Image Card – Noise results

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Prior to Hyperlynx…?

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Observations

 Via filling with copper and its effects on the DC

drop analysis
 Placement radius
 Placement method
 Usage of MICRO vias, blind buried vias
 Calculation of ESR values from Vendor website

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Conclusion

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Conclusion

 Understanding of Load transient current

requirement is very important for the PI analysis.
 We need to work closely with the chip vendors as
mostly we don’t find the current profile details in
the datasheet.
 Working towards a common forum to include this
details in datasheet might help the industry in long
run.

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010
 Thank you

lakshminarayanans@hcl.in
Mobile: 9840250902

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S. Lakshminarayanan, Integrity of power for better performance of High Speed designs, 2010