ECE 448

Lecture 19

ASIC Design Flow

 Sources
• Jamie Bernard,
Physical Level Design using Synopsys,
Scholarly Paper, GMU, 2005

• Cory Ellinger,
VLSI Design Automation,
Independent Research Project,
GMU, 2005.
Introduction
 Introduction
• Technological Advances
– 19th Century - Steel
– 20th Century – Silicon

• Growth in Microelectronic (Silicon) Technology

– Moore’s Law (# of transistors double/18 months)
– One Transistor
– Small Scale Integration (SSI)
• Multiple Devices (Transistor / Resistor / Diodes)
• Possibility to create more than one logic gate (Inverter, etc)
– Large Scale Integration (LSI)
• Systems with at least 1000 logic gates (Several thousand transistors)
– Very Large Scale Integration
• Millions to hundreds of millions of transistors (Microprocessors)
– Intel indicates that dual core processors will soon exist that
contain 1 billion transistors
 Introduction
• Manual (Human) design can occur with small number of
transistors

• As number of transistors increase through SSI and VLSI,

the amount of evaluation and decision making would
become overwhelming (Trade-offs)

– Maintaining performance requirements (Power / Speed / Area)

– Design and implementation times become impractical

• How does one create a complex electronic consisting of

millions of transistors?

Automate the Process using Computer-Aided Design (CAD) Tools

 Introduction
• CAD tools provide several advantages
– Ability to evaluate complex conditions in which solving one
problem creates other problems
– Use analytical methods to assess the cost of a decision
– Use synthesis methods to help provide a solution
– Allows the process of proposing and analyzing solutions to occur
at the same time

• Electronic Design Automation

– Using CAD tools to create complex electronic designs (ECAD)
– Several companies who specialize in EDA
• Cadence® Design Systems
• Magma® Design Automation Inc.
• Synopsys®

CAD Tools Allow Large Problems to be Solved

Design Flow
Top Level Digital Design Flow

Design Inception

RTL Design

Synthesis Macro Development

Place + Route

Physical Verification

Design Complete
 RTL Design
Design Function Digital Tool

Design Inception Design Inception

Cadence NC Verilog
RTL Design
Mentor Graphis ModelSim

Lint Checking
Cadence Hal
(users digression)

FPGA Verification
Xilinx ISE
(users disgression)

Code Coverage
Cadence ICT
(users disgression)

Cadence NC Verilog
Testbench Developement
Mentor Graphics ModelSim

Mixed Mode Simulation Cadence AMS Designer

Formal Verification Cadence Conformal

Agilent ADS
System Interface Simulation
Synthesis Matlab

Synthesis + Macro Synthesis + Macro

Development Development
 Synthesis + Macro Development
Design Function Digital Tool

RTL RTL

Synopsys DC
Synthesis Macro Generation Artisan
Cadence RC

DFT Macro Verification Synopsys DFT Compiler

Mentor Graphics Calibre
Cadence RC

Macro Rules Generation

/ Artisan/
Static Timing Analysis Synopsys PrimeTime
Library Generation Cadence DFII

Logical Equivalency Cadence Conformal

Verification Verification

Cadence NC Verilog
Gate-Level Simulation
Mentor Graphics Modelsim

Place + Route Place + Route

 Place + Route
Design Function Digital Tool

Synthesis Synthesis

Floorplan

Macro Placement
/ Std Cell
Placement

Cadence Encounter
Placement-Based
Optimization

Clock Tree Synthesis

Static
Synopsys
Timing
Analysis Prime-
Time
Route
Cadence NanoRoute

Spare Cells/ Decoupling Mentor Graphics

ATPG Cap Filler Cells FastScan Cadence Encounter

RC Extraction
Cadence Fire
&Ice QX

Signal Integrity Cadence CeltIC/ Voltage

Storm

Metal Fill Cadence Encounter

Verification
Verification
 Physical Verification
Design Function Digital Tool

Placed + Routed Placed + Routed

Design Design

GDSII Preparation/
Simulation Preparation Cadence DFII Cadence DFII
Schematic Preparation

Layout / Chip Finishing Back Annotated Simulation Cadence Virtuoso Cadence NC Verilog

DRC

LVS Mentor Graphics Calibre

ERC

Synopsys Nanosim
Top-Level Simulation
Cadence AMS Designer

Design Complete Design Complete

Design Flow - Overview

• Generic VLSI Design Flow from System

Specification to Fabrication and Testing

• Steps prior to Circuit/Physical design are

part of the FRONT-END flow

• Physical Level Design is part of the BACK-

END flow
– Physical Design is also known as “Place and
Route”

• CAD tools are involved in all stages of VLSI

design flow
– Different tools can be used at different
stages due to EDA common data formats*

• Synopsys® CAD tool for Physical Design is

called Astro™
Front-End Design Flow
Synthesis using Design Compiler
Wireload model basics (1)
Wireload model basics (2)
Back-End Design Flow
Physical Level Design
using Synopsys®
What does Astro™ do?
Where does the Gate Level Netlist come from?
1st Input to Astro™
Standard Cell Library
2nd Input to Astro™

• Pre-designed collection of
logic functions
– OR, AND, XOR, etc

• Contains both Layout and

Abstract views
– Layout (CEL) contains drawn
mask layers required for
fabrication
– Abstract (FRAM) contains
only minimal data needed for
Astro™
– Timing information
• Cell Delay / Pin Capacitance
• Common height for
placement purposes
 Timing Constraints
3rd Input to Astro™

• Derived from system specifications and implementation of

design

• Identical to timing constraints used during logic synthesis

• Common constraints in electronic designs

– Clock Speed/Frequency
– Input / Output Delays associated with I/O signals
– Multicycle Paths
– False Paths

• Astro™ uses these constraints to consider timing during

each stage of the place and route process
 Concept of Place and Route

• Location of all standard cells is automatically chosen by the

tool during placement (Based upon routing and timing)

• Pins are physically connected during routing (Based upon

timing)
 Concepts of Placement

• Standard cells are placed in “placement rows”

• Cells in a timing-critical path are placed close together to reduce routing related
delays (Timing Driven)

• Placement rows can be abutting or non-abutting

 Concepts of Routing

• Connecting between metal layers

requires one or more “vias”

• Metal Layers have preferred routing

directions
– Metal 1 (Blue) Horizontal
– Metal 2 (Yellow) Vertical
– Metal 3 (Red) Horizontal
Design Setup
 Design Flow – Design Setup

• The three main inputs for Astro™ need to be combined into

a common database

• Design Setup needs to be completed prior to performing

place and route

• This environment (database) allows Astro™ to use both the

logical and physical information of the design

• Goal of Design Setup is to prepare design for Floorplanning

 Design Setup Step #1
Creating a Design Library
 Technology File

• Layer and via Definitions

• Process design rules (Minimum metal widths and spacing)

• Resistance / Capacitance parasitic models

• Units (Time / Capacitance / Distance)

• GUI display information (Colors and fill template for layers)

• This file is stored in the design library (Common Database)

 Design Setup Step #2
Attach Reference Libraries

• Reference libraries contain cells used by

many other designs

• They are referenced by pointers in the

design library for memory efficiency
Design Setup Step #3
Read Netlist
• Netlist is generated from logic synthesis
stage

• Netlist can be in several different formats

– Verilog
– VHDL
– EDIF (Electronic Design Interchange Format)

• Parsed for syntax errors and other errors

that may cause problems during physical
design
Design Setup Step #4
Expand Netlist

• Netlist must be flattened or “Expanded

• During this process, Astro™ verifies that an

“abstract” view is available for each leaf cell
(Reference Library Check)
Design Setup Step #5
Create Starting Cell

• UNIX structure for design library

• CEL directory will contain starting cell
(beginning point for place and route)
– CEL (Graphical)
– NETL (Netlist)
– EXP (Expanded)
 Design Setup Step #6
Bind Netlist to Cell

• Logical and physical representations are

merged into Starting Cell
 Design Setup Step #7
Preserve the Hierarchy
• After Place and Route, the design must be
functionally verified
– Goal of reusing existing test benches and
stimulus files

• Astro™ only operates on a flat design

– By default output netlist will be flat
– Test “probe” points on sub-block boundaries may
have been moved or removed, and the test bench
can not be reused

• Solution: Preserve the Hierarchy

– Astro™ can maintain the ports and function of the
ports at the hierarchical boundaries of the sub-
blocks.
– Astro™ can then operate on flat design and
reconstruct the hierarchy if needed
Floorplan
 Design Flow – Floorplan

• Layout design done at the chip level

– Defining layout hierarchy
– Estimation of required design area

• A blueprint showing the placement of major components in the

design (non-standard cell)
– Inputs / Output (I/O)
– RAMs / ROMs/
– Reusable Intellectual Property (IP) macros

• Approaches to Floorplanning (Automatic or Manual)

– Constructive
– Iterative
– Knowledge-Based
 Design Must Be Floorplanned Before P&R

• Floorplan of design:
– Core area defined with large macros placed
– Periphery area defined with I/O macros placed
– Power and Ground Grid (Rings and Straps) established
• Utilization:
– The percentage of the core that is used by placed standard cells and
macros
– Goal of 100%, typically 80-85%
I/O Placement and Chip Package
Requirements
• Some Bond Wire
requirements:

– No Crossing

– Minimum Spacing

– Maximum Angle

– Maximum Length
 Guidelines for a Good Floorplan

• A few quick iterations of place and route with timing checks

may reveal the need for a different floorplan
Defining the Power/Ground Grid and
Blockages

• Purpose of Grid is to
take the VDD and
VSS received from
the I/O area and
distribute it over the
core area
• Blockages can also
be added in the
floorplan to prohibit
standards cells from
being placed in those
areas
Timing Driven Placement
Design Flow – Timing Driven Placement
• Astro™ optimizes, places, and
routes the logic gates to meet
all timing constraints

• Balancing design requirements

– Timing
– Area
– Power
– Signal Integrity
Timing Constraints
• Astro™ needs constraints to
understand the timing
intentions
– Arrival time of inputs
– Required arrival time at outputs
– Clock period

• Constraints come from the

Logic Synthesis tool
– SDC (Synopsys Design
Constraints) format
 Cell and Net Delays

• Astro™ calculates delay for every cell and every net

• To calculate delays, Astro™ needs to know the

resistance and capacitance of each net
– Uses geometry of net and Look Up Tables to estimate the
resistances and capacitances
 Timing Sanity Check
• Prior to placement, Astro™ can check the design
timing constraints for feasibility

• The process is called a “Zero-Interconnect” check

• Astro™ performs timing analysis based upon design

constraints (SDC) and cell delay only, while ignoring
the RC delay

• If major timing violations exist, the problem will

probably get worse with the added RC delay (routing)

Zero-Interconnect Check Saves Time and Resources

Timing Driven Placement

• Timing Driven
Placement places
critical path cells close
together to reduce net
RC

• Prior to routing, RC
are based on Virtual
Routes

• What if critical paths

do not meet timing
constraints with
placement?
 Logic Optimizations

• These optimizations can be done during pre-place, in-place,

or post-place stages of placement

• Each optimization can be done separately or all done

concurrently during placement (none – one – all)
Clock Tree Synthesis
 Design Flow – Clock Tree Synthesis

• All clock pins are driven by a single clock source

• Large delay and transition time due to length of net

• Clock signal reach some registers before others (Skew)

 Clock Tree Topologies

• Clock source is connected to center of the network

• Networks are distributed in a H or X shape until clock

pin of register is driven by a local buffer

H-Tree and X-Tree Topologies Solve Single Clock Pin Problem

 After Clock Tree Synthesis

• A clock (buffer) tree is built to balance the output loads and

minimize the clock skew

• A delay line can be added to the network to meet the

minimum insertion delay (clock balancing)
 Gated - CTS

• Clocks may not be generated directly from I/O

• Power saving techniques such as clock-gating are used to

turn of the clock to sections of the design

• Astro™ can interpret gated clocks and can build clock trees
“through” the logic to the registers
Effects of CTS

• Several (Hundreds/Thousands)
of clock buffers added to the
design

• Placement / Routing congestion

may increase

• Non-clock cells may have been

moved to less ideal locations

• Timing violations can be

introduced
Routing
 Design Flow – Routing

• Routing is a fundamental step in the place and route

process

• Create metal shapes that meet the requirements of a

fabrication process
– The physical connection between cells in the design

• Virtual routes used during placement and CTS need to

become reality
– Timing of design needs to be preserved
– Timing data such as signal transitions and clock skew needs to
match the virtual route estimates

Process of Routing Can Be Timing Driven

 Timing Driven Routing

• Routing along the timing-critical path is given priority

– Creates shorter, faster connections

• Non-critical paths are routed around critical areas

– Reduces routing congestion problems for critical paths
– Does not adversely impact timing of non-critical paths
 Concept of Routing Tracks

• Metal routes must meet minimum width and spacing

“design rules” to prevent open and short circuits during
fabrication

• In grid based routing systems, these design rules

determine the minimum center-to-center distance for each
metal layer (Track/Grid spacing)

• Congestion occurs if there are more wires to be routed

than available tracks
 Grid-Based Routing System

• Metal traces (routes) are built

along and centered around
routing tracks

• Each metal layer has its own

tracks and preferred routing
direction
– Metal 1 – Horizontal
– Metal 2 – Vertical

• Track and pitch information can

be located in the technology file
– Design Rules
 Routing Operations

• Astro™ performs 4 stages during routing

– 1) Global Routing
– 2) Track Assignment
– 3) Detailed Routing
– 4) Search and Repair

• After stages 1-3, all clock/signal nets will

be completely routed and should meet all
timing and design rule (DRC) requirements

• Any remaining DRC violations can be fixed

by Search and Repair
 Global Routing

• First step in routing process

• Each net receives a broad routing plan determining how

the net will be routed in the design
– Determine open channels for routing

• Provides the background information for the next step of

Track Assignment

• Routing congestion is resolved

– If congestion is severe, extreme measures may be taken such as
moving large macros or re-floorplanning the design to relieve
congestion

Globally Connecting All Point A’s to All Point B’s

 Track Assignment

• Second step in routing

process

• Assigns each net to a

specific track and creates
the physical metal traces

• Attempts are made to

make long, straight
traces and to reduce the
numbers of vias

• Physical DRC rules are

not checked
 Detailed Routing

• Third step in routing process

• Attempts to clear DRC violations using a
fixed size Sbox
• All violations may not be fixed due to fixed
Sbox size
 Search and Repair

• Last step in routing process

• Fixes the remaining DRC violations through multiple

loops using a progressively larger Sbox size

• Design must have 0 DRC violations

– DRC rules for Astro™ are only a subset of the complete
technology DRC rules
– Must use Hercules™ for sign-off DRC check
Verification
What Happens After Place and Route?

Verification
 Formal Verification

• New standard cells have been added to the design

through timing optimizations and clock tree synthesis

• The final netlist created by Astro™ needs to be compared

to the original gate-level netlist

• Formal verification ensures the functional equivalency at

the logic level between the two implementations (original
vs. final) of the design
– The intended function was maintained throughout the physical
design process

Formality® is the Sign-Off Tool for Formal Verification

 Timing Verification
• Star-RCXT™ performs the layout parasitic extraction of
the resistances and capacitances of all routes in the
design

• Results in a format such as SPEF (Standard Parasitic

Extended Format)
– SPEF is an smaller, extended format of Standard Parasitic Format
(SPF), which enables the transfer of design specific resistances
and capacitances from physical design to timing analysis and
simulation tools

• Primetime® performs static timing analysis

– Detects timing violations by combining SPEF from Star-RCXT™
and netlist from Astro™ and checks against the design timing
constraints (clock frequencies)

Star-RCXT™ and Primetime®

are the Sign-Off Tools for Timing Verification
 Physical Verification
• Checks the design for fabrication feasibility and physical
defects that could result in the design to not function
properly
– 3 checks (DRC, ERC, and LVS)

• Design Rule Checks (DRC)

– Verifies that design does not violate any fabrication rules
associated with the target process technology (metal width/space,
antenna ratio, etc)

• Electrical Rules Checks (ERC)

– Verifies that there are no short or open circuits with power and
ground as well as resistors/capacitors/transistors with floating
nodes (part of LVS)

• Layout Versus Schematic (LVS)

– Final physical design matches the logical (schematic) version in
terms of correct connectivity and number of electrical devices

Hercules™ is the Sign-Off Tool for Physical Verification

 Fabrication

• Physical Design process is complete

upon successful completion of timing,
functional, and physical verification

• The design can be “Taped-Out” and

GDSII created for the manufacturer
– GDSII (Graphic Design System II) is a
binary format containing the physical
geometry information of the design.
– The shapes are assigned numeric
attributes in the form of “Layer Number”
and “Data Type” (Metal 1 => 100:0)

• Fabrication and Test determine

which chips can be implemented into
the system (yield)
 Future
• Technology continues to push the envelope with each new
process node
– Requirements of faster speeds, lower power and cost, and all within
the smallest area possible creates problems during physical design

• Challenges in physical design are dramatic at 130nm/90nm

– Voltage Drop, Crosstalk and Signal Integrity, Reliability
(Electromigration)
– PD tools can still be implemented to address these issues

• 65nm/45nm Concerns
– Leakage power of transistors could reach the level of the dynamic
power of the design
– Wiring delays outweighing gate delays (130nm and beyond)
– Cross coupling capacitance could begin to dominate over the
capacitance of the wire itself

• These challenges and concerns will force logic designers to

think physically and physical designers to think electrically
EDA Tool Advancement Needed for 45nm
 Conclusion

• Designing a sophisticated VLSI design is complicated

– Number of transistors combined with challenges at each processing
node

• Design time can be over 1 year from system conception to fabricated

chips

• No one person or design team could manually design and complete a

system in a time frame to be market competitive

Task of Designing, Placing,

Routing, and Fabricating Complex VLSI Designs
Must Become Automated
QUESTIONS ?