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The situation when two expressions are allowed to execute at same instance of time
without mentioning the order of execution
In logical shift the MSB will be accumulated by zero's , i.e vacant positions are
zero-filled.
In arithmetic right shift MSB will be accumulated by sign bit, i.e the vacant
positions are filled with the MSB/sign bit if the operand is signed.
Logical left shift (<<), arithmetic left shift (<<<) and logical shift right(>>)
operators, shift the bits left/right by the number of bit positions specified by the right
operand, and the vacated bits are filled with zeros. The arithmetic right shift operator
(>>>) will fill the vacated bits with 0 if the left operand is unsigned, and the most
significant bit if the left operand is signed.
Left Shift:
In this example, the reg result is assigned the binary value 0100, which is 0001
shifted to the left two positions and zero-?lled.
module sh;
reg [3:0] st, result;
initial begin
st = 1;
result = (st << 2);
end
endmodule
In this example, the reg result is assigned the binary value 1110, which is 1000
shifted to the right two positions and sign-?lled.
module shift;
reg signed [3:0] st, result;
initial begin
st = 4’b1000;
result = (st >>> 2);
end
endmodule
Inter delay simply wait for appropriate no of time steps before executing the
command.
ex : #10 q = x + y;
Intra delay wait for appropriate no of time steps before assignment of RHS to
LHS.
ex : q = #10 x + y;
A function shall execute in one simulation time unit; a task can contain time-
controlling statements like always@ etc .
A function cannot enable a task; a task can enable other tasks or functions.
A function shall have at least one input type argument and shall not have an
output or inout type argument ; a task can have zero or more arguments of any
type.
A function shall return a single value; a task shall not return a value.
module generate_ex2(out,in,select);
input En;
input [0:1] select;
output [0:3] out;
assign out = En? (1 << select) : 4’b0;
endmodule
What is alias?
Used only on nets to have a two-way assignment.
module top_alias ();
wire rhs,lhs;
alias lhs=rhs;
In the above verilog code, if LHS changes it reflects to RHS and similarly if RHS
changes it reflects to LHS as well.
Given only two xor gates one must function as buffer and another as
inverter?
Ans : Tie one of xor gates input to 1 it will act as inverter. Tie one of xor gates input
to 0 it will act as buffer.
What is slack?
'Slack' is the amount of time that is measured from when an event 'actually
happens' and when it must 'happen'.
Negative slack implies that the 'actually happen' time is later than the 'deadline'
time.
If two similar processors, one with a clock skew of 100ps and other with a
clock skew of 60ps. Which one will consume more power? Why?
Clock skew of 60ps is more likely to have clock power. Because it is likely that low-
skew processor has better designed clock tree withmore powerful and number of
buffers and overheads to make skew better.
How many 2 input xor's are needed to implement 16 input parity generator?
A:
Since the "a = 0" is an active event, it is scheduled into the 1st "queue".
The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue.
Finally, the display statement is placed into the 4th queue.
Only events in the active queue are completed this sim cycle, so the "a = 0"
happens, and then the display shows a = 0. If we were to look at the value of a in
the next sim cycle, it would show 1.
A:
10 30 50 70 90 110 130
___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___
a ___________________________________________________________
This obviously is not what we wanted, so to get closer, you could use
"always @ (posedge clk)" instead, and you'd get
10 30 50 70 90 110 130
___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___
___ ___
a _______________________| |___________________| |_______
reg clk;
reg a;
A:
10 30 50 70 90 110 130
___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___
(3)a __________________________________________________________
Since the #delay cancels future events when it activates, any delay over the actual
1/2 period time of the clk flatlines...
With changing a to a wire and using assign, we just accomplish the same thing...
10 30 50 70 90 110 130
___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___
(6)a __________________________________________________________
- If you note, for all possible combinations of “sel”, there is a match in the case
statement. Say if there was no default in the case statement, then when “sel”
takes a value 2’b11, then it is “not-ful” case statement. The previous value of
“sel” will be held, there by inferring a latch during synthesis.
If you notice, each of the 3 cases are unique, in the sense, there can be only one
possible match out of the 3 for “irq” . The 3 case conditions are independent of each
other. This is called “parallel- case”
casez (irq)
3'b1??: int2 = 1'b1;
3'b?1?: int1 = 1'b1;
3'b??1: int0 = 1'b1;
endcase
If the 3-bit irq bus is 3'b011, 3'b101, 3'b110 or 3'b111, more than one case item
could potentially match the irq value. This will simulate like a priority encoder where
irq[2] has priority over irq[1], which has priority over irq[0]. This example will also
infer a priority encoder when synthesized
This is an “overlap-case” statement.
Behavioral coding describe the design in algorithmic way that is the functionality is
defined by which operation must occur not by how they are implemented in
hardware.