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Race Conditions

The situation when two expressions are allowed to execute at same instance of time
without mentioning the order of execution

Difference between logical and arithmetic shift

In logical shift the MSB will be accumulated by zero's , i.e vacant positions are
zero-filled.

In arithmetic right shift MSB will be accumulated by sign bit, i.e the vacant
positions are filled with the MSB/sign bit if the operand is signed.

Logical left shift (<<), arithmetic left shift (<<<) and logical shift right(>>)
operators, shift the bits left/right by the number of bit positions specified by the right
operand, and the vacated bits are filled with zeros. The arithmetic right shift operator
(>>>) will fill the vacated bits with 0 if the left operand is unsigned, and the most
significant bit if the left operand is signed.

Left Shift:

In this example, the reg result is assigned the binary value 0100, which is 0001
shifted to the left two positions and zero-?lled.

module sh;
reg [3:0] st, result;
initial begin
st = 1;
result = (st << 2);
end
endmodule

Arithmetic Right Shift :

In this example, the reg result is assigned the binary value 1110, which is 1000
shifted to the right two positions and sign-?lled.

module shift;
reg signed [3:0] st, result;
initial begin
st = 4’b1000;
result = (st >>> 2);
end
endmodule

What is the difference between “wire” and “reg” datatypes


The main difference between wire and reg is, wire cannot hold (store) the value
when there no connection between a and b like a->b, if there is no connection in a
and b, wire loose value. But reg can hold the value even if there in no connection.
Default values:wire is Z,reg is x.

What exactly expression reg[8*13:1] string_val; signifies?


Reg can hold up to 13 characters.

Difference between inter delay and intra delay?

Inter delay simply wait for appropriate no of time steps before executing the
command.
ex : #10 q = x + y;
Intra delay wait for appropriate no of time steps before assignment of RHS to
LHS.
ex : q = #10 x + y;

Task and Function

 A function shall execute in one simulation time unit; a task can contain time-
controlling statements like always@ etc .

 A function cannot enable a task; a task can enable other tasks or functions.

 A function shall have at least one input type argument and shall not have an
output or inout type argument ; a task can have zero or more arguments of any
type.

 A function shall return a single value; a task shall not return a value.

Difference between always and always@


The only difference is always@ can be synthesized but not other one.
The always without @ will be used only in test benches.

Difference between $display and $monitor


$display display its parameter whenever that is executed.
$monitor display its parameter whenever the value of parameter changes.
$strobe: display only at the end of the current simulation time

Verilog code to Divide the clock by 2


always @ (posedge clk_in)
if (reset)
clk_out <= 1'b0;
else
clk_out <= ! clk_out ;

Verilog code for Binary to Gray Code

assign out = {( binary[3]),(binary[3] ^ binary[2]), (binary[2] ^ binary[1]),


(binary[1]^binary[0]) };

Verilog code for one hot encoder


always @ (posedge clk)
if (reset)
out <= 8'b0000_0001 ;
else if (enable)
out <= {out[7], out[6], out[5], out[4], out[3], out[2], out[1], out[0] };

Verilog code for Parity Checker

assign parity_out = ^data_in; // data_in is 8 bits

Verilog for 8-bit left shifter

always @(posedge Clock)


begin
register <= register << 1;
register[0] <= Input;
end
assign output = register[7];

What is the synthesized hardware for the verilog code below?

module generator_ex1(data, select, out);


input [0:7] data;
input [0:2] select;
output out;
assign out = data [select];
endmodule

Ans: 8:1 Mux

module generate_ex2(out,in,select);
input En;
input [0:1] select;
output [0:3] out;
assign out = En? (1 << select) : 4’b0;
endmodule

Ans: 2:4 Decoder

Verilog code for D-Flip Flop with gated clock

D type flip flop with gated clock


reg q;
wire gtd_clk = enable && clk;
always @ (posedge gtd_clk)
q <= d;

What is alias?
Used only on nets to have a two-way assignment.
module top_alias ();
wire rhs,lhs;
alias lhs=rhs;

In the above verilog code, if LHS changes it reflects to RHS and similarly if RHS
changes it reflects to LHS as well.

What is the difference between: c = con ? a : b; and if (con) c = a; else c =


b;
The operator (?) gives answers even if the condition is "x",
so for example if con = 1'bx, a = 'b10, and b = 'b11, it will give c = 'b1x.
Whereas“if” treats Xs or Zs as FALSE, so it will return always c = b.

How are memories declared?


Memories are declared as two-dimensional arrays of registers.
syntax:
reg [msb:lsb] identifier [first_addr:last_addr] ;

Inverter using ONLY NAND

NOR using ONLY NAND

XOR using ONLY NAND

casez Vs casex Vs case


casez treats all z as "Don't care".
casex treat all z or x as "Don't care".
case pass all z or x to the result.

Given only two xor gates one must function as buffer and another as
inverter?
Ans : Tie one of xor gates input to 1 it will act as inverter. Tie one of xor gates input
to 0 it will act as buffer.

How to fix the setup and hold violation?


Setup violation can be fixed by slow down the clock.
By inserting buffer in the path we can reduce the hold violations.

What is slack?
'Slack' is the amount of time that is measured from when an event 'actually
happens' and when it must 'happen'.

Negative slack implies that the 'actually happen' time is later than the 'deadline'
time.

4- input NAND gate using 2-input NAND gates

If two similar processors, one with a clock skew of 100ps and other with a
clock skew of 60ps. Which one will consume more power? Why?

Clock skew of 60ps is more likely to have clock power. Because it is likely that low-
skew processor has better designed clock tree withmore powerful and number of
buffers and overheads to make skew better.

How many 2 input xor's are needed to implement 16 input parity generator?

It is always n-1, where n is number of inputs. So 16 input parity generator will


require 15 two input xor's.
Q: Given the following Verilog code, what value of "a" is displayed?

always @(clk) begin


a = 0;
a <= 1;
$display(a);
end

A:

This is a tricky one! Verilog scheduling semantics basically imply a


four-level deep queue for the current simulation time:

1: Active Events (blocking statements)


2: Inactive Events (#0 delays, etc)
3: Non-Blocking Assign Updates (non-blocking statements)
4: Monitor Events ($display, $monitor, etc).

Since the "a = 0" is an active event, it is scheduled into the 1st "queue".
The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue.
Finally, the display statement is placed into the 4th queue.

Only events in the active queue are completed this sim cycle, so the "a = 0"
happens, and then the display shows a = 0. If we were to look at the value of a in
the next sim cycle, it would show 1.

Q: Given the following snipet of Verilog code,

draw out the waveforms for clk and a

always @(clk) begin


a = 0;
#5 a = 1;
end

A:

10 30 50 70 90 110 130
___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___

a ___________________________________________________________
This obviously is not what we wanted, so to get closer, you could use
"always @ (posedge clk)" instead, and you'd get

10 30 50 70 90 110 130
___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___

___ ___
a _______________________| |___________________| |_______

Using the given, draw the waveforms for the following

versions of a (each version is separate, i.e. not in the same run):

reg clk;
reg a;

always #10 clk = ~clk;

(1) always @(clk) a = #5 clk;


(2) always @(clk) a = #10 clk;
(3) always @(clk) a = #15 clk;

Now, change a to wire, and draw for:

(4) assign #5 a = clk;


(5) assign #10 a = clk;
(6) assign #15 a = clk;

A:

10 30 50 70 90 110 130
___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___

___ ___ ___ ___ ___ ___ ___


(1)a ____| |___| |___| |___| |___| |___| |___| |_

___ ___ ___ ___ ___ ___ ___


(2)a ______| |___| |___| |___| |___| |___| |___|

(3)a __________________________________________________________

Since the #delay cancels future events when it activates, any delay over the actual
1/2 period time of the clk flatlines...
With changing a to a wire and using assign, we just accomplish the same thing...

10 30 50 70 90 110 130
___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___

___ ___ ___ ___ ___ ___ ___


(4)a ____| |___| |___| |___| |___| |___| |___| |_

___ ___ ___ ___ ___ ___ ___


(5)a ______| |___| |___| |___| |___| |___| |___|

(6)a __________________________________________________________

What is difference between Verilog full case and parallel case?

A "full" case statement is a case statement in which all possible case-expression


binary patterns can be matched to a case item or to a case default. If a case
statement does not include a case default and if it is possible to find a binary case
expression that does not match any of the defined case items, the case statement is
not "full."

module mux3c (y, a, b, c, sel);


output y;
input [1:0] sel;
input a, b, c;
reg y;
always @(a or b or c or sel)
case (sel)
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
default: y = 1'bx;
endcase

- If you note, for all possible combinations of “sel”, there is a match in the case
statement. Say if there was no default in the case statement, then when “sel”
takes a value 2’b11, then it is “not-ful” case statement. The previous value of
“sel” will be held, there by inferring a latch during synthesis.

A "parallel" case statement is a case statement in which it is only possible to match a


case expression to one and only one case item. If it is possible to find a case
expression that would match more than one case item, the matching case items are
called "overlapping" case items and the case statement is not "parallel."

always @(irq) begin


{int2, int1, int0} = 3'b0;
casez (irq)
3'b1??: int2 = 1'b1;
3'b01?: int1 = 1'b1;
3'b001: int0 = 1'b1;
endcase
end

If you notice, each of the 3 cases are unique, in the sense, there can be only one
possible match out of the 3 for “irq” . The 3 case conditions are independent of each
other. This is called “parallel- case”

casez (irq)
3'b1??: int2 = 1'b1;
3'b?1?: int1 = 1'b1;
3'b??1: int0 = 1'b1;
endcase

If the 3-bit irq bus is 3'b011, 3'b101, 3'b110 or 3'b111, more than one case item
could potentially match the irq value. This will simulate like a priority encoder where
irq[2] has priority over irq[1], which has priority over irq[0]. This example will also
infer a priority encoder when synthesized
This is an “overlap-case” statement.

Difference between Behavioral and RTL Modeling

RTL coding is describing the system in terms of expressions,clocks and registers,


manually binding operation to specific clock periods.So everything is about how data
transfer takes place between registers WRT clocks.

Behavioral coding describe the design in algorithmic way that is the functionality is
defined by which operation must occur not by how they are implemented in
hardware.

Timing conditions when there is a feedback path in the circuit:

t_clock_high <= T_prop


t_clock_low >= T_setup
T_hold <= T_prop

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