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CSET 4650
Field Programmable Logic Devices
Dan Solarek
Objectives
2
Some Basics
usually flip-flops
SR, JK, D, T
4
Some Basics
?
0 1 0 0 1
0 1 0 1 1
0 1 1 0 x
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 x
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
function
truth table
6
Logic Circuit Implementation
Memory
7
Logic Circuit Implementation
U19-251641-02
PLA
Programmable Devices
8
Electronic Components
Logic
Standard
ASIC
Logic
Programmable
Logic Devices Gate Cell-Based Full Custom
(PLDs) Arrays ICs ICs
SPLDs
(PALs) CPLDs FPGAs
SRAM - volatile
10
Programmable ROM (PROM)
11
UV EPROM
Erasable PROM
Common technologies used UV light to
erase complete device
Took about 10 minutes
Holds state as charge in very well insulated
areas of the chip
Nonvolatile for several (10?) years
12
EEPROM
13
Details of ROM
14
Simple PLDs
15
Programmable Logic Device
16
Programmable Array Logic (PAL)
17
Early PALs
19
Early PALs
20
Early PALs
22
Programmable Electrically
Erasable Logic (PEEL)
23
Complex Programmable
Logic Devices (CPLDs)
24
Complex PLDs
25
Complex PLDs
27
Field Programmable Logic
Devices (FPGAs)
28
Field Programmable Logic
Devices (FPGAs)
30
Field Programmable Logic
Devices (FPGAs)
31
Field Programmable Logic
Devices (FPGAs)
32
PLD Device Density and VLSI
Technology
Year 1995 1996 1997 2000 2003 2004 ?
100K LC*
8Mb RAM
Gate Count 25K 100K 250K 1M
400 18X18
multipliers
Transistor
3.5M 12M 23M 75M 430M 1B
Count
34
How PLDs Remember Their
Configuration
35
How PLDs Remember Their
Configuration - Antifuses
37
How PLDs Remember Their
Configuration - Flash
38
How PLDs Remember Their
Configuration - EPROM
40
Hardware Description Languages
41
Programmable Logic Solutions
42