ECE 327 Digital Computer Design

Section 1 (3 credit hrs)

Spring 2011
General Information

Instructor: Dr. Melissa C. Smith (smithmc@clemson.edu)

100-G Riggs Hall, (864) 656-2119
Office hours: Times TBD or by appointment
Lecture: MWF 9:05 AM-9:55 PM, Riggs 226
Course webpage: http://bb.clemson.edu
Prerequisites: ECE 272
Required Text: Fundamentals of Digital Liogic with VHDL Design
By: Stephen Brown and Zvonko Vranesic,

Course Objectives

Understand modern design methodologies (CAD and HDL)

Understand design for FPGA devices
Understand design of control and timing circuitry
Understand design of high-speed ALUs

Grading

1st Exam: 20%

2nd Exam: 20%
Assignments and Projects: 40%
Final Exam: 20%
Grades will be based on the following percentages:
A – 90 and above
B – 80 to 89
C – 70 to 79
D – 60 to 69
F – 59 and below

Policies

Students may leave after 10 minutes if the professor or guest lecturer does not arrive in that time.
Attendance is required. Students are responsible for getting lecture notes, handouts, and homework
assignments for missed classes from fellow students or from the class website when applicable.
Homework is due on the day and time specified in the assignment instructions; late assignments
will not be accepted. Zeros will be given for missed in-class graded activities. Make-ups for graded
activities and homework assignments are possible only with a valid, written, medical or university
excuse. It is the student’s responsibility to give the professor the written excuse and to arrange for
any makeup work to be done before the exam for that unit is taken. All makeup exams will be given
on the last day of the semester, by prior appointment only. Students are expected to complete all
assignments independently unless the instructor specifies team collaboration is permitted.
It is recommended that students check their email and blackboard daily for important
announcements, assignments, and other class related information. It is preferred that you use your
clemson.edu account and not forward to another account (e.g. hotmail, yahoo, etc.) as there is the
potential for lost information with these systems.

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Disability Services

Students with disabilities who need accommodations should make an appointment with me to
discuss specific needs within the first month of classes. Students should present a Faculty
Accommodation Letter from Student Disabilities Services when we meet. Student Disability
Services is located in G-20 Redfern (phone number: 656-6848, email: sds-l@clemson.edu). Please
be aware that accommodations are not retroactive and new FAL must be presented each semester.

Academic Integrity

This course follows Clemson University procedures. Students suspected of violating academic
integrity will be reported. All work on quizzes, tests, exams, design assignments, projects, and labs
is to be wholly your own unless otherwise instructed. Possessing, using, providing, or exchanging
improperly acquired written, verbal, or electronic information will be considered a violation of the
academic honor code. Violations will result in a grade of F for the semester.

The official statement of Clemson University on Academic Integrity:

“As members of the Clemson University community, we have inherited Thomas

Green Clemson’s vision of this institution as a “high seminary of learning.”
Fundamental to this vision is a mutual commitment to truthfulness, honor, and
responsibility, without which we cannot earn the trust and respect of others.
Furthermore, we recognize that academic dishonesty detracts from the value of a
Clemson degree. Therefore, we shall not tolerate lying, cheating, or stealing in any
form.”

Course Topic List

• Introduction to CAD tools and simulation (~1 week)

1. CAD workflow
2. Technologies
3. Simulation
1. Logic vs. electrical simulation
2. Time vs. event simulation
3. Special problems in simulation
4. Schematic capture vs. HDLs
• VHDL Introduction (1 to 2 weeks)
1. Entity, architecture, process
2. Signals, nets, variables
3. Concurrent statements
5. Testbenches
• Device Technologies (~1 week)
1. ROM, PLA, PAL
2. CPLDs, FPGAs
3. Xilinx SpartanXL
4. Xlinix Virtex II
5. CMOS logic
6. Standard cell designs
7. Board level designs
• Synchronous Sequential Design (5 weeks)
o State Machines
1. More and Mealy Models
2. Algorithmic state machines
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 3. Regular language recognizers
4. VHDL specification
o Register Transfer Level Design
o ALU Design
1. Shift-add multipliers
2. Bit-pair recoding
3. Restoring and non-restoring division
4. Array multipliers
5. General arithmetic logic units
o Design for FPGAs
• Floating Point (2 weeks)
1. Formats
2. Addition/Subtraction
3. Multiplication
4. Hardware organization
5. Rounding, special values
• Asynchronous Sequential Design (2 weeks)
1. Fundamental mode circuit analysis
2. Synthesis from flow tables
3. Asynchronous state diagram and primitive flow tables
4. State reduction
5. State assignment
6. Races and hazards
7. VHDL specification
• Logic Minimization (1 week)
1. Quine-McClusky tabular method
• Circuit Testing (1 week)
1. Faults
2. Test sets
3. Random Testing
4. Controllability and Observability
5. Design for testability
1. LFSR, test generator, signature checking
2. Scan-path design
3. BILIBOs
4. JTAG

* The above schedule, policies, procedures, and assignments in this course are subject to change
in the event of extenuating circumstances, by mutual agreement, and/or to ensure better student
learning.

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Academic Honesty:

All work on quizzes, tests, design assignments, and labs is to be wholly your own.
Possessing, using, providing, or exchanging improperly acquired written, verbal, or
electronic information will be considered a violation of the academic honest policy.

Violations will result in a grade of F for the semester.

Examples of academic honest violations include, but are not limited to:
– Possessing, using, or exchanging similar projects from previous semesters
– Collaborating on individual assignments
– Multiple groups collaborating on group projects

I have read and understood the above stated academic honesty policy. I accept that
any form of academic dishonesty, as described above, will result in a minimum
punishment of a grade of F in the course.

Name: ________________________________________

Date: _________________________

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