Professional Documents
Culture Documents
CP
2 Q’
4
5
Y
S S S Q
Master Slave
Y’
R R R Q’
CP
MASTER-SLAVE FLIP-FLOP
Flip-Flop on RT54SX-A
(Not hardened)
Master Slave
RT54SX-A SEU Performance
10-6
October, 2000
Flip-Flop String
Flip-Flop String w/ Buffers
Cross-section (cm2/flip-flop)
10-7
Notes:
1. S/N LAN4001
10-8 2. Ions = 210 MeV Cl-35, 284 MeV Br-81, 345 MeV I-127
3. Fluence ~ 107 ions/cm2
4. Bias = 4.5, 2.25 VDC
5. Checkerboard pattern
6. Frequency = 1 MHz
7. 200 flip-flops / string
8. Regular CLK Buffer
10-9
0 10 20 30 40 50 60
2
LET (MeV-cm /mg)
RT54SX-S Latch
(SEU Hardened)
AFB
D B ANQ A Y A A Y A
Y A A
A B Y
S B
C C
BFB
B BNQ A Y B A Y
B A A
Y
A S B B Y A Y
C
C
CFB
B CNQ A Y C A Y C A A
Y
A B Y
S B
C C
G
Flip-Flop Timing: RT54SX-S
Fclock and Fdata are the frequency of the synchronizing clock and
asynchronous data.
• Software is available to automate the calculations with
built-in tables of parameters.
• Not all manufacturers provide data.
Metastability - Sample Data
Sample Metastable Time Data
CX2001 Technology
50 MHz clock, 10 MHz data rate
25
20
15
log10 (MTBF (years))
10
-5
-10
Note: Each flip-flop has its own K1, K2 parameters.
-15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VCC
D Q D Q
DFC1B DF1
EVENT CLK
CLR
CLK
SYSRESET B AND 2A
Y
A
SYSCLK
Metastable State:
Possible Output from a Flip-flop
CLK
Metastable
Q
Metastable State:
Possible Outputs from a Flip-flop
CLK
Q Correct Output
Q
Parallel Registers
D Q Q[3:0]
DATA [ 3 : 0 ]
DF1
CLOCK CLK
4-Bit Parallel Register
D Q
DF1
CLK
D Q
DF1
CLK
D Q
DF1
CLK
D Q Q[3:0]
4-Bit Register With Enable
DATA [ 3 : 0 ]
DF1
CLOCK CLK
D Q
DF1
CLK
D Q
DF1
CLK
D Q
DF1
CLK
Register Files (Simplified)
Register 2
Q
D
Register 1
CLK
Register
Decoder
(AND plane)
Memory BC BC BC
D1 Word 1
Address
inputs BC BC BC
Decoder D2 Word 2
(AND plane)
BC BC BC
Word3
D3
Memory BC BC BC
enable
Read/write
OR plane
Data
outputs
Rad-Hard PROM Architecture
CE
OE Control Logic I/O Buffers
VPP*
DQ0 - 7
No latches in this architecture
W28C64 EEPROM
Simplified Block Diagram
E2
Row Row Memory
A6-12 Address Address Array
Latches Decoder
CE* Edge
Detect & Timer
WE* Latches