Effects of process variation in VLSI

interconnects – a technical review

K.G. Verma
Shobhit University, Meerut, India
B.K. Kaushik
Department of Electronics & Electrical Engineering, G.B. Pant Engineering College, Pauri Garhwal, India, and
R. Singh
Shobhit University, Meerut, India

Abstract
Purpose – Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The purpose of
this paper is to provide a comprehensive overview of types and sources of all aspects of interconnect process variations.
Design/methodology/approach – The impacts of these interconnect process variations on circuit delay and cross-talk noises along with the two
major sources of delays – parametric delay variations and global interconnect delays – have been discussed.
Findings – Parametric delay evaluation under process variation method avoids multiple parasitic extractions and multiple delay evaluations as is done
in the traditional response surface method. This results in significant speedup. Furthermore, both systematic and random process variations have been
contemplated. The systematic variations need to be experimentally modeled and calibrated while the random variations are inherent fluctuations in
process parameters due to any reason in manufacturing and hence are non-deterministic.
Originality/value – This paper usefully reviews process variation effects on very large-scale integration (VLSI) interconnect.

Keywords Integrated circuit technology, Operations and production management

Paper type Technical paper

1. Introduction the design stage, which ultimately translates to a parametric

The performance of very large-scale integration (VLSI)/ultra
large-scale integration density (ULSI) chip is becoming less
predictable as device dimensions shrink below the sub-
100 nm scale. The reduced predictability can be attributed to
poor control of the physical features of devices and
interconnects during the manufacturing process. Variations
in these quantities result in variations in the electrical behavior
of circuits. These variations have interdie and intradie
components, as well as layout pattern dependencies. The
device material variations in geometry (tox, Leff , W), and
variations in doping levels and profiles have a direct impact on
the behavior of a metal-oxide semiconductor field-effect
transistor (MOSFET). Variations in the line width affect the
resistance and the interlayer capacitance. Variations in
the interwire spacing may cause a significant degradation in
the signal integrity. Layout pattern dependent variations
within the interlayer oxide and the chip multiprocessing
process also have a significant impact on the interconnect
parasitics. The disparate sources of variations in the IC
fabrication process lead to both random and systematic effects
on circuit performance. All of these make it increasingly
difficult to accurately predict the performance of a circuit at
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Microelectronics International
26/3 (2009) 49– 55
q Emerald Group Publishing Limited [ISSN 1356-5362]
[DOI 10.1108/13565360910981562]
yield loss. Due to the high complexity of design and the
presence of a large number of correlated parameters that
exhibit significant variations within a chip and between chips,
fast and efficient methods are needed to compute an accurate
statistical description of the response.
Process variations are not completely random. It can be
divided into deterministic part and nondeterministic part.
Random variations are inherent fluctuations in process
parameters such as dopant fluctuations from wafer to wafer,
lot to lot. On the other hand, systematic variations depend on
the layout pattern and are therefore predictable for the
systematic part, the variations need to be experimentally
modeled and calibrated, in order to either compensate hiring
the design phase or captured in the analysis phase. These
effects, which include optical proximity correction (OPC),
residual error and chemical mechanical planarization (CMP)
dishing (Orshansky et al., 2000) have a substantial but
deterministic impact on the critical dimension (CD) of a
transistor gate or the width and thickness of an interconnect
wire. By accounting for systematic part of process variation in
timing analysis, uncertainty can be reduced, thereby achieving
closer bound for circuit performance. With the shrinking
feature size in VLSI technology, the impact of process
variation is increasingly felt. To address the effect, great
amount of research has been done recently, such as the clock
skew analysis under process variation (Liu et al., 2000;
Mehrotra et al., 2000; Malavasi et al. 2002), statistical
performance analysis (Brawhear et al., 1994; Chang and
Sapatnekar, 2003; Agarwal et al., 2003) worst case
performance analysis (Orshansky et al., 2000; Acar et al.,
2001), parametric yield estimation (Borkar et al., 2003),

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 Effects of process variation in VLSI interconnects
K.G. Verma, B.K. Kaushik and R. Singh
impact analysis on micro architecture (Borkar et al., 2003)
and delay fault (Gattiker et al., 2001) test under process
variation (Luong and Walker 1996; Liou et al., 2002; Krstic
et al., 2003; Lu et al., 2004a). Since the width, thickness and
spacing of interconnects are each scaled by 1/a
(scaling factor), cross-section areas must scale by 1/a2. The
length of short distance interconnections is scaled by 1/a, so
that resistance is increased by a. With decreasing device
dimensions, we see increase in the levels of integration and
consequent increase in die size. This lengthens the
interconnections from one side of the chip to the other end
and, therefore, both resistance and capacitance of
interconnects are increased, producing much larger time
constants. Thus, the effects of increased propagation delays,
signal decay, and clock skew will reduce the maximum
achievable operating frequency, even though the smaller
transistors produce gates with less delay. One solution to this
problem has been to make use of multilayer interconnections
with thicker, wider conductors and thicker separating layers.
Other method is to use cascaded drivers and repeaters to
reduce the effects of long interconnect. A further option is to
use optical interconnection techniques where a very high level
of interconnection methodology is required (Fabbro et al.,
1995).
Figure 1 shows a typical interconnect geometry in a custom
design layout (Liu et al., 2000). Interconnects on adjacent
layers are orthogonal to each other, which is a special case of
the general configuration. The top interconnect has larger
width and smaller length compared to lower interconnects.
The capacitance at any metal line or node consists of the
following three components:
1 overlap capacitance Cov due to the overlap between two
interconnects in different metal layers;
2 lateral capacitance C lat between two intra-layer
interconnects; and
3 fringe capacitance Cfr between two interconnects in
different metal layers; this fringe capacitance is between
the sidewall of one interconnect and the top (or bottom)
of another interconnects in a different layer (Pucknell and
Eshraghian, 1988).
2. Nanometer process variation
As the technology reaches deep submicron or nanometer
regime, the errors due process variations becomes prominent.
The errors are briefly enumerated as follows.
Figure 1 Schematic of a typical interconnect structure
Cfr4
Cfr3 Cfr1
Cfr2
Cov2 Clat
Cov1 Cfr5
Source: Pucknell and Eshraghian (1988)
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Errors in deep-submicron (DSM):
The number of transient errors is expected to increase in
future technology generations:
.
Interconnects will be longer.
.
Smaller feature size brings new error sources (like
radiation).
.
The physical implementation of circuits and interconnects
is expected to function erroneously from time to time.
.
Designs cannot be considered nearly 100 per cent reliable
anymore.
Sources of DSM errors:
.
cross-talk;
.
electro-magnetic interference;
.
radiation;
.
process variations; and
.
other.
Given the perspective of different categories of variation, we
can now briefly survey some of the specific process variations
typically of concern in evaluating devices and interconnect in
integrated circuit design.
2.1 Device geometry variations
The first set of process variations of concern relate to the
physical geometric structure of MOSFET and other devices
(resistors and capacitors) in the circuit. These typically
include.
Film thickness variations. The gate oxide thickness is a
critical but usually relatively well controlled parameter.
Variation tends to occur primarily from one wafer to
another with good across wafer and across die control.
Other intermediate process thickness variations (e.g. poly or
spacer thickness) can impact channel length, but are rarely
directly modeled.
Lateral dimension variations. Lateral dimensions (length and
width) typically arise due to photolithography proximity
effects (a systematic pattern dependency), mask, lens, or
photo system deviations (a repeated die dependent variation,
though not directly a function of the layout density or other
layout parameters); or plasma etch dependencies (which can
have both wafer scale etch rate dependencies, as well as layout
density, aspect ratio, or other dependencies). MOSFETS are
well known to be particularly sensitive to effective channel
length (and thus to poly gate length and spacer width), as well
as gate oxide thickness and to some degree the channel width.
Of these, channel length variation often is singled out for
particular attention. This is due to the fact that such
variations have direct impact on device output current
characteristics (Yu et al., 1996).
2.2 Device material parameter variations
The device material variations are also prominent sources of
variations. The variations can be accounted for doping,
deposition and anneal variations.
Doping variations. Deviations arising due to dose, energy,
angle, or other ion implant dependencies can affect junction
depth and dopant profiles (and thus may also impact effective
channel length), as well as affect other electrical parameters
such as threshold voltage. Variations in thermal anneal and
gate doping can also change the degree of gate depletion in an
active device, and cause variation in the effective gate oxide
thickness. Depending on the gate technology used,
these deviations can lead to some loss in the matching of
 Effects of process variation in VLSI interconnects
K.G. Verma, B.K. Kaushik and R. Singh
Negative-Channel Metal Oxide Semiconductor (NMOS)
versus Positive-Channel Metal Oxide Semiconductor
(PMOS) devices even in the case where within wafer and
within die variation is very small.
Deposition and anneal. Additional material parameter
deviations are observed in silicide formation, and in the
grain structure of poly or metal lines. These variations may
depend on the deposition and anneal processes. These
material parameter deviations can contribute to appreciable
contact and line resistance variation.
2.3 Device electrical parameter variations
In many cases, the underlying geometry distribution is not
characterized, but instead the key electrical parameters are
directly extracted and modeled for device electrical parameter
variations.
Vt variation. A key concern is threshold voltage (Vt)
variation. Threshold voltage of a MOSFET varies due to:
.
Changes in oxide thickness.
.
Substrate, polysilicon and implant impurity level.
.
Surface charge.
Process variation may increase or decrease the aspect ratio
(W/L). Variation in W and L is caused by lithographic process.
These variation are not correlated because W is determined in
the field oxide step while L is defined in the polysilicon and
source/drain diffusion steps. While many elements of Vt may
be due to oxide thickness or other geometric deviations,
additional sources of variation are often encountered. In
particular, mobile charge in the gate oxide can introduce a
bias dependent variation; this is sometimes approximated as
being about 10 percent of the Vt of the smallest device in a
given technology. Another source of Vt variation that is just
beginning to become important in static random access
memory (SRAM) and other circuits related to random dopant
fluctuations. In particular, as scaling of metal-oxide
semiconductor (MOS) devices continues into the deep
submicron regime, concern has been raised about the
random placement and concentration fluctuations due to
discrete location of dopant atoms in the channel and source/
drain regions.
Leakage currents. Sub threshold leakage currents may vary
substantially, and can be affected by shallow trench isolation
structure and stress (Boning and Nassif, 2000).
3. Interconnect characterization
Owing to the process variation, interconnect technology
parameters (ITP) are varying substantially. For simplicity, the
researchers consider variations in metal width (W), metal
thickness (T), and inter-layer dielectric (ILD) thickness (H).
The typical distribution of ITP can be observed for
permittivity, ILD thickness, metal height and metal width
(Figure 2) (Boning and Nassif, 2000). The variation is
especially large in the ILD thickness and metal line width.
Their variations have a definite impact to the total line
capacitance and interline coupling capacitance and result in
variation of the signal delay and cross-talk noise. The effect of
the process variation should be modeled, because its impact
on the signal delay and cross-talk is substantial. The
conventional skew corner worst-case modeling is too
conservative (Boning and Nassif, 2000).
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4. On-chip interconnect variations
The source for on-chip variations (OCV) is related to
variation in interconnects height and width, resulting in
variation in both resistance and capacitance. Since the delays
attributed to interconnect are becoming more dominant as
geometries shrink, particular attention should be paid to
accurate modeling of interconnect variations. In advanced
interconnect processes, which could involve use of multiple
dielectrics, use of different metallization on different layers
could result in significant variations. Depending on material
properties of low-k dielectrics, “dishing” could be observed
on metal lines spaced wide apart. Erosion is the other
mechanism and is a function of line space and density.
Examples are shown in Figure 3.
Two additional sources of variation are the CMP process
and proximity effects in the photolithography and etch
processes. Variation in the CMP process results from the
difference of hardness of the interconnect material and that of
the dielectric. Ideally the CMP process will remove the
unwanted copper, leaving only lines and vias. The
photolithography and etch proximity effects are shown in
micro loading effects as the etch process step tends to over-
etch isolated lines. Diffraction effects and local scattering in
photolithography may tend to over expose densely spaced
lines and under expose isolated lines. Tiling and metal slotting
have been added as design rule requirements to mitigate these
effects by minimizing the density gradient. Different tiling
algorithms will give varying results, but the smaller the density
gradient, the smaller the variations that will be seen on the die
(Jarrar and Taylor, 2006).
4.1 Cross-talk noise
Cross-talk noise is the main source of noise in static
complementary metal-oxide semiconductor (CMOS)
designs (Nagaraj et al., 2001; Narasimha et al., 2006; and
Demircan, 2006). The cross-talk noise increases the signal
settling time. Among several factors that affect the cross-talk
noise, key factors include aggressor/victim drive strengths,
parasitic resistance, inductance, capacitance (RLC) of the
interconnect network, aggressor signal switching times,
transistor device models and victim receiver noise margins.
Unless cross-talk noise occurs on asynchronous signals such
as reset clear signals or on clock signals, cross-talk noise has to
be strong enough to propagate through logic before it could
be detected. The glitch in the victim net from aggressor net
causes the victim net to take longer time to settle to its final
value. In static combinational logic, cross-talk increases the
delay across a net; in dynamic logic cross-talk can cause the
state of a node to flip, causing a permanent error. The cross-
talk-induced delay is in fact the cross-talk-induced glitch
plus the original response of the affected victim line. In simple
terms the amplitude of the noise induced in a victim line scales
with Cc/Ctot. Cross-talk noise verification could be classified
into four major steps:
1 coupled network extraction;
2 victim aggressor selection;
3 cluster network generation; and
4 cross-talk noise computation.
Process variations impact signal-integrity issues such as cross-
talk noise, coupling induced delay, electromigration, current
multiplied by resistance (IR) drop, etc. When process
variations impact these parameters significantly,
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K.G. Verma, B.K. Kaushik and R. Singh Volume 26 · Number 3 · 2009 · 49 –55

Figure 2 Typical distribution of Interconnect technology parameters

Permittivity IMD2 thickness IMD3 thickness
30 25
160 s/m = 0.2 s/m = 5.8 s/m = 7.1
×100 25 ×100 20 ×100
120 20
15
80 15
10
10
40 5
5
0 0 0
2.94 3.57 4.20 4.83 0.04 1.02 1.20 1.30 (mm) 0.04 1.02 1.20 1.30 (mm)

M3 height M3 width
60 40
s/m = 3.0 s/m = 4.6
50 ×100 ×100
30
40
30 20
20
10
10
0 0
0.02 1.12 1.32 1.52 (mm) 0.75 0.91 1.07 1.22 (mm)
Source: Boning and Nassif (2000)

Figure 3 CMP induced OCV on interconnects

Dielectric level before CMP
Erosion
Dielectric level after CMP
Dishing
Copper
Dielectric
manufactured products may experience unexpected reliability
failures. Therefore, it is extremely important to include
variability during reliability analysis and optimization – this
will minimize yield loss due to reliability failures caused by
process variation and ensure a robust design across the entire
process spread.
The impact of interconnect variations on signalintegrity
issues, such as cross-talk noise and coupling induced-delay
degradation (i.e. dynamic delay) is one of actively researched
area. Accurate statistical modeling of interconnect coupling
requires accurate nominal models for cross-talk noise and
coupling-induced-delay change caused by the simultaneous
switching of aggressor and victim wires.
Modeling static noise has been a rigorously studied topic
and various static-noise models have been proposed time to
time that exhibit a high degree of accuracy (Sakurai, 1993;
Vittal et al., 1999; Devgan, 1997; Acar et al., 1999; Ding et al.,
2003; Chen and Marek-Sadowska, 2002). However, accurate
estimation of cross-talk-induced delay remains a challenging
task. Typically, dynamic delay is modeled by replacing the
coupling capacitance between two wires by an equivalent
ground capacitance based on the Miller effect. A few other
approaches model dynamic delay by the superposition of
a static-noise waveform on the nominal switching waveform of
the isolated victim (Sato et al., 2003; Bhardwaj et al., 2002).
These superposition-based approaches require accurate
modeling of static noise and nominal victim waveforms.
These waveforms must then be properly aligned to obtain
worst case delay change.
Static noise is defined as the noise pulse induced on a quiet
victim net due to the switching of neighboring aggressors.
Agarwal et al. (2006) discussed the impact of process variation
on static cross-talk noise in coupled RC-interconnects. Static
noise can result in functional failures due to false switching of
the victim line. For the first order, the magnitude of static
noise is directly proportional to the ratio of coupling
capacitance to total ground capacitance. This causes the
noise magnitude to be very sensitive to variations in metal
width and interwire spacing, and small variations in these
dimensions can result in large fluctuations in the noise peak.
To prove this fact, consider a simple coupled RC-interconnect
test case. The width (W), thickness (T), spacing (S), and ILD
layer thickness (H) for the interconnect lines are randomly
chosen to be 0.4, 0.75, 0.45, and 0.3mm, respectively.
Moreover, the variation in W, T, and H are assumed to be 25,
21, and 17 percent of the nominal values, respectively, (W and
S to be perfectly inversely correlated) (Agarwal et al., 2006).
The spread of noise waveforms can be obtained using
Simulation Program With Integrated Circuit Emphasis
(SPICE) Monte Carlo simulations.
Using simulations it is shown that for this test case, the
noise peak varies from approximately 160 to 235 mV, thereby
implying that variation in noise due to process variation can
be significant and should be modeled accurately. The noise-
peak distribution is Gaussian and the mean and variance of
this distribution is obtained using the Monte Carlo results.
The impact of noise on functional failures is typically
characterized by noise-immunity curves.
Dynamic delay is defined as the signal delay on the victim
line when both the aggressor and the victim switch

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 Effects of process variation in VLSI interconnects
K.G. Verma, B.K. Kaushik and R. Singh
simultaneously. It is well known that an adjacent switching
aggressor can either slow down or speed up a victim
depending on its switching polarity with respect to the
victim. The victim becomes slower in the case of out-of-phase
switching and faster due to in-phase switching. The delay
push-out during out-of-phase switching is a major concern
due to the possibility of setup-time failures, and hence, must
be accounted for in order to ensure correct operation of the
circuit. The dynamic-delay modeling with and without
process variations can ascertain the effect of process
variations.
Cross-talk noise is relatively less Gaussian than cross-talk
delay. The propagated noise is even less Gaussian. This can
be attributed to non-linear nature of the transfer functions of
the CMOS gates.
4.2 Delays due to interconnect variation
Interconnects have turned out to be most crucial factor of
signal delays, especially, in deep and very deep submicron
designs. Timing margin have become so small as frequencies
increase that even pico-second variations can no longer
be ignored, in particular for high-speed clock design. Global
interconnect delay increases as technology scales down. To
mitigate the global interconnect delay problem metal wires
have been scaled in a selective fashion. Optimal buffer
insertion methods, which reduce delay from quadratic to
linear, become difficult as the number of buffers increase at a
fast rate. The proliferation of buffers also leads to increased
power in designs. Alternatives to buffer insertion have been
proposed, some of which include static source-follower driver
(Kil et al., 2006), differential current sensing, and multilevel
signaling. In multilevel signaling approach, matching
and proper sizing of the driver and receiver transistors is
done and it is thus prone to process variations, resulting in
doubled bandwidth and delay comparable to buffer insertion.
Simply scaling down the supply voltage, undesirable
characteristics of scaled CMOS, such as drain induced
barrier lowering, quantum mechanical gate tunneling, and
punch through can also be alleviated. In the sub-threshold
region, the MOS gate capacitance is significantly less than
that in the super-threshold region due to the channel
depletion capacitance that appears in series with the oxide
capacitance Kil et al. (2006). Unlike MOS gate capacitance,
the wire capacitance value is independent of the supply
voltage. As a result, the CV/I delay of wires increase more
steeply than that of logic gates in subthreshold circuits,
exacerbating the global interconnect delay problem.
To first order, delay through an interconnect can be
expressed as the RC product of its resistance and capacitance.
With any change in the physical dimensions of the wire, its
resistance and capacitance also change, causing interconnect
delay to fluctuate. In order to model the impact of variability
on wire delay, one needs to capture the effect of geometric
variations on the electrical parameters. The change in
electrical parameters due to variations in geometric
dimensions can be captured by the simple linear
approximation.
The thickness of metal lines can vary at the bottom due to
etch effects. CMP effect influences the thickness variation
from the top of the metal, varying the interwire resistance and
capacitance. Though the distribution of resistance is fairly
Gaussian, the tail of the distribution can be attributed to non-
linear increase in resistance due to electron scattering effects.
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Surface and grain boundary scattering of electrons increases
the resistance for narrow width wires. As technology
continues to scale, the tail would become more prominent
due to increased electron scattering effect. The delay
distribution using Monte Carlo simulations shows that, even
with large variations in geometric dimensions, the delay
distribution remains Gaussian.
Characterizing and managing process variations of
interconnect geometry is becoming critical for 0.13 m and
below. Delay analysis can no longer ignore process variations
for 0.13 m and below technologies. Individual parameter
sensitivity analysis show that the delays are most influenced by
the interconnect resistance and capacitance (Lu et al., 2004b).
4.3 Parametric delay evaluation under process variation
In order to address the effect of process variation, the various
methods are:
.
clock skew analysis under process variation;
.
statistical performance analysis;
.
worst case performance analysis parametric yield
estimation;
.
impact analysis on micro architecture; and
. delay fault test under process variation.
In all the above research, one important task is to compute
variational path delay under process variation, either as
functions of process variables or as random variables of
certain distribution. However, the conventional methods to
compute path delay are either slow or inaccurate. The
response surface method (RSM) performs multiple
simulations to obtain high accuracy; the RSM method must
perform multiple parasitic extractions under different process
conditions (Brawhear et al., 1994; Acar et al., 2001; Gattiker
et al., 2001; Fabbro et al., 1995). Since, there are a large,
number of metal layers in the modern technology, there are
many interconnect process variables. For example, for a
k-layer technology, there are 3 k process variables,
corresponding to the metal width, metal thickness and
inter-layer dialectic thickness of each layer. Thus, the
traditional RSM becomes prohibitive for large circuits.
Another method Parametric Delay Evaluation (PARADE)
for fast using analytical formulae and pre-characterized
lookup tables is used to estimate for the interconnect delays.
In this method variational path delays is evaluated efficiently,
based on the lumped C delay model and based on the effective
capacitance delay model, respectively. No multiple parasitic
extractions and multiple delay evaluations are needed
(Lu et al., 2004b). The efficiency of this method makes it
possible to comprehensively analyze circuit performance on all
interconnect and device process variables for large circuits.
Compared to the traditional RSM, the delay error is within
7 per cent using analytical methods, and is within 1 per cent
using the table lookup method in PARADE (Lu et al., 2004b.
Thus, PARADE method avoids multiple parasitic extractions
and multiple delay evaluations as did in the traditional RSM,
and results in significant speedup. Since this method is based
on effective capacitance delay model it achieves higher
accuracy (Lu et al., 2004b).
5. Interconnect analysis
By accounting for systematic part of process variation in
timing analysis, uncertainty in interconnects analysis can be
reduced, thereby achieving closer bound for circuit
 Effects of process variation in VLSI interconnects
K.G. Verma, B.K. Kaushik and R. Singh
performance. One way of random analysis is to use OPERA
technique that models the stochastic response in an infinite
dimensional Hilbert space in terms of orthogonal polynomials
expansions (Vrudhula et al., 2006). It is the prototype
software that has the capability to carry out a SPICE Monte
Carlo analysis. Using such a polynomial representation,
there is no need to repeatedly generate samples of the random
parameters, and solve the system as required in Monte Carlo
approach. The accuracy in obtaining the variance by OPERA
can be increased further by increasing the order of the
expansion. This provides an attractive alternative to the
computationally expensive Monte Carlo simulations (Wang
et al., 2004).
Typically, ITP are fixed by parasitic extractors and a single
fixed value is used for the ILD or metal thickness of each
layer. Another approach to account for process variation is
depicted in Figure 4.
For random part, it is assumed that the change in the delay
of each cell on a path due to process variation can be
described as a linear function of the variation, an assumption
valid as long as the variation are small. Making this
assumption allows one to sum the cell delays to calculate
the probability distribution function of the path delay in a
straightforward way. First the delay sensitivities to cell
physical parameters and interconnect RC networks are
calculated. Then it is integrated with RC sensitivities to
process parameters, to get the corresponding delay
sensitivities to those process parameters. Given distributions
of these parameters, the delay distribution is obtained Dai and
Ji (2001).
6. Conclusion
Process variation represents a major challenge to design
system-on-chip using nanometer technologies. In this paper,
we have reviewed process variation effects on VLSI
interconnect. Variations in the interconnect geometry of
nanoscale chips deciphers to variations in their performance.
The resulting diminished accuracy in the estimates of
performance at the design stage can lead to a significant
Figure 4
Circuit layout
Variation RC sensitivities
RC extraction
models
RC netlist
Normal timing analysis
Critical path list
Statistical timing analysis
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Volume 26 · Number 3 · 2009 · 49 –55
reduction in the parametric yield. Thus, determining an
accurate statistical description (e.g. moments, distribution,
etc.) of the interconnect’s response is critical for designers. In
the presence of significant variations, device or interconnect
model parameters such as wire resistance, capacitance, etc.
need to be modeled as random variables or as spatial random
processes. Furthermore, in addition to metal thickness and
width variation, damaged dielectric regions on the side of the
metal lines are important contributions to cross-talk and
delays. It has also been comprehended that process variations
are not completely random data. The systematic part of
variations plays an important role in deviating electrical
parameters.
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Corresponding author
B.K. Kaushik can be contacted at: brajesh_k_k@yahoo.com
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