Oxidation lift-off technology

S. Oktyabrsky*, M. Yakimov, V. Tokranov, J. van Eisden, A. Katsnelson

College of Nanoscale Science and Engineering, University at Albany – SUNY, 251 Fuller Rd.
Albany, NY USA 12222

ABSTRACT

Reduction of the stresses produced in hybrid integrated structures due to thermal expansion coefficient difference
requires removal of the substrate as one of the key elements. Commonly used epitaxial lift-off technique can hardly be
employed for the fabrication of VCSELs with all-epitaxial DBRs due to the low etching selectivity between AlAs
sacrificial layer and DBR layers with high Al contents. Novel method of substrate removal named oxidation lift-off was
proposed and demonstrated. This process shows higher selectivity against Al-content than epitaxial lift-off method, that
allows for the release of a VCSEL structure with epitaxial DBRs and separate individual components on Si, reduces the
number of process steps and eventually reduces the cost of the fabricated/integrated devices. Au-Ge alloy was used for
the metal bonding of the test oxidation lift-off structures grown by MBE. 1 µm thick AlAs imbedded sacrificial layer
was laterally oxidized to release the partially processed devices from the GaAs substrate. 2D array of separated
VCSELs was fabricated on top of the Si substrate. Contact annealing, substrate removal, device separation, bonding and
formation of the oxide apertures were completed within a single processing step. Electroluminescent spectra, I-V and P-
I characteristics of fabricated devices were measured. Series resistance of fabricated devices was found to be about 100
Ohms. Lasing with threshold current of 8 mA was demonstrated for the device with 25 µm aperture.

Keywords: oxidation lift-off, hybrid integration, VCSEL, stress reduction, metal bonding.

1. INTRODUCTION

Merging of optical emitters with silicon electronics is a long-standing challenge for many applications, such as chip-
level optical interconnects, optics-on-a-chip systems, optical telecom chips, etc. [1]. In these applications, optical
transmitters are typically envisioned as an array of group III-V compound semiconductor vertical cavity surface
emitting lasers (VCSELs) bonded to a top level metallization of Si integrated circuitry [2, 3]. Dissimilarity of materials
and incompatibility of Si and III-V technologies makes the technologies of hybrid integration of dense arrays of fast III-
V photoemitters and photodetectors with Si a real showstopper for implementation of the emerging III-V/Si systems.

Due to the stresses induced by the difference in thermal expansion coefficients (6.8x10-6 vs. 2.6x10-6 for GaAs and Si,
respectively) integration technology should include substrate release and separation of the devices. Removal or thinning
of the GaAs substrate is an essential first step to reduce the thermal mismatch stresses down to the acceptable levels [4,
5]. Our finite-element analysis [1] shows that thinning down the attached GaAs layer reduces the stress values by 3-6
times, which might enhance the system integrity against fracture/voiding of solder bumps used for bonding and stress-
induced degradation of laser diodes. The second important step is separation of the GaAs-based components to reduce
the area of the bonded structure and, therefore, to prevent buckling and cracking of the thinned III-V layer.

Though there are a few methods demonstrated for GaAs substrate removal, this technology is still challenging, in
particular when combined with the separation of the processed devices on top of Si chip. Three most widely used
methods of substrate removal: (i) wet etching, (ii) smart-cut and (iii) epitaxial lift-off have specific issues when used for
fabrication of efficient AlGaAs-based light emitting devices, such as VCSELs and resonant cavity photodetectors.
(i) A simple substrate wet chemical thinning down to an imbedded AlAs etch-stop layer was employed in a number of

*
soktyabrsky@uamail.albany.edu; phone 1 518 437-8686; fax 1 518 437-8603

Optoelectronic Integration on Silicon II, edited by 149

Joel A. Kubby, Ghassan E. Jabbour, Proceedings of SPIE Vol. 5730
(SPIE, Bellingham, WA, 2005) · 0277-786X/05/$15 · doi: 10.1117/12.591112
 studies [5, 6]. The wet chemistries (such as NH4OH-H2O2-H2O) often attack metal or polymer layer used for bonding.
Protection of edges and attached surface of the structure results in high nonuniformity of etching and makes the
technology unreliable and hardly scalable. In addition it produces significant amount of a chemical waste.
(ii) An epitaxial lift-off technology proposed by Yablonovitch [7] has proven to be very effective when GaAs/low-Al
concentration AlxGa1-xAs structure is separated from GaAs substrate. This method involves selective lateral etching of
AlAs sacrificial layer using HF acid or buffered oxide etch. However, layers with x >0.7 have too low selectivity of
etching with respect to AlAs. In fact, the etching rate changes just by a factor of 10 for x=0.8-1 [8]. To utilize the
selectivity of several orders of magnitude, the structure to be separated should contain layers with x<0.6. However, in a
particular case of vertical cavity surface emitting lasers (VCSELs) with epitaxial distributed Bragg reflectors (DBRs),
the number of periods should be doubled to obtain the same reflectivity as in the GaAs/AlAs DBR. Therefore, the
application of epitaxial lift-off method to VCSEL structures is problematic.
(iii) A smart cut technology was demonstrated most recently [9, 10]. This method relies on light element implantation to
generate a localized stressor release layer. In the second stage, the structure is annealed to create a crack along the
stressed layer and release the thin layer over the implanted region. The smart cut method is very useful to separate
majority carrier devices or passive structures on virtually any semiconductor substrate (Si, GaAs and InP layer release
were demonstrated), which are not sensitive to the defects induced by implantation. As to the laser structures, this
method is not applicable.

Recently, we have introduced a novel process of substrate removal, oxidation lift-off method [11], that provides high
planarity and low roughness of the released epitaxial structure and can be used for fabrication of efficient light emitting
devices containing DBRs, such as VCSELs. In the present paper, we report on the fabrication of VCSELs hybrid
integrated on a Si substrate using the oxidation lift-off technology and metal bonding by Au/Ge alloy. Substrate
removal, separation of the devices, formation of oxide apertures, bonding and contact annealing steps were carried out
in a single process.

2. WET OXIDATION FOR GaAs SUBSTRATE RELEASE

Wet lateral oxidation process has been proposed by Dallesasse et al. [12] and widely used later to form current and light
confinement aperture by the formation of an AlOx layer close to the VCSEL active area [13, 14], or to form a high
reflectivity broad stop-band DBRs [15]. This process is based on steam oxidation of AlGaAs layers imbedded into the
structure. It has been demonstrated that this process has sufficient selectivity for even small difference in Al content in
AlGaAs layers [11].

The major advantage of the wet oxidation process is its extremely high selectivity with respect to the Al content in
AlGaAs alloy. This property requires a precise control over the composition during growth of the heterostructure in
order to achieve reproducible oxidations [12]. The growth of high Al content alloys is, however, problematic with
respect to reproducibility. Molecular beam epitaxy (MBE) provides a means to employ short-period superlattices
(SPSLs) also termed digital-alloys, which consist of a few monolayer (ML) - thick layers, to enhance control over the
composition as compared to alloys. In MBE, the SPSLs of a wide variety of compositions can be grown without
changing the effusion cell temperatures. Moreover, SPSL retains an atomically smooth surface during growth as
compared to alloys, which is especially important when very thick structures like VCSELs with a total thickness in
excess of 10 µm are grown.

Figure 1 shows a dependence of lateral oxidation rate of 100 nm-thick AlxGa1-xAs layers at different temperatures. To
increase the accuracy and reproducibility of the high Al-content layer composition provided by molecular beam epitaxy,
we employed short-period superlattices consisting of (Al0.6Ga0.4As)1ML (AlAs)yML stacks, with y = 3-19 monolayers to
achieve the average Al content of x = 0.90-0.98.

It can be seen from the Figure 1, that by decreasing the Al content only a few percent, the oxidation rate can be reduced
significantly and, therefore, the wet oxidation process provides a high selectivity with respect to the Al content.
Comparing AlAs to All0.9Ga0.1As, a selectivity of about 1:10 to 1:100 can be achieved depending on the oxidation
temperature. This make the proposed technique suitable for use with most optoelectronic devices, like VCSELs with
x=0.85-0.9 alloy used in Bragg reflectors. The oxidation process was observed to proceed linearly with time and the
rates for SPSLs were significantly higher than those of alloys with the equal average Al content. This difference in the

150 Proc. of SPIE Vol. 5730

 1 450°C
Oxidation rate, µm/min ELO
400°C

0.1 350°C
Superlattices
Alloys

0.01

1E-3
90 92 94 96 98 100
Al content, %

Figure 1. Oxidation rate vs. Al content for various oxidation temperatures, illustrating the
selectivity of the wet oxidation process with respect to the Al content of the 100 nm-thick layer to
be oxidized. Open symbols with dotted lines correspond to alloy, and closed symbols with solid
lines correspond to short-period superlattice. Thin line with crosses shows composition dependence
of wet etch rate by buffered oxide etch solution typical for epitaxial lift-off (ELO) from Ref. 8.

oxidation rates is decreasing with increasing oxidation temperature and they become equal within the error of the
experiment at 450 °C. This observation is in agreement with a report by Pickrell et al.[16], who observed the same trend
for an AlAs/GaAs SL with an effective Al content of 98 %.

The highest selectivity against Al content is obtained at low temperatures when the oxidation rates are low. Therefore,
the oxidation experiments for GaAs substrate release described in this paper were carried out at 400-420 0C at the
oxidation rates 0.3-0.6 µm/min for AlAs layers.

It is well documented by now that VCSELs employing oxidized AlAs layers suffer from delamination and degradation
problems [17] due to build-up stress in the AlOx layer originating from a considerable shrinkage of the AlAs upon wet
oxidation. High Al content AlGaAs layers are generally preferred as wet oxidation layers and are proved to be more
mechanically stable [17]. However, even in this case, large oxidation lengths eventually results in cracking [18].
Recently, we have demonstrated that 1000 Å-thick Al0.98Ga0.02As layer embedded into 2 µm thick-Al0.1Ga0.9As layer,
shows cracking upon oxidation over ~20 µm. Similar structure is shown in Figure 2. The crack propagates
approximately 20 µm from the mesa edge along the oxidized layer and then towards the top of the structure.
Remarkably, the crack always originated at 20 µm from the mesa edge for this structure, indicating the existence of a
critical stress and, therefore, a critical oxidation length (naturally this critical length depends on thickness and
composition of the structure). This disadvantage of the lateral oxidation method will be exploited in the oxidation lift-
off technology to release an epitaxial structure from the GaAs substrate by introducing a crack into the sacrificial AlAs
oxidation layer.

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 Figure 2. Optical micrograph (left) and (right) Focused Ion Beam cross-sectional image of an LED structure with a
laterally oxidized 90 µm mesa. Crack propagates along the oxidized Al0.98Ga0.02As layer over 22 µm and then towards
the top of the structure. Cracks were formed during wet oxidation.

3. PROCESSING DETAILS

All-epitaxial VCSEL structure was grown on a (100) GaAs substrate using an EPI GEN II MBE system. An AlxGa1-xAs
layer with x = 0.96 aluminum content was imbedded into the structure between the bottom DBR and the active area of
the VCSEL structure and later used to form oxide apertures (Fig. 3a). The VCSEL DBRs were grown for substrate-
emitting operation to enable the face-to-face bonding with a Si wafer. Semi-transparent bottom DBR contained 19
periods, and top DBR had 29 periods of GaAs/Al0.9Ga0.1As quarter-wavelength layers with 10 nm-thick graded
interlayers. The active area consisted of 3 periods of 10 nm InGaAs quantum wells separated with 8 nm-thick
Al0.25Ga0.75As layers. A 1 µm thick AlAs release layer was grown between the substrate and the VCSEL structure. The
top DBR was p-doped with carbon to 5x1018 cm-3 and the bottom DBR was n-doped with Si to 3x1018 cm-3.

The following process flow was applied for the fabrication of the devices. A p-type Pt/Ti/Pt/Au (10/40/10/150 nm)
ohmic contact was deposited on top of the p-DBR using e-beam evaporation and lift-off process. A Cr/Pt/Au/Ge/Au
(5/10/150/30/20 nm) stack was deposited on top of a Si/SiO2 wafer used as a substrate for VCSELs. In this stack Cr
acted as an adhesion layer to SiO2, Pt was used as a diffusion barrier for Cr, and the 20 nm-thick top gold layer was
used to prevent the Ge layer from oxidation in the air and water vapor environments.

After contact layer deposition and metal lift-off, VCSEL mesa structures were formed by reactive ion etching in the
Cl2/BCl3 ECR plasma using a photoresist mask. The mesas were etched down to the substrate through the imbedded
AlAs release layer (Fig.3b).

In the following step, the VCSEL mesas are aligned (face-to-face) with metal pads on Si substrate. In our case, for a
demonstration purpose we have used a blanket Cr/Pt/Au/Ge/Au metal stack on the Si/SiO2 wafer, and no alignment was
necessary. This bonding sandwich was further placed into the preheated 400˚C oxidation furnace for bonding, contact
annealing, substrate release, and oxide apertures formation. Moderate load ~5g per square cm of the substrate area that
corresponds to a 5 kG/cm2 of the mesa area, was applied to the structure in order to enable bonding (Fig. 3c).

The furnace was purged for 10 minutes with dry nitrogen to facilitate melting of the Au-Ge eutectic employed
for metal bonding. After that water vapor was introduced by flowing nitrogen through a bubbler. The oxidation was
carried out at 420˚C for 20 minutes that corresponded to a 10 µm oxidation length of Al0.96Ga0.04As oxidation layer, 1.5

152 Proc. of SPIE Vol. 5730

 Figure 3. Schematics of the oxidation lift-off process flow: (a) VCSEL structure growth, (b) Au-Ge contact
deposition and mesa etching, (c) bonding, oxidation and substrate release in oxidation furnace, (d) final structure
with released substrate.

µm oxidation length of Al0.9Ga0.1As DBR layer, and 100 µm-long oxidation of pure AlAs that was long enough to
release the substrate.

After 20 minutes of oxidation, the furnace was turned off, pumped down and then purged by dry nitrogen to
remove residual steam. When the temperature inside the furnace dropped below 360°C (eutectic temperature for Au-Ge
alloy) the metal layer solidified and the bonded GaAs/Si structure was unloaded from the furnace. At this point the
GaAs substrate is found to be released from the device mesas (Fig. 3d). It was also found that the release aluminum
oxide film primarily stayed attached to the substrate, but if the residues of this film found on the bonded devices, they
can be removed by etching in a phosphoric acid.

The final structure consists of a Si/SiO2 wafer covered by AuGe alloy that acts as a bonding and contact layer
and separated VCSEL mesas bonded on to the Si/SiO2 wafer. Bonding, separation of the devices, annealing of the
contact and formation of oxide apertures were completed within one step.

4. RESULTS AND DISCUSSION

To evaluate the capabilities of the oxidation lift-off technology, we employed the method to release large mesas of
VCSEL structures from GaAs substrates. Figure 4 shows 1x2 mm2 structure bonded to Si/SiO2 substrate using AuGe
alloy and released from the GaAs substrates using the process described above. This structure contained DBRs layers
with Al content as high as 0.9 but the oxidation of the DBR layers (~1 µm deep) is hardly visible at the image scale.

4.1 Bonding schemes

Most typical bonding schemes involve solder bumps, similar to flip-chip packaging[19], polymer glues [6, 20] or metal
alloys [21] to attach optoelectronic components to Si.

Proc. of SPIE Vol. 5730 153

 Figure 4. Large area ( 1x2 mm ) of VCSEL
Figure 5. FIB cross-sectional image of the bonded VCSEL.
structure transferred on Si by oxidation lift-off.
Interface region shows the crystallized AuGe/Au alloy layer.
Note clean and uniform surface of the structure
after substrate release.

In our experiment, Au-Ge alloy was a natural choice, because it is a widely used ohmic contact metal to n-type GaAs.
We envision that it might be substituted by other eutectic alloys with a melting point close to 400 0C, such as Al-Ge,
Au-Si. We have in fact, observed formation of Au-Si if bonding was done directly to Si substrate without oxide layer. In
this case, the surface of the substrate was found to become rough due to precipitation of Au-Si alloy. A focused ion
beam (FIB) cross-section of a bonded interface is shown in Figure 5. The bonding interfaces uniform, the alloy layer
consists of crystallites a few hundred nm in size and is multiphase due to complex metallurgy of the bonding layer.

In the bonding technology employed, the bonding alloy becomes the part of metallization scheme on Si and is used as
an electrical contact to the optoelectronic component. The metal is also beneficial for its high thermal conductivity
which is required for integration On the other hand, the problem of the metal bonding is a poor stability against wet
chemistries which might be used in further processing. For some applications it might be useful to employ polymer
instead of metal bonding. We have recently demonstrated [6] that BCB can withstand 400 0C annealing without
degradation, and therefore, might be considered as a first candidate for bonding medium for oxidation lift-off
technology. Naturally, this polymer material will require double-layer metallization from the top of the device bonded
to Si, but might provide lower parasitic capacitance if high-frequency components are bonded.

No matter which bonding material is used in epitaxial-lift-off technology, the substrate release and device separation
step should be completed during the bonding cycle. Otherwise, the structure may fracture on cooling down.

An optical image and FIB cross-section of a device mesa fabricated on a Si/SiO2 wafer by oxidation lift-off technique is
shown in Figure 6. No residual aluminum oxide was found on the surface of the device. From the FIB cross-section it is
found that the DBR was oxidized less than 2 µm deep and the oxidation layer by 12 µm. These lengths are reasonably
close to the expected values. The bonded area shows good quality bonding. No voids or cracks were found under the
bonded devices.

154 Proc. of SPIE Vol. 5730

 Figure 6. (a) Optical image and (b) FIB cross-section of a 48x48 µm2 VCSEL mesa fabricated on Si/SiO2 wafer by oxidation lift-
off technique. The oxidation length of the DBRs is about 2 µm, and the aperture is oxidized by 12 µm.

4.2 VCSEL characterization

We evaluated electrical and optical characteristics of VCSELs fabricated on top of the Si substrate by the described
oxidation lift-off technology. A blanket AuGe layer on top of the Si wafer was used as a contact to the p-side of the
structure. As the goal of the device characterization was in testing of the bonding/separation technology, we have
neither planarized the structure, nor deposited n-type Ohmic contact on top of the VCSEL. Instead tungsten probe was
contacted to the top of the n-DBR. This increased the contact resistance of the structure and did not allowed for reliable
electrical DC measurements. Planarization of the structure using reflowable PMGI polymer is underway.

Pulse electrical excitation (1 µs pulses with 2.8 ms period for I-V and P-I measurements) was applied to reduce the
heating of the top probe-to-semiconductor contact. Typical current-voltage (I-V) and power-current (P-I) characteristics
of the fabricated VCSEL with 24x24 µm2 aperture size (48x48 µm2 mesa size) are presented in Figure 7a. Series
resistance of this device was evaluated from the slope of the linear part of the I-V characteristic and was found to be
about 100 Ohms which is among the lowest values for hybrid integrated VCSELs mainly due to a large area contact to
the p-DPR resulting in a uniform current through it. Threshold current of 8 mA was found for this device. The measured
maximum pulse optical power was about 0.8 mW at 20 mA driving current that provides a large field for improvement
of the performance characteristics. Typical electroluminescent spectra of the VCSEL measured under CW conditions
are presented in Figure 7b for driving currents below and above the threshold demonstrating a clear multimode lasing of
the bonded device. Shift of the lasing peak is caused by the overheating of the structure likely due to heat generated by
n-probe .

4.3 Advantages of the oxidation lift-off technology

The oxidation lift-off method combines beneficial properties of epitaxial lift-off (ELO) and smart-cut technologies
described in the introduction. Similar to the smart-cut method, the lateral oxidation creates a stressor layer, but without
implantation through the device structure. Similar to the ELO, wet oxidation is a lateral modification of a thin layer
which does not involve etching of the bulk of GaAs substrate. Unlike ELO, wet oxidation is highly selective at high Al
content in AlxGa1-xAs compounds. In addition, oxidation lift-off allows to obtain bonding, device layer release and
device separation in a single thermal treatment process step.

Proc. of SPIE Vol. 5730 155

 Figure 7. (a) Current-voltage and power-current characteristics, and (b) CW electroluminescent spectra of the VCSEL fabricated
by oxidation lift-off technique.

This process does not require any additional steps for substrate removal, such as etching or polishing. It shows
extremely high selectivity for the Al content that makes this process beneficial for the integration of VCSELs containing
epitaxial DBRs with high Al-content layers. It does not produce any significant amount of chemical waste.

The method has several important advantages over the methods described above: this technology provides bonding and
components separation in a single-step process; it is insensitive to wafer bending due to compliancy of mesa structure; it
does not require thermal cycling of the GaAs substrate bonded to Si substrate; it makes possible to fabricate oxide
aperture in VCSELs in the same oxidation step if the Al concentration in the oxide-aperture layer is chosen properly; it
allows for robust bonding with hard high melting temperature solder.

CONCLUSIONS

Hybrid integrated VCSELs were fabricated on top of a Si wafer by the oxidation lift-off technology. Device mesas
formed by reactive ion etching were bonded to a Si wafer using metal bonding by Au/Ge alloy. Substrate removal,
bonding, contact annealing and formation of oxide apertures were done within the same processing step by wet lateral
oxidation of the VCSEL structure. Lasing, electrical and optical characteristics of the fabricated devices were
demonstrated.

The proposed technology can be employed for heterogeneous integration of various GaAs-based devices, such as lasers,
light-emitting diodes, photodetectors, transistors, etc. with Si or other substrates. The applications include various large
broadband optical telecommunication and interconnect modules including chip-level optical interconnects, various RF
and microwave systems which require integration of high performance III-V semiconductor components with Si
circuits, various sensor applications utilizing optical and microwave technologies, "system-on-a-chip" applications, just
to name a few.

ACKNOWLEDGEMENT

This work has been supported by MARCO, DARPA and NYSTAR through Focus Center for Interconnects for
Hyperintegration. This support is greatly appreciated.

156 Proc. of SPIE Vol. 5730

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