Session 12C2
A Digital Phase Lock Loop
For VLSI Telecommunication Applications
IEEE
ABSTRACT
T h i s paper d e s c r i b e s t h e d e s i g n and s i m u l a t i o n
r e s u l t s f o r two v e r s i o n s of a d i g i t a l phase l o c k
l o o p ( D P L L ) . One v e r s i o n u s e s a s i m p l e random
walk f i l t e r , whereas t h e second v e r s i o n uses a
s i m p l e a d a p t i v e scheme t o extend t h e l o c k
frequency r a n g e without d e g r a d i n g t h e phase
resolution.
INTRODUCTION
An e s s e n t i a l component i n any synchronous
telecommunication system i s a d i g i t a l phase-locked
l o o p (DPLL). I t i n s u r e s t h a t t h e c l o c k i n t h e
receiver and t r a n s m i t t e r a r e synchronized. A
b a s i c DPLL i s designed t o r e c o v e r a p e r i o d i c c l o c k
i n t h e p r e s e n c e of n o i s e . The a d d i t i o n of 2
t r a n s i t i o n one s h o t a t t h e i n p u t t o a b a s i c DPLL,
makes it p o s s i b l e t o r e c o v e r a c l o c k from an
a p e r i o d i c d a t a stream.
T h i s paper d e s c r i b e s two v e r s i o n s of a t r a n s i t l o r
sampling DPLL. The f i r s t uses a random walk
f i l t e r [ I 1 c21 f o r n o i s e r e j e c t i o n . A random walk
f i l t e r is e s s e n t i a l l y an up-down c o u n t e r , whose.
i n p u t i s t h e p o l a r i t y of t h e phase e r r o r and whose
o u t p u t s a r e ADD and SUB ( s u b t r a c t ) phase
c o r r e c t i o n s . The c o u n t e r i s reset t o z e r o a f t e r a
phase c o r r e c t i o n i s made. With t h f s v e r s i o n , high
phase r e s o l u t i o n r e s u l t s i n narrow l o c k - i n
f r e q u e n c y r a n g e and l o n g c a p t u r e time. I n v e r s i o n
2 of t h e DPLL, a n a d a p t i v e scheme designed t o
r e d u c e t h e c o n f l L c t i n t h e s e performance c r i t e r i a
is employed. With t h i s scheme t h e t h r e s h o l d f o r
t h e ADD and SUB s i g n a l s i s a d a p t e d , based upon t h e
t h r e e p r e v i o u s phase c o r r e c t i o n s . I n an a l t e r n a t e
a d a p t i v e scheme C31, t h e reset s t a t e of t h e f i l t e r
i s adapted.
Both v e r s i o n s of t h e DPLL have been s u c e s s f u l l y
s i m u l a t e d u s i n g t h e l o g i c s i m u l a t o r SILOS. '
Version 1 i s being f a b r i c a t e d f o r u s i n 2 micron
CMOS by H a r r i s Corporation.
ARCHITECTURE AND DESIGN
The a r c h i t e c t u r e f o r t h e f i r s t v e r s i o n of t h e DPLL
is shown i n F i g u r e 1. I t c o n s i s t s of a t r a n s i t i o n
one s h o t , which c o n v e r t s t h e i n p u t d a t a s t r e a m
i n t o an a p e r i o d i c c l o c k stream, a mod 1 5 up/down
c o u n t e r , which a c t s a s a phase comparator and
random walk f i l t e r , a decoder, which decodes phase
Proceedings
Harry A.Nienhaus
E l e c t r i c a l Engineering
U n i v e r s i t y o f South F l o r i d a
Tampa, F l o r i d a
Vijay K. J a i n
E l e c t r i c a l Engineering
U n i v e r s i t y o f South F l o r i d a
Tampa, F l o r i d a
c o r r e c t i o n s from t h e random walk f i l t e r o u t p u t , a
phase c o n t r o l l e r , which e i t h e r adds o r s u b t r a c t s a
p u l s e from a master c l o c k d a t a s t r e a m and resets
t h e random walk f i l t e r a f t e r 2 phase c o r r e c t i o n i s
decoded, 2 mod 64 c o u n t e r , which d i v i d e s t h e
master c l o c k f r e q u e n c y , and a 2 phase c l o c k
generator.
The o p e r a t i o n of t h e DPLL i s a s f o l l o w s . A 20.48
MHz c l o c k is c o n v e r t e d t o a 10.24 MHz, 2 phase,
nonoverlapping c l o c k which d r i v e s a phase
c o n t r o l l e r . The phase c o n t r o l f e r o u t p u t is
normally a 10.24 MHz c l o c k with'25k d u t y c y c l e .
T h i s i s d i v i d e d down by a mod 64 c o u n t e r t o a 160
KHz c l o c k whose phase i s compared t o t h e i n p u t ,
which i s 2 d a t a s t r e a m d e r i v e d from a 160 KHz
clock. The mod 15 up/down c o u n t e r performs t h e
phase comparison, f i l t e r s o u t n o i s e , and improves
t h e l o c k - i n phase r e s o l u t i o n . The o u t p u t of t h e
up/down c o u n t e r i s n o t decoded u n t i l a n e t of 7
phase e r r o r s of t h e same p o l a r i t y a r e counted.
When t h i s o c c u r s , t h e decoder t e l l s t h e phase
c o n t r o l l e r t o e i t h e r add o r s u b t r a c t 2 p u l s e from
t h e c l o c k stream. A t t h e same time t h e phase
c o n t r o l l e r a l s o produces a p u l s e t o r e s e t t h e
up/down c o u n t e r . I f a p u l s e i s s u b t r a c t e d , t h e
160 KHz c l o c k phase i s s h i f t e d r i g h t , and ii' a
p u l s e is added, i t is s h i f t e d l e f t .
The 2 phase non o v e r l a p p i n g 13.24 MHz c l o c k
s i g n a l s are o b t a i n e d by decoding t h e o u t p u t s of
two mod 2 c o u n t e r s which a r e 93 degrees o u t of
phase. The c l o c k i n p u t t o t h e c o u n t e r s i s a 23.48
MHz c l o c k . T h i s g i v e s g l i t c h - f r e e o u t p u t s which
a r e r e l a t i v e l y independenI9 of propagation d e l a y s .
The s c h e m a t i c 2nd t i m i n g diagrams of t h e phase
c o n t r o l l e r a r e shown i n F i g u r e s 2 and 3
r e s p e c t i v e l y . - T h e o p e r a t i o n of t h i s block i s 2s
f o l l o w s . I n i t i a l l y , both f l i p f l o p s a r e r e s e t t o
0 and w i l l remain a t 0, a s l o n g a s b o t h t h e A D D
and SUB i n p u t s a r e 0. For t h i s c a s e t h e PHI1
c l o c k s t r e a m w i l l be t r a n s f e r r e d t o t h e o u t p u t .
I f t h e A D D i n p u t goes t o 1 , t h i s i s t r a n s f e r r e d t o
QA when PHI1 goes h i g h , and 2 s i n g l e PHI2 c l o c k
p u l s e i s added t o t h e PHI1 c l o c k s t r e a m normally
t r a n s m i t t e d . S h o r t l y a f t e r QA goes t o 1 , t h e LD
s i g n a l r e s e t s t h e up/down c o u n t e r t o 3, A D D goes
t o 0 , and QA goes back t o 0 when PHI1 a g a i n goes
high. I f t h e SUB i n p u t goes t o 1 , t h i s is
t r a n s f e r r e d t o QS when PHI2 goes h i g h , 2nd a
s i n g l e p u l s e is s u b t r a c t e d from t h e P H I 1 c l o c k
stream normally t r a n s m i t t e d . Again t h e L D s i g n a l
- 1989 Southeastcon
1216 CH2674-5/89/0000-1216$01.00019891EEE
 "

X2CLK

FIGURE 1. D I G I T A L PHASE LOCKEU LOOP

PHI1
n, n n n
PHI2
n n :,n n n L
ADD
V

SUB
1

QA

T
"
L

CP

F I G U R E 2. PHASE CONTROLLER SCHEMATIC n

i n s u r e s t h a t o n l y a s i n g l e c o r r e c t i o n i s made f o r
each A D D o r SUB s i g n a l . FIGURE 3. PHASE CONTROLLER T I M I N G DIAGRAM

T h e mod 64 c o u n t e r c o n s i s t s of a synchronous mod

16 counter assynchronously d r i v i n g a synchronous
mod 4 c o u n t e r . The XOR g a t e p l u s 2 d e l a y
i n v e r t e r 5 shown i n F i g u r e 1 form a t r a n s i t i o n one A Simple a n a l y s i s of t h e DPLL i n t h e absence Of

s h o t . Since t h e i n p u t s t o t h e Xor g a t e a r e noise follows.

i d e n t i c a l , t h e o u t p u t i s 0 except a f t e r . a 0 t o 1
o r 1 t o 0 t r a n s i t i o n . Because of t h e d e l a y i n t h e Let Tc = d i s c r e t e time C o r r e c t i o n . (1/10.24 MHz)
d e l a y i n v e r t e r s , t h e o u t p u t w i l l go t o l o g i c 1 f o r T = e r r o r i n t h e period.
approxjmately 20 n s a f t e r every i n p u t t r a n s i t i o n .
This one s h o t makes i t p o s s i b l e t o r e c o v e r a c l o c k L = counter divider r a t i o . (64)
from an a p e r i o d i c d a t a stream. N = random walk f i l t e r Count.
f = f r e e r u n n i n g frequency. (160 KHz)
The decode f u n c t i o n s a r e :
Tne f o l l o w i n g r e l a t i o n s h i p i s e a s i l y s e e n from
SUB = a3Q2Q1Q0 F i g u r e 1.

ADD = Q a a T = l / f o = LT c
3 2 1

A p o r t i o n of t h e s i m u l a t i o n timing diagram j u s t The DPLL is c a p a b l e of making a f i n i t e c o r r e c t i o n

p r i o r t o and a f t e r l o c k - i n is shown i n F i g u r e 4. of +Tc e v e r y N c y c l e s t o t h e nominal p e r i q d To.
T h i s Rhows t h e s i g n a l s IN, OUT, t h e o u t p u t of t h e Hence t h e limits on t h e a v e r a g e p e r i o d of t h e
t r a n s i t i o n one s h o t , A D D , SUB, and LD. Note t h a t output are:
b e f o r e l o c k - i n , c o n s e c u t i v e SUB s i g n a l s occur t o
c o r r e c t t h e phase. A f t e r l o c k - i n ADD and SUB T = T 2 Tc/N = T [ I 2 1/LN)
sig n a l s a 1ter n a t e .

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 X2CLK

RESET

FIGURE 5. A D A P T I V E D I G I T A L PHASE LOCKED LOOP

The f r e q u e n c y l o c k r a n g e is t h e r e c i p r o c a l of ACKNOWLEGEMENT
t h i s , and t h e p e r i o d e r r o r must s a t i s f y t h e
relationship , T h i s work was s u p p o r t e d by t h e Center f o r
M i c r o e l e c t r o n i c s and T e s t (CMDAT) of t h e
Te 2 _+TO/LN U n i v e r s i t y of South F l o r i d a .

BIBLIOGRAPHY
S i n c e t h e maximum phase e r r o r is T o / 2 , and t h e
maximum c o r r e c t i o n is T /N, t h e maximum number of J. K. Holmes, "Performance of a F i r s t - O r d e r
T r a n s i t i o n Sampling D i g i t a l Phase-Locked Loop
cycles k required t o lock-in is, Using Random-Walk Models", I E E E T r a n s a c t i o n s
on Communications, v o l com-23, no 2 , Apr
k = NTo/2Tc = LN/2 1972.

The phase r e s o l u t i o n i n degrees i s 360 Tc/LN J . Sandoz, "Performance Improvement of a

Note t h a t t o g e t good phase r e s o l u t i o n LN must be
l a r g e . On t h e o t h e r hand, l a r g e LN means t h a t t h e
l o c k frequency r a n g e is narrow, and t h e c a p t u r e
time is long. T h i s c o n f l i c t can be p a r t i a l l y
r e s o l v e d by u s i n g an a d a p t i v e f i l t e r which makes N
small b e f o r e l o c k - i n and i t s normal v a l u e a f t e r
lock-in. Note t h a t b e f o r e l o c k - i n when t h e phase
e r r o r is l a r g e , t h e p r o b a b i l i t y of n o i s e g i v i n g
r i s e t o an e r r o n e o u s phase c o r r e c t i o n is much
l o w e r t h a n a f t e r lock-in. T h i s is because a major
s o u r c e of n o i s e a f t e r l o c k - i n is r i n g i n g .
Binary Q u a n t i z e d A l l D i g i t a l Phase-locked
Loop w i t h a N e w Aided-Acquisition Technique",
I E E E T r a n s a c t i o n on Communications, vol com-
32, no 1 2 , Dec 1984.
H. Yamamoto and S. Mori, llPerformance of a
Binary Q u a n t i z e d A l l D i g i t a l Phase-Locked
Loop w i t h a New C l a s s of S e q u e n t i a l F i l t e r " ,
I E E E T r a n s a c t i o n on Communications, v o l corn-,
2 6 , no 1 , Jan 1978.

The a r c h i t e c t u r e f o r t h e a d a p t i v e v e r s i o n ol-' the

DPLL is shown i n F i g u r e 5. T h i s u s e s t h e
following simple algorithm. I f 3 consecutive ADD
s i g n a l s o c c u r , t h e n e x t ADD s i g n a l is decoded a s
-3 i n s t e a d of -7. S i m i l a r l y , i f 3 c o n s e c u t i v e SUB
s i g n a l s o c c u r , t h e n e x t SUB s i g n a l is decoded a s a
+3 i n s t e a d of a +7. T h i s scheme, which is s i m p l e r
t h a n t h a t used i n C31, w i l l approximately double
t h e l o c k f r e q u e n c y r a n g e and c u t t h e c a p t u r e time
i n h a l f . S i n c e ADD and SUB s i g n a l s a l t e r n a t e
d u r i n g l o c k - i n , it w i l l n o t . a f f e c t t h e r e s o l u t i o n
or t h e n o i s e r e j e c t i o n p r o p e r t i e s d u r i n g t h i s
time. Additonal hardware r e q u i r e d i s an RS l a t c h ,
and 3 D F F ' s t o s t o r e t h e p o l a r i t y of t h e l a s t 3
c o r r e c t i o n s , p l u s a m u l t i p l e x e d decoder.

A p o r t i o n of t h e s i m u l a t i o n t i m i n g diagram f o r t h e
a d a p t i v e DPLL j u s t p r i o r t o and a f t e r l o c k - i n i s
shown i n F i g u r e 6. T h i s shows t h e t h e s i g n a l s I N ,
OUT, ADD, SUB, and LOAD. Note t h a t j u s t p r i o r t o
l o c k - i n , c o n s e c u t i v e SUB s i g n a l s o c c u r , each a f t e r
3 d a t a t r a n s i t i o n s . After l o c k - i n o c c u r s , t h e
operation is identical t o version 1.

Proceedings - 1989 Southeastcon

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OUT

SUB

ADD

F I G U R E 4. D P L L S I M U L A T I O N T I M I N G DIAGRAM

-
-

IN

ADD I

SUB I

LD

F I G U R E 6. ADPLL S I M U L A T I O N T I M I N G DIAGRAM

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 VIJAY K. JAIN'

Vijay K. Jain (M'63-SM'75) received the

Ph.D. degree in electrical engineering from
Michigan State University, East Lansing, in 1964.
He has been on the faculty of several
universities, including Michigan State University,
Florida State University, Georgia Institute of
Technology, and the University of South Florida,
Tampa. As Full Professor of Electrical
Engineering since 1976 at USF, he has taught
courses in Communication Systems, Microprocessors
Based DSP, Communication Networks, and Digital
Signal Processing (including speech and image
processing). His current research interests
include VLSI design for signal processing.
In the summer of 1952, and again in 1984, he
was with the AT&T Bell Laboratories, Murray Hill,
NJ .
-

H A R R Y A. NIENHAUS

H. A. Nienhaus i s a n A s s o c i a t e P r o f e s s o r i n t h e
E l e c t r i c a l Engineering Department a t t h e
U n i v e r s i t y of South F l o r i d a , where he has been
s i n c e 1967. P r i o r t o t h i s he worked a t Xerox
Corp. I n f o r m a t i o n Systems D i v i s i o n and McDonnell
A i r c r a f t Corp. E l e c t r o n i c s D i v i s i o n . He r e c e i v e d
h i s BSEE degree i n 1958 and h i s MSEE degree i n
1964, b o t h from S t . Louis U n i v e r s i t y . H i s p r e s e n t
i n t e r e s t s i n c l u d e V L S I , DSP a r c h i t e c t u r e s , and
high speed a r i t h m e t i c .

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