K L E F UNIVERSITY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

CURRICULUM
M.Tech. Degree Programme
In
VLSI

 
 K.L. UNIVERSITY
M.Tech (VLSI)
Syllabus Structure

Yr I Semester II Semester
Code Subject Cr Code Subject Cr
VL511 Foundations of CMOS 5 VL521 VLSI System Design 4
VLSI Design
VL512 Computer Hardware 4 VL522 Low Power VLSI Design 4
Description Languages
VL513 Programmable Logic 4 VL523 Analog VLSI Design 4
Devices
VL514 VLSI Layout Synthesis 4 VL524 VLSI Technology 3
I Algorithms
VL515 ELECTIVE - I 3 VL525 Digital System Testing and 4
Design for Testability
VL516 ELECTIVE - II 3 VL526 ELECTIVE - III 3
VL517 CMOS VLSI Design Lab 2 VL527 VLSI System Design and 2
Low Power Lab
VL518 HDL and PLD Lab 2 VL528 Analog Design and 2
Technology Lab
VL529 VLSI Test Lab 2
27 28

III Semester IV Semester

II
PROJECT WORK PROJECT WORK

ELECTIVE – I ELECTIVE – III

VL515-A Embedded Systems 3 VL526-A Logic Synthesis Algorithms 3
VL515-B VLSI Digital Signal VL526-B Formal Verification 3
Processing 3
ELECTIVE - II 3 VL526-C Advanced Topics In VLSI 3
VL516-A Computer Networking and 3
Mobile Systems 3
VL516-B Computer Architecture &
Parallel Processing
SEMESTER – I
VL511 Foundations of CMOS VLSI Design

 
1. CMOS Basics: Introduction to VLSI, History; MOS transistor theory; MOSFET Switches;
Transmission Gate; Design metrics; MOS Devices; CMOS Process Technology. (7)
 
2. Circuit Characterization: CMOS Inverter – the dynamic view; DC & AC Analysis; βn / βp
ratio; Basic logic gate design; Basic physical design; Logic effort. (5)
 
3. Digital CMOS Design: Basics of Digital CMOS Design; Combinational MOS Logic circuits;
complex logic circuits; Sequential MOS logic Circuits; Circuit families. (8)
 
4. Circuit Simulation: Delay estimate; SPICE Simulation; Asynchronous Sequential Circuit
Design; Short channel effects; Layout - design rules; inverter delays; propagate delays; Scaling
of MOS circuits. (8)
 
5. Datapaths: Datapath and Memories; SRAMs; ROMs, CAMs, PLAs; Adders; Multipliers;
Data path timing issues; Memory structures; Static CMOS design. (10)
 
6. Dynamic CMOS: Clocking; Clock trees, PLLs; Dynamic CMOS structure and design;
Charge sharing; Clock generation; Clock distribution; Clocked storage elements. (6)
 
7. VLSI Design Methodology: Typical ASIC Design Flow; Synchronous design using
Programmable Devices; Designing for speed, power, reliability, testability; Area and Power
Dissipation Estimation; Interconnect & Wire Engineering. (8)
 
8. Timing & Layout: Timing Analysis - Setup and Hold Times; Timing and clock
synchronization; Pipelining; Design Rule Checking; Hierarchical Layout Methodology; Timing
Simulation. (7)

Mini-Project: To design and physically implement an IC for the given functionality and to
successfully simulate it. (ALU type circuitry)

Text Book:

1. Jan M. Rabaey, “Digital Integrated Circuits”

Reference Book:

1. Neil Weste and K. Eshragian, “Principles of CMOS VLSI Design: A System

Perspective”
VL512 Computer Hardware Descriptive Language

Topics:
1. Introduction to VHDL: VHDL as a standard, VHDL terms, traditional design methods
2. Behavioral modeling: introduction to behavioral modeling, transport versus inertial
delay, simulation deltas, drivers, generics, block statements.
3. Sequential processing: process statement, signal assignment versus variable assignment,
sequential statements, IF statements, CASE statements, LOOP statements, EXIT
statements, ASSERT statements, WAIT statements, concurrent assignment problem,
passive process
4. Data types: object types, data types, file type caveats, subtypes
5. Subprograms and packages: subprograms, function, conversion function, resolution
function, procedures, packages
6. Predefined attributes: value kind attributes, functional kind attributes, signal kind
attributes, type kind attributes, range kind attributes
7. Configurations: default configurations, component configurations, mapping library
entities, generics in configurations, generic value specification in architecture, generic
specification in configurations, block configurations, architecture configurations
8. VHDL Synthesis: simple gate- concurrent assignment IF control flow statements, case
control statements, simple control statements, asynchronous reset, more complex
sequential statements, state machine examples
9. Introduction to Verilog: Verilog as HDL, a tutorial to verilog, Identifiers, format,
compiler directives, value set, data types, parameters, Comments, operands, Operators.

Text books
1. ‘VHDL’ by Douglas Perry, Tata Mcgraw-hill third edition
2. ‘A Verilog HDL Primier’ by J. Bhaskar, BS Publication second edition.

Reference books

1. ‘The Designer's Guide to VHDL’ by Peter J Ashenden Morgan Kaufmann Publishers

2. “VHDL-Analysis and Modeling of Digital Systems”, by Navabi, Tata Mcgraw-hill edition

 
VL513 PROGRAMABLE LOGIC DEVICES

1. Programmable Logic: Read Only Memory (ROM), PROM, Programmable Logic Array
(PLA)/Programmable Array Logic (PAL). Combinational circuit realization using ROM,
PROM. (3)

2. CPLDs : Sequential PLDs. PGAs – Features, Programming and applications using

CPLDs,- Altera series – Max 5000/7000 Series and ALTERA FLEX Logic – 10000 Series
CPLDs. AMD’s – CPLD (Mach 1 to 5); (6)

3. FPGAs: Logic blocks, routing architecture, Design flow, Technology Mapping for
FPGAs, Case studies – Xilinx XC4000 & ALTERA’s FLEX 8000/10000 FPGAs (6)

4. Finite State Machines (FSM): Top Down Design ,Problem of initial state
assignment for one hot encoding. Linked state machines. Finite State Machines (7)

5. FSM Architectures and Systems Level Design: Architectures, State machine

Designs, SPLDs Programming, Applications using MAX 7000, Design flow, Timing,
PAR. (6)

6. Digital Front End Digital Design Tools for FPGAs & ASICs: Using Mentor
Graphics EDA Tool (“FPGA Advantage”) , Design Flow Using FPGAs, Guidelines and
Case Studies of parallel adder cell, parallel adder sequential circuits, counters,
multiplexers, parallel controllers (5)

Text Books :

1. P.K.Chan & S. Mourad, Digital Design Using Field Programmable Gate Array,
jPrentice Hall (Pte), 1994.

2. S.Trimberger, Edr., Field Programmable Gate Array Technology, Kluwer

Academic Publicatgions, 1994.

Reference Books:

1. The Programmable Logic Data Books, Xilinx, 1994.

2. PLD & FPGAs from Xilinx, Altera, AMD

VL514 VLSI Layout Synthesis Algorithms

TOPICS

1. Introduction - Review of Data structures and algorithms - Review of VLSI Design

automation tools - Algorithmic Graph Theory and Computational Complexity - Tractable and
Intractable problems. (6)

2. General purpose methods for combinatorial optimization, Simulated Annealing, Genetic

Algorithm. (6)

3. Partitioning: problem formulation, classification of partitioning algorithms, Group

migration algorithms – KL and FM, simulated annealing, other partitioning algorithms. (8)

4. Placement, Floor Planning & Pin Assignment: problem formulation, simulation base
placement algorithms, other placement algorithms, constraint based floor planning, floor
planning algorithms for mixed block & cell design. General & channel pin assignment. (8)

5. Global Routing: Problem formulation, classification of global routing algorithms, Maze

routing algorithm, line probe algorithm, Steiner Tree based algorithms, ILP based
approaches. (8)

6. Detailed Routing: problem formulation, classification of routing algorithms, single layer

routing algorithms, two layer channel routing algorithms, three layer channel routing
algorithms, and switchbox routing algorithms. (8)

7. Over The Cell Routing & Via Minimization: two layers over the cell routers, constrained
& unconstrained via minimization. (4)

8. Compaction: problem formulation, one-dimensional compaction, two dimension based

compaction, hierarchical compaction. (4)

MINI-PROJECT:
Implement and evaluate one of the algorithms studied in the class. Implementation must be don
C++ and the program must be evaluated on small, medium and large benchmarks. A report sho
be submitted to the professor and a brief presentation about the results must be presented to
whole class. (One of the following algorithms may be selected: simulated annealing
partitioning, KL, FM, channel routing, two dimensional compaction, force-directed placement e

TEXT BOOK

1. Sait and Youssuf, “VLSI Design Automation.”

REFERENCE

1. N.A. Sherwani, "Algorithms for VLSI Physical Design Automation", Kluwar

Academic Publishers, 2002.
VL517 CMOS VLSI Design Lab

List of Experiments:

1. Design of a CMOS Inverter and Transmission gate. (Spice Simulation)

2. Design of a 3-input NAND gate and 3-input NOR gate. (Spice Simulation)
3. Implementation of 3-input Minority gate. (Spice Simulation)
4. Implementation of NAND and NOR gates. (Using layout editor)
5. 2 Stage Dynamic Logic implementation. (Spice Simulation)
6. Domino Logic implementation. (Spice Simulation)
7. Static flop implementation. (Spice Simulation)
8. Implementation of Dynamic flop. (Spice Simulation)
9. Implementation of Y= (A+BC)´ (Spice Simulation)
10. Design of 4X1 Multiplexer. (Using layout editor)
11. Implementation of 4-bit Full-Adder. (Using layout editor)
12. Design of a full-custom 1-bit dynamic shift register. (Using layout editor)

Software/Tools Needed:

Magic, Spice, Sun Solaris Environment, Cadence Suite of Tools, Synopsys Suite of Tools,
IRSim, ModelSim
VL518 HDL and PLD LAB
 

HDL Experiments:  

1. 4 – bit adder and subtractor using VHDL

2. 4 – bit magnitude comparator using VHDL
3. 8 – bit priority encoder using VHDL
4. 4 - Bit up/down counter with loadable count using VHDL
5. Decoder and encoder using VHDL
6. 8 bit shift register using Verilog
7. Flip flops using Verilog

PLD Experiments:

1. Design and implementing of BCD to Seven segment display using FPGA

2. Design and Implementation of ALU using FPGA.
3. Design and Implementation of digital clock using FPGA.
4. Implementation of priority encoder using FPGA
5. 4 – bit binary multiplier using CPLD

Tools and hardware required :

• Simulator : modelsim

• Synthesis: Xilinx (or) altera (or) synopsis

• FPGA, CPLD kits

 
SEMESTER – II
VL521 VLSI System Design

1. Design Methodology: Structured design strategies; Hierarchy; PLAs; Standard-cell Design;

Full-custom Design; Physical Design Styles; Design Economics. (8)

2. Datapath Subsystems: Adders; Comparators; Counters; Shifters; Multipliers; Power and

Speed Trade-off. (9)

3. Memory and Array Subsystems: SRAM, DRAM, ROM, Registers, Queues, PLAs; Memory
Peripherals; Reliability; Power dissipation in Memories. (9)

4. Interconnect: Transmission lines; RC delay models; Capacitive parasitics; Resistive

parasitics; Crosstalk; Advanced Interconnect Techniques. (5)

5. Timing: Timing classification; Timing Issues; Synchronous design; Self-timed circuit design;
Power distribution. (6)

6. Clock: Arbiters; Clock Synthesis; PLLs; Clock generation; Clock distribution; Synchronous
Vs Asynchronous Design. (6)

7. Implementation Strategies: Custom Arrays; Semicustom and Structured Arrays; Custom

circuit Design; Cell-based design methodology; Implementation platform. (7)

Mini-Project:

To implement an 8-bit RISC Microprocessor.

Text-Book: Neil Weste and K. Eshragian, “Principles of CMOS VLSI Design: A System
Perspective”

Reference Books: Jan M. Rabaey, “Digital Integrated Circuits”; Wayne Wolf, “Modern VLSI
design: System on Silicon”
VL522 LOW POWER VLSI

Introduction : Need for low power VLSI chips, Sources of power dissipation on Digital
Integrated circuits. Emerging Low power approaches, Physics of power dissipation in CMOS
devices.

Device & Technology Impact on Low Power: Dynamic dissipation in CMOS, Transistor sizing
& gate oxide thickness, Impact of technology Scaling, Technology & Device innovation

Power estimation, Simulation Power analysis: SPICE circuit simulators, gate level logic
simulation, capacitive power estimation, static state power, gate level capacitance estimation,
architecture level analysis, data correlation analysis in DSP systems, Monte Carlo simulation.

Probabilistic power analysis: Random logic signals, probability & frequency, probabilistic
power analysis techniques, signal entropy.

Low Power Design Circuit level: Power consumption in circuits. Flip Flops & Latches design,
high capacitance nodes, low power digital cells library

Logic level: Gate reorganization, signal gating, logic encoding, state machine encoding, pre-
computation logic

Low power Architecture & Systems: Power & performance management, switching activity
reduction, parallel architecture with voltage reduction, flow graph transformation, low power
arithmetic components, low power memory design.

Low power Clock Distribution: Power dissipation in clock distribution, single driver Vs
distributed buffers, Zero skew Vs tolerable skew, chip & package co design of clock network

Algorithm & Architectural Level Methodologies: Introduction, design flow, Algorithmic level
analysis & optimization, Architectural level estimation & synthesis.

TEXT BOOKS:

1. Kaushik Roy, Sharat Prasad, “Low-Power CMOS VLSI Circuit Design” Wiley,2000

2. Gary K. Yeap, “Practical Low Power Digital VLSI Design”, KAP, 2002

3. Rabaey, Pedram, “Low Power Design Methodologies” Kluwer Academic, 1999

 VL523 ANALOG VLSI DESIGN

1. Background & Introduction : Design complexities, Requirements, Challenges &

Opportunities; Basic MOS Device physics: General considerations, MOS I/V
characteristics, Second order effects, MOS device models (4)

2. Current Mirror: Basic Current Mirrors; Cascode Current mirror, Active Current mirror-
large signal Analysis, Small signal analysis, Common mode properties (4)

3. Amplifiers Design: Single stage(CS,CG,CD) Configurations, Cascade stage; frequency

response (miller effect) of CG,CS,CD; (10)

4. Differential Amplifier: Operation, Basic Differential pair; frequency response of

Cascade & Differential pair; Noise Models; Noise BW; Feedback topology (10)

5. Operational Amplifier: Op-Amp topologies, Single stage, Two stage, Cascade, Gain
BW product, Slew rate; Noise in Op-Amp; Stability & Frequency compensation. (10)

6. Bandgap reference: Supply Independent biasing, Temperature Independent Reference,

PTAT current generation; (6)

7. Switched Capacitor & Other Applications: Sampling switches, Switched Capacitor

Integrator; Oscillators; ADC, DAC; (10)
.

TEXT BOOK:

Behzad Razavi, “Design Of Analog CMOS Integrated Circuits”, Tata Mcgraw Hill,2005

REFERENCE:

“CMOS Mixed Signal Circuit Design”, Jacob Baker

VL524 VLSI TECHNOLOGY

1. Overview: overview of CMOS fabrication. Different stages of fabrication(4)

2. Environment for VLSI Technology: Clean room and safety requirements. Wafer
cleaning processes and wet chemical etching techniques. (4)

3. Impurity Incorporation: Solid State diffusion modeling and technology; Ion

Implantation modeling, technology and damage annealing; characterization of Impurity
profiles.(4)

4. Oxidation: Kinetics of Silicon dioxide growth both for thick, thin and ultra thin films.
Oxidation technologies in VLSI and ULSI; Characterization of oxide films; High k and low k
dielectrics for ULSI.(4)

5. Lithography: Photolithography, E-beam lithography and newer lithography techniques for

VLSI/ULSI; Mask generation.(3)

6. Chemical Vapour Deposition Techniques: CVD techniques for deposition of

polysilicon, silicon dioxide, silicon nitride and metal films; Epitaxial growth of silicon;
modeling and technology.(4)

7. Metal Film Deposition: Evaporation and sputtering techniques. Failure mechanisms in

metal interconnects; Multi-level metallization schemes.(5)

8. Plasma and Rapid Thermal Processing: PECVD, Plasma etching and RIE
techniques; RTP techniques for annealing, growth and deposition of various films for use in
ULSI.(6)

MINI-PROJECT :

Course project could be designing and characterizing of NMOS, PMOS, NPN, PNP, IGBT,
Double-Gate Mosfets. They have to evaluate the spice parameters. By the end they have to
present for 5-10 minutes and have to submit a report on their work.

TEXT BOOK

1. C.Y. Chang and S.M.Sze (Ed), “ULSI Technology”, McGraw Hill

Companies Inc, 1996.

REFERENCE

1. Stephena, Campbell, “The Science and Engineering of Microelectronic

Fabrication”, Second Edition, Oxford University Press, 2005.
2. Yuan Taur, Tak. H. Ning, “Fundamentals of Modern VLSI Devices”,
Cambridge University Press, 2003.
VL525 Testing of VLSI Circuits

1. Introduction to Testing - Introduction, fault modeling (6)

2. Logic & fault simulation - Simulation for design verification and testing evaluation,
Algorithms for true-value simulation, fault simulation (4)

3. Testability Measures - SCOP controllability and observability, combinational

sequential SCOAP measures (3)

4. Combinational circuit test generation Algorithms and representations, ATPG

algorithms - D- algorithm, Podem, FAN (6)

5. Sequential circuit test Generation - ATPG for single clock synchronous circuits,
Time-frame expansion methods, simulation based sequential circuit ATPG (7)

6. Memory Test - Fault modeling, marching test algorithms, NPSF (3)

7. DFT - Scan design, boundary scan design, JTAG, BIST (9)

TEXT BOOK:

1. M.L. Bushnell and V.D. Agrawal, "Essentials of Electronic Testing for Digital,

2. Memory and Mixed-Signal VLSI Circuits", Kluwar Academic Publishers, 2002

REFERENCE BOOK:

1. M. Abramovici, M.A. Breuer and A.D. Friedman, "Digital Systems and

Testable Design" Jaico Publishing House, 2002.

2. P.K. Lala, "Digital Circuit Testing and Testability", Academic Press, 2002
VL528 ANALOG DESIGN AND TECHNOLOGY LAB

Analog Design:

1. Design and analysis of different current mirrors (simple, cascade etc.) under
active loads and passive loads.

2. Design and analysis of single stage amplifiers (CS, CG and CD)

3. Design and analysis of differential amplifier.

4. Design and analysis of single stage op-amps

5. Layout and post layout simulations of single stage amplifiers(CS,CG and CD)

6. Layout and post layout simulations of differential amplifier.

7. Layout and post layout simulations of single-stage op-amps.

VLSI Technology:

1. Device Design and process simulation of diode

2. Evaluations and Characterization of the nMOS spice parameters

1. Gate-characteristics
2. Drain-characteristics
3. Characterization of Base-bias effects

3. Process simulation of the nMOS

4. If time permits process and design simulations of pMOS, other technologies

like BJT, IGBT, Double-gate MOSFETS

TOOLS:

• ngspice / Magic / Cadence IC

• Silvaco TCAD / Synopsys TCAD

VL529 VLSI Testing Lab

ATPG

1. True-value simulation and fault simulation of a combinational circuit.

2. Test generation of a combinational circuit for struck at faults.

3. Test generation of sequential circuits for struck at faults.

4. Test generation of a simple ALU for struck at faults.

5. Test generation of a simple system for struck at faults.

6. Test generation of static RAM for struck at faults.

7. Test generation for struck at faults in a FPGA device.

DFT

8. Implementation full SCAN design in sequential circuit.

9. Implementation of partial SCAN design in a sequential circuit.

10. Implementation of Boundary SCAN design.

11. Implementation of BIST.

Tools :

Synopsys : Tetramax , Design Vision

 ELECTIVE – I

VL515-A EMBEDDED SYSTEMS

1. Introduction to embedded systems-An embedded system, processor in the

system, other hardware units, software embedded in to a system, example of
embedded system, embedded (4)

2. System - On –Chip(SOC) -SOC & VLSI circuit, OS services, I/O,N/W,O/S,

real time and embedded OS (6)

3. Processor and memory organization – for Structural units in a processor,

processor selection for an embedded system, memory devices, memory
selection for an embedded system, allocation of memory to program cache
and memory management links, segment blocks and memory map of a
system, direct memory accesses(DMA),interfacing processors, memories and
input and output devices (10)

4. Devices and buses for device networks – for I/O devices, timer and counting
devices, serial communication using the “l2 C” CAN devices. (6)

5. Device drivers- device drivers, parallel port device driver in a system, serial
port device driver in a system, device driver for internal programmable timing
devices, interrupt servicing mechanism. (10)

6. Programming concepts and embedded programming in C– inter process

communication and synchronization of processes, task and threads, multiple
processors in an application, problem of sharing data by multiple tasks and
routines, inter process communication. (10)

7. Hardware-software co-design in an embedded system – for project

management, embedded system design and co-design issues in a system
development process, design cycle in the development phase for an embedded
system, use of target systems, use of software tools for development of an
embedded system design (8)

TEXT BOOK

“Embedded systems Architecture, programming and design”, by Raj Kamal

REFERENCEs

1. “Embedded system design” by Arnold S Burger, CMP;

2. “An Embedded software primer” by David Simon, PEA;
3. “Embedded system design” by Steve Heath.
 ELECTIVE – I

VL515-B VLSI DIGITAL SIGNAL PROCESSING

1. Introduction to DSP Systems : Introduction; Representation of DSP algorithms:

Block diagram, signal flow graph, Data-flow graph, Dependence graph. (4)

2. Iteration bound : Data flow graph representations, Loop bound and Iteration
bound, Longest path matrix algorithm, the minimum cycle mean algorithm,
iteration bound of multirate data-flow graphs. (6)

3. Pipelining and parallel processing : Pipelining and parallel processing of FIR

digital filters, Pipeline interleaving in digital filters: Single and Multichannel
interleaving, Pipelining and Parallel processing in 1st order and higher order IIR
digital filters, Combined Pipelining and Parallel processing for IIR filters;
Pipelining and Parallel processing for low power. (12)

4. Retiming and Unfolding: definitions & properties, retiming techniques;

Algorithm for unfolding, properties of unfolding, sample period reduction and
Parallel processing applications (10)

5. Folding : Folding transformation, Systolic Architecture design, systolic array

design methodology, FIR systolic arrays, matrix-matrix multiplications. (8)

6. Fast convolution : Cook-Toom Algorithm, Modified Cook-Toom Algorithm,

Winogard Algorithm, Iterated convolution, Cyclic convolution; (8)

7. Filters & Transforms: Algorithm strength reduction in filters & transforms:

Parallel FIR filter, Parallel Fast FIR filter, FFT. (8)s

TEXT BOOK

Keshab K.Parhi, “VLSI Digital Signal Processing Systems: Design and

Implementation”, Wiley, Inter Science,1999.

REFERENCES:

S.Y.Kung, H.J White House, T. Kailath, “VLSI And Modern Signal Processing”,
Prentice Hall,1985.
 ELECTIVE – II

VL516-A COMPUTER NETWORKING & MOBILE SYSTEMS

1. INTRODUCTION: Uses of Computer Networks, Network Hardware, Network Software,

Reference Models (OSI, TCP/IP, Novell Netware and ATM).

2. PHYSICAL LAYER: Transmission Media, Wireless Transmission, Multiplexing (FDM,

TDM, WDM), Switching. Modems

3. DATA LINK LAYER: Data Link Layer design issues, Error Detection and Correction
(Types of Error, Detection, and Error Correction), Flow and Error Control, Stop and
Wait ARQ, Go-Back-N ARQ, Selective Repeat ARQ, Sliding Window Protocols, HDLC.

4. MEDIUM ACCESS CONTROL SUBLAYER: The channel Allocation problem, Random

Access-(ALOHA, CSMA, CSMA/CD, CSMA/CA), Ethernet, Fast Ethernet, IEEE802.4,
IEEE802.5, Wireless LANs (IEEE802.11,), Bridges

5. ROUTING PROTOCOLS: Network layer Design Issues, Routing Algorithms – (Shortest

Path Routing, Flooding, Distance Vector Routing, Link State Routing, Hierarchical
Routing, Broadcast Routing, Multicast Routing).

6. Wireless Networking(2G): GSM architecture: Mobile station, base station system,

Network and switching sub system, Radio interface, Location tracking and Call set up,
GSM Short message services –architecture, IS-95 architecture.

7. Wireless Networking (3G): Mobile services(2.5G) : GPRS: GPRS functional groups,

GPRS architecture. WAP : WAP model, WAP gateway, WAP Protocol. Mobile Services(3G)
Paradigm shifts in 3G systems CDMA 2000: Introduction, CDMA 2000 layering
structure, Upper layer, Link layer, W-CDMA

TEXT BOOKS

1. A.S Tanenbaum, “Computer Networks”, 4th Edition, Pearson

2. Theodore S. Rappaport, Wireless Communications Principles and Practice, 2nd Edition,
Pearson Education, 2003

REFERENCES
1. Gary R. Wright, W. Richard Stevens “TCP/IP Illustrated, Volume 2: The
Implementation”, Addison Wesley
2. W. Richard Stevens, ” TCP/IP Illustrated, Volume 1: The protocols ”, Addison Wesley
3. William Stallings, “Data and Computer Communications”, Seventh Edition,Pearson
Education
 ELECTIVE – II

VL516-B COMPUTER ARCHITECTURE AND PARALLEL PROCESSING

1. PRINCIPLES OF PARALLEL PROCESSING: Multiprocessors and Multicomputers

– Multivector and SIMD Computers- PRAM and VLSI Models- Conditions of
Parallelism- Program Partitioning and scheduling-program flow mechanisms- parallel
processing applications- speed up performance law.

2. PROCESSOR AND MEMORY ORGANIZATION: Advanced processor technology

– Superscalar and vector processors- Memory hierarchy technology- Virtual memory
technology- Cache memory organization- Shared memory organization.

3. PIPELINE AND PARALLEL ARCHITECTURE: Linear pipeline processors- Non

linear pipeline processors- Instruction pipeline design- Arithmetic design- Superscalar
and super pipeline design- Multiprocessor system interconnects- Message passing
mechanisms.

4. VECTOR, MULTITHREAD AND DATAFLOW ARCHITECTURE : Vector

Processing principle- Multivector Multiprocessors- Compound Vector processing-
Principles of multithreading-fine grain multicomputers- scalable and multithread
architectures – Dataflow and hybrid architectures.

5. SOFTWARE AND PARALLEL PROCESSING : Parallel programming models-

parallel languages and compilers- parallel programming environments- synchronization
and multiprocessing modes- message passing program development- mapping programs
onto multicomputers- multiprocessor UNIX design goals- MACH/OS kernel architecture-
OSF/1 architecture and applications.

TEXT BOOK:

1. Kai Hwang, Advanced Computer Architecture, TMH 2001.

REFERENCES :

1. William Stallings, Computer Organization and Architecture, McMillan Publishing

Company, 1990.
2. M.J. Quinn, Designing efficient Algorithms for parallel computer, McGraw Hill
International, 1994.
 ELECTIVE – III

VL526-A Logic Synthesis Algorithms

1. Introduction – Review of Boolean algebra, laws of Boolean algebra, don’t care conditions,
implicants and prime-implicants, minimal SOP expressions, review of the K-map method for
minimization, Overview of logic synthesis algorithms, Interaction between logic and layout
synthesis. (6)

2. Introduction to Two Level Minimization – Quine-McClusky method, cover tables, MINI

logic minimization algorithm, Theory of Unate functions, Tautology checking using unite
function, complementation using unite function. (7)

3. ESPRESSO Algorithms: ESPRESSO exact minimization, ESPRESSO cover table method

using branch-and-bound heuristic, EXPRESSO heuristic minimization. (6)

4. Minimization of Multi-Output Functions: Common implicants, extensions to MINI and

ESPRESSO methods for multi-output functions. (3)

5. Multi-Level Minimization: Representation of multi-level networks, Algebraic factorization,

heuristic multi-level minimization. (4)

6. Minimization of Finite State Machines: State encoding, input encoding, output encoding,
optimal encodings, equivalent states, FSM minimization. (4)

7. Synchronous Retiming: Synchronous networks, retiming of synchronous networks,

optimal retiming, peripheral retiming, interplay between retiming and resynthesis. (4)

8. Technology Mapping or Cell Binding: Canonical representation of library cells and subject
netlists, DAG cover problem, optimal DAG covering, optimal covering subject to timing
constraints, other coverings. (4)

MINI-PROJECT:
Implement and evaluate one of the algorithms studied in the class. Implementation must be don
C++ and the program must be evaluated on small, medium and large benchmarks. A report sho
be submitted to the professor and a brief presentation about the results must be presented to
whole class. (One of the following algorithms may be selected: unite tautology checking, F
minimization, synchronous retiming etc.)

TEXT BOOK

1. Srinivas Devadas et al., “Logic Synthesis.”

REFERENCE

1. Gary Hachtel and Fabio Somenzi, "Logic Synthesis", Kluwar Academic Publishers.
 ELECTIVE – III

VL526-C Advanced Topics in VLSI

Selection of topics varies from year to year. Following is a sampling of topics:

1. Frequency scaling methods.

2. Voltage scaling methods.

3. Multi-threshold designs.

4. Process variations and methods to cope with process variations.

5. Self-timed systems.

6. Opto-electronic systems.

7. Advanced technologies. SOI, GaAs etc.

TEXT BOOK

No text books. Various selections from literature will be provided.