06

6.
Synchronous Sequential Logic 6-1
Chapter 6. Synchronous Sequential Logic
Introduction
x Combinational y
(I/P) (O/P) x NS Memory O/P
Circuit y
(I/P) q’ Elements
Memory Logic Logic (O/P)
q q’ q (NS)
(PS) (NS) Elements (PS)
Mealy’s Model Moore’s Model
Figure 1: Synchronous sequential circuit models.
✯ A sequential circuit is a logic circuit that employ memory elements in addi-

tion to (combinational) logic gates.
✏ Their outputs are determined from the state of the memory cells (as well
as the present input combination).
✏ The state of the memory elements, in turn, is a function of the previous
inputs (and the previous state).
✏ Its behavior therefore is specified by a time sequence of inputs and inter-
nal states.
✯ The binary information stored in the memory elements (flip-flops) at any
given time defines the state of the sequential circuit.
✯ An asynchronous sequential circuit changes their states and output values
whenever a change in input values occurs.
✏ Its behavior depends on the order in which its input signals change and
can be affected at any time.
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
6. Synchronous Sequential Logic 6-2
✯ A synchronous sequential circuit changes their states and output values at

fixed points of time, which are specified by the rising and/or falling edge of
a free-running clock signal.
✏ Its behavior is defined at discrete instants of time.
✏ Synchronization usually is achieved by a timing device called a clock
generator, which generates a periodic train of clock pulses distributed
throughout the system to trigger the memory elements.
✏ A synchronous sequential circuit can be modeled by a finite state ma-
chine (FSM):
M = ( x; y; q; f; h);
where f : x q ! y (the Mealy machine) or f : q ! y (the Moore
machine) is the output function, and h : x q ! q0 is the next-state
function. Note that q0 (t) = q(t + 1).
Clock period
Clock Rising edge

width Falling edge
Figure 2: Clock signal [Gajski].
✯ Clock period: time between successive transitions in the same direction (mea-
sured in ms, ns, or ps).
✯ Clock frequency: the reciprocal of clock period (measured in KHz, MHz, or
GHz).
✯ Clock width: time during which the clock signal is high (value is 1).
✩ A clock signal is active high if the state changes occur at the clock’s
rising edge or during the clock width. It is active low otherwise.
✯ Clock duty cycle: ratio of clock width and clock period.
SR Latch
✯ The SR latch is a basic memory element which can store one bit of informa-
tion.
✩ It consists of two cross-coupled NOR gates or two cross-coupled NAND
gates.
✩ It has two input signals, the set signal (S ) and the reset signal (R).
✩ It has two output signals, Q and Q0 .
✩ It has two states, the set state (when Q = 1 and Q
0 = 0 ) and the reset
state (when Q = 0 and Q0 = 1).
☞ In the NOR-type SR latch, if S ,

= R = 1 Q = Q = 0
0 .
✏ If, subsequently, both S and R are disasserted at the same time, the out-
put would be unpredictable.
✍ It is delay dependent.
✍ The latch can oscillate (if both NOR gates have the same delay).
✍ The oscillation is called critical race.
✏ Normally, we prohibit the input combination S = R = 1 to avoid the
problem.
✍ Q and Q0 are then always complementary to each other.
☞ In the NAND-type SR latch, if S ,
= R = 0 Q = Q = 1
0 .
✏ If, subsequently, both S and R are asserted at the same time, the output
would be unpredictable.
✏ Normally, we prohibit the input combination S = R = 0 to avoid the
problem.
✍ Q and Q0 are then always complementary to each other.
S R Q Q (next) Q’(next)
S 1.4 Q’
0 0 0 0 1
0 0 1 1 0
0 1 X 0 1
1.4 Q 1 0 X 1 0
R
1 1 X 0 0
(a) Logic schematic (c) Truth table
1.4
1.4
1.4 Undefined
Q 2.8 2.8
1.4
Q’ 1.4 1.4 1.4

Undefined
2.8 2.8
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10
(b) Timing diagram

S R Q Q (next) Q’(next)
S 1.4 Q
0 0 X 1 1
0 1 X 1 0
1 0 X 0 1
1.4 Q’ 1 1 0 0 1
R
1 1 1 1 0
(a) Logic schematic (c) Truth table
1.4 1.4 1.4 Undefined

Q 2.8 2.8 1.4
1.4 Undefined
Q’ 2.8 2.8 1.4 1.4
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10
(b) Timing diagram
Figure 3: NOR-type and NAND-type SR latches [Gajski].
Gated SR Latch (Clocked SR Latch)
✯ The gated SR latch is one that has a third input, C (usually the clock signal),
which enables or disables the SR latch (see Fig. 4).
✯ The designer must make sure that the input signals do not change during the
time window around the falling edge of C .
✏ The window starts at setup time tsetup before the falling edge of C and
ends with hold time thold after the falling edge of C .
✏ In Fig. 5, e.g., the following conditions must hold for C :
t12 t11 tsetup
t13 t12 thold
C S R Next state of Q
S
• • • Q 0 X X No change
1 0 0 No change
C • 1 0 1 Q = 0; Reset state
1 1 0 Q = 1; Set state
• • • Q 1 1 1 Undefined
R
(a) Logic diagram (b) Function table
Fig. 4-7 SR Latch with Control Input
Figure 4: Gated SR latch (NAND-type) [Mano & Kime].
C S R Q Q (next)
0 X X 0 0
R 0 X X 1 1
2.0 Q
S Q 1 0 0 0 0
C C
1 0 0 1 1
R Q’
2.0 Q’ 1 0 1 X 0
S
1 1 0 X 1
1 1 1 X NA
(a) Graphic symbol (b) Logic schematic (c) Truth table
reset state set state reset state
2.0
2.0
Q 4.0 4.0
t0 t1 t2 t3 t4 t5 t6 t7 t8 t 9 t 10 t 11 t 12 t 13
(d) Timing diagram
Figure 5: Gated SR latch (NOR-type) [Gajski].
Gated D Latch
✯ The gated D latch has only one input D (the data input).
✩ Constructed from a gated SR latch by connecting the D input to S and
0
D to R.
✩ Avoiding S = R = 1 (for NOR-type latch).
D C D Q Q (next)
2.0 Q 0 X 0 0
D Q
C
0 X 1 1
C Q’ 1 0 X 0
2.0 Q’
1 1 X 1
(a) Graphic symbol (b) Logic schematic (c) Truth table
reset state set state reset state
3.0
3.0
Q 4.0 4.0
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
t t t t t t
setup hold setup hold setup hold
(d) Timing diagram
Figure 6: Gated D latch [Gajski].
Flip-Flops
☞ A latch which is enabled whenever C = 1 is called a level-sensitive latch (or

level-triggered latch).
☞ At any point during that time, any input changes will propagate to the output
(with some small delay), causing erroneous shifting as shown below.
✏ Solutions: master-slave and edge-triggered flip-flops.
✏ A flip-flop (FF) responds to input changes only during the transition in
C.
X Y
D Q1 D Q2 D Q3
C C C
Clk
(a) Logic schematic
Q1 4.0 3.0
Q2 4.0 3.0
Q3 4.0 3.0
t0 t1 t2 t3 t4 t5 t6 t7
(b) Timing diagram
Figure 7: Erroneous shifting with D latches [Gajski].
✯ A master-slave flop-flop is implemented with two latches—a master latch and

a slave latch.
✩ The input to the master latch is the input to the FF.

✩ The input to the slave latch is the output from the master latch.
✩ The output from the slave latch is the output of the FF.
✯ Both latches are driven by the same clock signal, C lk .
✩ The master latch is enabled iff C lk = 0 .
✩ The slave latch is enabled iff C lk = 1 .
✯ Advantage: the FF is never transparent.
Master Slave
latch latch
D D Qm D Qs Q
4.0/3.0 4.0/3.0
C C
Clk
(a) Logic schematic
Clk
Qm 4.0 3.0 5.0 3.0
Qs 4.0 3.0 4.0
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
(b) Timing diagram
Figure 8: Master-slave flip-flop [Gajski].
Master−slave flip−flop Master−slave flip−flop Master−slave flip−flop

X Y
D Q 1m D Q 1s D Q 2m D Q 2s D Q3m D Q3s
C C C C C C
Clk
(a) Logic schematic
Q1m 4.0 3.0
Q1s 4.0 3.0
Q2m 5.0 3.0
Q2s 4.0 3.0
Q3m 5.0 3.0
Q3s 4.0
t0 t1 t2 t3 t4 t5 t6 t7
(b) Timing diagram
Figure 9: Shifting with master-slave flip-flops [Gajski].
✯ An edge-triggered FF is implemented with three interconnected SR latches:

set, reset, and output latches.
✩ Positive-edge-triggered FF (0-to-1 transition)
✩ Negative-edge-triggered FF (1-to-0 transition)
Set latch
A
1.4
S
1.4 1.4 Q
Clk
R
1.4 1.4 Q’
Output latch
D 1.4 B
Reset latch
(a) Logic schematic
Clk
A 2.8 2.8 4.2 2.8
S 1.4 1.4 1.4 1.4
R 1.4 1.4
B 1.4 1.4 2.8 1.4
Q 2.8 4.2
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
(b) Timing diagram
Figure 10: Edge-triggered flip-flop [Gajski].
Table 1: Flip-flop types [Gajski].

Flip−flop Flip−flop Characteristic Characteristic Excitation
name symbol table equation table
S R Q (next) Q Q(next) S R
0 0 Q 0 0 0 X
S Q
Q (next) = S + R’Q
Clk 0 1 0 0 1 1 0
SR
SR = 0
R Q’ 1 0 1 1 0 0 1
1 1 NA 1 1 X 0
J K Q (next) Q Q(next) J K
0 0 Q 0 0 0 X
J Q
Clk 0 1 0 Q (next) = JQ’+ K ’Q 0 1 1 X
JK
K Q’ 1 0 1 1 0 X 1
1 1 Q’ 1 1 X 0
Q Q(next) D
0 0 0
D Q (next)
D Q 1
0 1
Clk 0 0 Q (next) = D
D
1 0 0
Q’ 1 1
1 1 1
Q Q(next) T
0 0 0
T Q (next)
T Q 0 1 1
0 Q
T Clk Q (next) = TQ ’+ T ’Q
1 0 1
Q’ 1 Q’
1 1 0
Flip-Flop Types
☞ We assume only positive (rising) edge-triggered FFs.

✏ SR (set-reset), JK, D (data), and T (toggle) FFs are the four major FFs
commonly used.
☞ The characteristic table gives for every input and state combination before
the rising edge of C lk the corresponding state of the FF after the falling edge
of C lk .
✏ A characteristic equation for each FF can be derived from the character-
istic table using the map method.
☞ The excitation table is derived from the characteristic table by transposing
input and output columns.
✏ It gives the value of the FF inputs that are necessary to change the FF’s
present state to the desired next state.
Table 2: State diagrams for various flip-flops [Gajski].

Flip−flop
name State diagram
S,R = 1,0
S,R = 0,0 S,R = 0,0
SR Q=0 Q=1
S,R = 0,1
J,K = 1,0 or 1,1

J,K= 00 J,K = 0,0
JK Q=0 Q=1
J,K = 0,1 or 1,1
D=1
D= 0 D= 1
D Q=0 Q=1
D=0
T=1
T= 0 T= 0
T Q=0 Q=1
T=1
✯ A flip-flop can have asynchronous inputs: P RS (preset) and C LR (clear or

reset).
✏ They are used to preset and clear the FF independently of other inputs.
✏ They are not controlled by the clock signal.
CLR
D
Q PRS
D Q
C
Clk Q’
Q’ CLR
PRS
(a) D latch (b) Graphic symbol
Set latch
PRS
A
S
Q PRS
D Q
Clk
R Clk Q’
Q’
CLR
Output latch
D B
CLR
Reset latch
(c) D edge−triggered flip−flop (d) Graphic symbol
Figure 11: D flip-flop with asynchronous inputs [Gajski].
Analysis of Sequential Logic
☞ The analysis of a sequential circuit consists of obtaining a table or a diagram

for the time sequence of inputs, outputs, and internal states: the state table or
the state diagram.
☞ It is also possible to write Boolean expressions including the necessary time
sequence.
☞ The same information available in a state table can be represented graphically
in a state diagram.
✏ A state diagram is a directed graph, where each node represents a unique
state, and each arc a unique state transition.
✏ The derivation of a state diagram from a state table (and vice versa) is
unique so far as isomorphism is concerned (thus can be reversed).
Given a logic schematic, the analysis procedure is as follows:
1. Derive excitation equations

2. Derive next-state and output equations
3. Generate next-state and output tables
4. Generate state diagram
5. Develop timing diagram
6. Simulate logic schematic
Cnt
D0 Q0
Q’0
D1 Q1
Q’1
Clk
(a) Logic schematic
D0 = Cnt + Q0 = Cnt’Q0 + Cnt Q0’
D1 = Cnt’Q1 + Cnt Q1’Q0 + Cnt Q1 Q0’
(b) Excitation equation
Q0 (next) = D0 = Cnt’Q0 + Cnt Q0’
Q1 (next) = D1 = Cnt’Q1 + Cnt Q1’Q0 + Cnt Q1 Q0’
(c) Next−state equations
Present state Next state

Q1 Q0 Q1 (next) Q0 (next)
Cnt = 0 Cnt = 1
0 0 0 0 0 1
0 1 0 1 1 0
1 0 1 0 1 1
1 1 1 1 0 0
(d) State table
Figure 12: Analysis of a modulo-4 counter [Gajski].
Cnt = 0 Cnt = 0
Cnt = 1
Q1 Q0 = 00 Q1 Q0 = 01
Cnt = 1 Cnt = 1
Cnt = 0 Cnt = 0
Cnt = 1
Q1 Q0 = 11 Q1 Q0 = 10
(e) State diagram
clock cycle 1 clock cycle 2 clock cycle 3 clock cycle 4
Clk
Cnt
Q1
Q0
t0 t1 t2 t3 t4 t5
(f) Timing diagram
Figure 13: Analysis of a modulo-4 counter (cont’d) [Gajski].
Cnt
D0 Q0 Y
Q’0
D1 Q1
Q ’1
Clk
(a) Logic schematic
Y = Q1 Q0
(c) Next−state and output equations
Present state Next state Outputs

Q1 Q0 Q1 (next) Q0 (next) Y
Cnt = 0 Cnt = 1
0 0 0 0 0 1 0
0 1 0 1 1 0 0
1 0 1 0 1 1 0
1 1 1 1 0 0 1
(d) State and output table
Figure 14: Analysis of a state-based (Moore) modulo-4 counter [Gajski].
Cnt = 0 Cnt = 0
Q1 Q0 = 00 Cnt = 1 Q1 Q0 = 01
Y=0 Y=0
Cnt = 1 Cnt = 1
Cnt = 0 Cnt = 0
Q1 Q0 = 11 Cnt = 1 Q1 Q0 = 10
Y=1 Y=0
(e) State diagram
Clk
Cnt
Q1
Q0
t0 t1 t2 t3 t4 t5
(f) Timing diagram
Figure 15: Analysis of a state-based (Moore) modulo-4 counter (cont’d) [Gajski].
Cnt
D0 Q0 Y
Q’0
D1 Q1
Q ’1
Clk
(a) Logic schematic
Y = Cnt Q1 Q0
(c) Next−state and output equations
Present state Next state / Outputs

Q1 Q0 Q1 (next) Q0 (next) / Y
Cnt = 0 Cnt = 1
0 0 0 0/0 0 1/0
0 1 0 1/0 1 0/0
1 0 1 0/0 1 1/0
1 1 1 1/0 0 0/1
(d) State and output table
Figure 16: Analysis of a input-based (Mealy) modulo-4 counter [Gajski].
Cnt = 0/Y = 0 Cnt = 0/Y = 0

Cnt = 1/Y = 0
Q1 Q0 = 00 Q1 Q0 = 01
Cnt = 1/Y = 1 Cnt = 1/Y = 0
Cnt = 0/Y = 0 Cnt = 0/Y = 0

Cnt = 1/Y = 0
Q1 Q0 = 11 Q1 Q0 = 10
(e) State diagram
Clk
Cnt
Q1
Q0
t0 t1 t2 t3 t4 t5
(f) Timing diagram
Figure 17: Analysis of a input-based (Mealy) modulo-4 counter (cont’d) [Gajski].
Synthesis of Sequential Logic

Design description
or timing diagram
Develop
state diagram
Generate next−state
and output tables
Minimize
states
Encode inputs,
states, outputs
Derive next−state and

output equations
Choose
memory elements
Derive excitation
equations
Optimize
logic implementation
Derive logic schematic

and timing diagrams
Simulate
logic schematic
Verify functionality
and timing
Figure 18: Synthesis procedure for FSM models [Gajski].
FSM Model (State Diagram) Capture
✯ Consider a modulo-3 up/down counter.

✩ Two inputs: count enable (C ) and count direction (D).
➣ When C = 0 , it stops counting.
➣ When C = 1 , it counts up if D = 0 and down if D = 1 .

✩ One output: Y = 1 when the counter reaches 2 while counting up or 0
while counting down.
CD = 10
CD = 10 CD = 10
D Y u0 u1 u2
Modulo−3
C up/down
Clk counter
CD = 11 CD = 11
d0 d1 d2
CD = 11
(a) Counter symbol (b) Partial state diagram (up and down counting)
CD = 10
CD = 10 CD = 0X CD = 0X CD = 0X
CD = 10 CD = 10 CD = 10 CD = 10
u0 u1 u2 u0 u1 u2
11 11
=
10
= CD
10
CD D D
CD = 10 C
=
CD = 10 C
=
= 1
CD
=1
= 1
CD = 1
CD
=1
CD = 1
10
1
10
1
CD
CD
CD = 11 CD = 11 d0 CD = 11 d1 CD = 11 d2
d0 d1 d2
CD = 11
CD = 0X CD = 0X CD = 0X
CD = 11
(c) Partial state diagram (changing direction) (d) Final state diagram
Figure 19: State diagram for a modulo-3 counter [Gajski].
Example 1 (State Diagram for the BCD-to-Excess-3 Decoder)
✯ The inputs are applied serially, with LSB first, and the outputs are generated
serially, too.
TABLE 4-6
Sequence Tables for Code Converter Example
Sequences in Order of Digits Represented Sequences in Order of Common Prefixes
BCD Input Excess-3 Output BCD Input Excess-3 Output
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0
1 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1
0 1 0 0 1 0 1 0 0 0 1 0 1 1 1 0
1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 0
0 0 1 0 1 1 1 0 0 1 1 0 1 0 0 1
1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0
0 1 1 0 1 0 0 1 1 0 0 1 0 0 1 1
1 1 1 0 0 1 0 1 1 0 1 0 0 0 0 1
0 0 0 1 1 1 0 1 1 1 0 0 0 1 1 0
1 0 0 1 0 0 1 1 1 1 1 0 0 1 0 1
Table 4-6 Sequence Tables for Code Converter Example
Init Init
0/1 1/0 0/1 1/0
B1=0 B1=1 B1=0 B1=1
0/1 1/0 0/0 or 1/1

(a)
B2=0 B2=1 B2=X
(b)
Init Init
0/1 1/0 0/1 1/0

0/1 or 1/1 0/1 or 1/1
B1=0 B1=1 B1=0 B1=1

0/0 or 1/1 0/0 or 1/1
0/1 1/0 0/0 or 1/1 0/1 1/0 0/0 or 1/1
B2=0 B2=1 B2=X B2=0 B2=1 B2=X
0/0 or 1/1
0/1 1/0
1/0
0/1
B3=0 B3=1 B3=0 B3=1
(c) (d)
Fig. 4-22 Construction of a State Diagram
State Minimization
☞ We would like to reduce the number of gates and FFs during the design of a
sequential circuit (they sometimes are competing objectives).
✏ The number of gates and the number of inputs per gate for the next state
and output functions can be reduced by state minimization.
✏ The number of FFs required is directly related to the number of states of
the FSM.
✍ For an FSM with m states, we would need dlog2 me FFs.
0/0
a NS O/P
PS 0 1 0 1
0/0
1/0 0/0 a a b 0 0
0/0 0/0
b c b c d 0 0
1/0 c a d 0 0
1/0
0/0 d e f 0 1
g 1/1 d e
e a f 0 1
1/1
0/0 f g f 0 1
1/1
f g a f 0 1
1/1
t 0 1 2 3 4 5 6 7 8 9 10 11
q a a b c d e f f g f g a
x 0 1 0 1 0 1 1 0 1 0 0
y 0 0 0 0 0 1 1 0 1 0 0
Figure 20: An FSM example.
✍ Given the FSM as shown above, can we find an equivalent FSM with fewer than
7 states?
Definition 1
Two FSMs are said to be (behaviorally) equivalent if given any input sequence,
starting from any identical initial state, they produce the same output sequence.
Definition 2
Two states, sj and sk , in an FSM are said to be equivalent, denoted as sj sk , iff
1. 8 2x
i ; h(sj ; i) = h(sk ; i) ;
2. 8 2 x
i ; f (sj ; i) = f (sk ; i) .
➀ Find rows in the state table that have identical NS and O/P entries. They
correspond to equivalent states. If there are no equivalent states, stop.
➁ When 2 states are equivalent, one of them can be removed. Update the entries
of the remaining table to reflect the change. Go to ➀.
NS O/P NS O/P NS O/P

PS 0 1 0 1 PS 0 1 0 1 PS 0 1 0 1
a a b 0 0 a a b 0 0 a a b 0 0
b c d 0 0 b c d 0 0 b c d 0 0
c a d 0 0 c a d 0 0 c a d 0 0
d e f 0 1 ➁ d e df 0 1 d e d 0 1
e a f 0 1 e a df 0 1 e a d 0 1
f g f 0 1 f ge f 0 1
g a f 0 1 ➀ g a f 0 1
t 0 1 2 3 4 5 6 7 8 9 10 11
q a a b c d e d d e d e a
x 0 1 0 1 0 1 1 0 1 0 0
y 0 0 0 0 0 1 1 0 1 0 0
☞ The same output sequence results although the state sequence is different.
☞ Note that in either machine, 3 FFs are required to represent the states.
☞ Three FFs can represent up to 8 states. Unused states are treated as don’t-
cares.
☞ In general, reducing the state table is likely (but does not guarantee) to result
in a smaller number of FFs or gates.
Present Next−state
state
CD = 0X CD = 10 CD = 11
u0 u0/0 u1/0 d2/1

u1 u1/0 u2/0 d0/0
u2 u2/0 u0/1 d1/0
d0 d0/0 u1/0 d2/1
d1 d1/0 u2/0 d0/0
d2 d2/0 u0/1 d1/0
(a) Initial state table
{u 0 , u1 , u2 , d 0 , d1 , d2 }
CD = 0X 0 0 0 0 0 0
Output
10 0 0 1 0 0 1 values
11 1 0 0 1 0 0
001 000 010

G0 = {u0 , d0 } G1 = {u 1 , d1 } G 2 = {u 2 , d2 }
CD = 0X G0 G0 G1 G1 G2 G2
Next
10 G1 G1 G2 G2 G0 G0 states
11 G2 G2 G0 G0 G1 G1
(b) Partitioning into equivalence classes
Present Next−state
state
CD = 0X CD = 10 CD = 11
s0 s0 / 0 s1 / 0 s2/ 1
s1 s1 / 0 s2 / 0 s0/ 0
s2 s2 / 0 s0 / 1 s1/ 0
(c) Final next−state/output table
Figure 21: State reduction for the modulo-3 counter [Gajski].
✯ Equivalence classes of states also can be obtained by an implication table.

✏ A triangular table in which every entry represents a specific pair of states.
✏ Every pair of states is assigned one entry in the table.
s 1
s 2
s 3
s 4
<s2 , s6 >
s 5 <s3 , s4 >
<s0 , s4 >
s 6
s 0 s 1
s 2
s 3
s 4
s 5
Figure 22: An implication table [Gajski].
➀ Enter a for every pair of states that differ in their output values for at least
one set of input values.
☞ Pairs of states that are not equivalent are eliminated.
➁ For the remaining pairs of states, enter into each entry the next-state pairs
that would have to be equivalent if the pair of states represented by the entry
are to be equivalent.
☞ The equivalence of the next-state pair is implied.
☞ For example, the equivalence of < s1 ; s5 > implies the equivalence of
< s3 ; s4 >.
➂ Scan the table from top to bottom one row at a time, and from left to right
one column at a time, and enter a into any square having at least one
nonequivalent next-state pair.
☞ May be iterated several times until no ’s are entered during the table
scan.
☞ All the noncrossed entries represent equivalent pairs.

➃ Group the equivalent states into equivalent classes.
☞ If si sj and sj sk , then si sk .
Present Next−state / Output

state
CD = 0X CD = 10 CD = 11
u0 u0/0 u1/0 d2/1

u1 u0/0 u2/0 d0/0
u2 u2/0 u0/1 d1/0
d0 d0/0 u1/0 d2/1
d1 d2/0 u2/0 d0/0
d2 d2/0 u0/1 d1/0
(a) Next−state and output table
u1
u2
d0
d1 <u 0 , d 2 >
d2
u 0
u 1
u2 d0 d1
(b) Implication table
Figure 23: Reduction using the implication table [Gajski].
State Encoding (Assignment)

NS O/P NS O/P PS I/P NS O/P
PS 0 1 0 1 q ass-1ass-2ass-3 PS 0 1 0 1 ABC x ABC y
a a b 0 0 a 001 000 000 001 001 010 0 0 000 0 XXX X
000 1 XXX X
b c d 0 0 b 010 010 100 010 011 100 0 0 001
001
0
1
001
010
0
0
c a d 0 0 c 011 011 010 011 001 100 0 0 010 0 011 0
010 1 100 0
d e d 0 1 d 100 101 101 100 101 100 0 1 011
011
0
1
001
100
0
0
e a d 0 1 e 101 111 011 101 001 100 0 1 100 0 101 0
100 1 100 1
101 0 001 0
101 1 100 1
110 0 XXX X
110 1 XXX X
111 0 XXX X
111 1 XXX X
☞ Different state encodings (assignments) result in different (combinational)

circuits for the intended FSM.
✏ Different costs and delays.
✏ There are at least n! different ways to encode n states.
☞ There is no easy state-encoding procedure that guarantees a minimal-cost or
minimal-delay combinational circuit.
✏ Exploration of all possibilities is impossible.
✏ Heuristics are often used.
✍ Minimum-bit change: assigns Boolean values to the states in such
a way that the total number of bit changes for all state transitions is
minimized.
✍ Prioritized adjacency: assigns adjacent encodings, which differ in
one bit only, to all states that have a common source, destination, or
output.
1. The highest priority is given to states that have the same next state
for a given input value.
2. The second priority is given to the next states of the same state.
3. The third priority is given to states that have the same output
value for the same input values.
✍ One-hot encoding: uses redundant encoding in which one FF is as-

signed to each state.
1 1
00 01 00 01
2 2 1 1
1 1
11 10 10 11
(a) Straight−forward encoding (b) Minimum−bit−change encoding
Figure 24: Two different encodings for a 2-bit binary counter [Gajski].
0/0 0/0
s0 s1 01 11
Priority 1: (s1 , s2 )
0/1, 1/1 Priority 2: (s1 , s 2 ) 0/1, 1/1

0/0 1/0 0/0 1/0
Priority 3: (s0 , s1 ), (s2 , s3 )
0/1 0/1
s3 s2 00 10
(a) Initial state diagram (b) Adjacency priorities (c) Possible encoding
Figure 25: Encodings based on prioritized adjacency [Gajski].
Encoding A Encoding B Encoding C

Q1 Q 0 Q1 Q 0 Q 2 Q1 Q0
s0 0 0 0 1 0 0 1
s1 0 1 0 0 0 1 0
s2 1 0 1 0 1 0 0
Figure 26: Some encodings for modulo-3 counter [Gajski].
CD
Q1 Q0 00 01 11 10 00 01 11 10
00 0 0 0 0 1 0 0 1 00 0 0 1 0
01 0 1 0 1 0 0 1 0 01 0 0 0 0
11 XX XX XX XX 11 X X X X
10 1 0 1 0 0 1 0 0 10 0 0 0 1
Q1 (next) Q0 (next) Y
(a) Next−state map (b) Output map
Q1 (next) = Q C ’+ Q C D’+ Q’Q0’C D

10 1
Q0 (next) = Q C + Q C D + Q’Q0’C D’
0
0 1
Y = Q1 C D + Q’1 Q0’C D
(c) Excitation and output equations
1.4 1.4
Q1 (next) Q0 (next)
1.8
Y
1.8 1.8 1.8 1.8 1.4
2.2
2.2 2.2
Cost (Q 1 ) = 24 Cost (Q 0 ) = 24 Cost (Y) = 18

Delay (Q 1 ) = 4.0 Delay (Q 0 ) = 4.0 Delay (Y) = 3.6
(d) Cost and delay estimation
Figure 27: Cost and delay estimation for encoding A [Gajski].
CD
Q1 Q0 00 01 11 10 00 01 11 10
00 0 0 0 0 0 1 1 0 00 0 0 0 0
01 0 1 0 1 1 0 0 0 01 0 0 1 0
11 XX XX XX XX 11 X X X X
10 1 0 1 0 0 0 0 1 10 0 0 0 1
Q1 (next) Q0 (next) Y
(a) Next−state map (b) Output map
Q1 (next) = Q C ’+ Q C D + Q’Q0’C D’
1 0 1
Q0 (next) = Q C ’+ Q C D’+ Q’Q0’C D

0
0 1
Y = Q1’C D + Q0’C D
1.4 1.4
Q1 (next) Q0 (next)
1.8
Y
1.8 1.8 1.8 1.8 1.4
1.8
2.2 2.2
Cost (Q 1 ) = 24 Cost (Q 0 ) = 24 Cost (Y) = 16

Delay (Q 1 ) = 3.6 Delay (Q 0 ) = 3.6 Delay (Y) = 3.2
Figure 28: Cost and delay estimation for encoding B [Gajski].
CD
Q2 Q1 Q0 00 01 11 10 00 01 11 10
000 X X X X X X X X X X X X 000 X X X X
001 0 0 1 0 0 1 1 0 0 0 1 0 001 0 0 1 0
010 0 1 0 0 1 0 0 0 1 1 0 0 010 0 0 0 0
100 1 0 0 1 0 0 0 1 0 0 0 1 100 0 0 0 1
Q2 (next) Q1 (next) Q0 (next) Y
(a) Next−state table (b) Output table
Q2 (next) = Q C ’+ Q C D + Q C D’
2 0 1
Q1 (next) = Q C ’+ Q2 C D + Q0 C D’
1
Q0 (next) = Q C’+ Q2 C D’+ Q C D

0 1
Y = Q0 C D + Q2 C D’
1.4
Q2 (next) 1.8
1.8 1.8 Q1 (next) 1.4 Y

Q0 (next) 1.8
1.8
Cost (Q ) = Cost (Q ) = Cost (Q ) = 22 Cost (Y) = 16

0 1 2
Delay (Q 0 ) = Delay(Q 1 ) = Delay (Q 2) = 3.6 Delay (Y) = 3.2
Figure 29: Cost and delay estimation for encoding C [Gajski].
Choice of Memory Elements
☞ After state minimization and state encoding, we choose the proper type of FF
for implementation.
☞ Given the state transition table, we wish to find the FF input conditions that
will cause the required transitions.
✏ A tool for such a purpose is the excitation table, which can be derived
from the characteristic table (or equation).
✏ SR FFs are generally used when different signals set and reset the FFs.
✏ D FFs are good for applications requiring data transfer (e.g., shift regis-
ters).
✏ T FFs are good for those involving complementation (e.g., binary coun-
ters).
✏ Many digital systems are constructed entirely with JK FFs because they
are the most versatile available.
✍ JK is useful when we need to combine the behavior of T and SR.
✏ The excitation table for the JK flip-flop has many don’t-cares, which are
more likely to result in simpler combinational circuits.
An example using SR FFs:

PS I/P NS O/P
Q Q+ S R ABC x ABC y SA SB SC RA RB RC
0 0 0 X 000 0 XXX X X X X X X X
000 1 XXX X X X X X X X
0 1 1 0 001 0 001 0 0 0 X X X 0
001 1 010 0 0 1 0 X 0 1
1 0 0 1 010 0 011 0
1 1 X 0
010 1 100
011 0 001
0
0 ..
011 1 100
100 0 101
100 1 100
0
0
1
.
101 0 001 0
101 1 100 1
CD
Q1 Q0 00 01 11 10
00 00 00 10 01
01 01 01 00 10
11 XX XX XX XX
10 10 10 01 00
Q1 (next) Q (next)
0
(a) Next−state table for encoding A
Q (present) Q (next) S R J K T D
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 1 0
1 1 X 0 X 0 0 1
(b) Flip−flop excitation table
CD
Q1 Q0 00 01 11 10
00 0 X 0 X 0 X 0 X 1 0 0 X 0 X 1 0
01 0 X X 0 0 X X 0 0 X 0 1 1 0 0 1
11 X X X X X X X X X X X X X X X X
10 X 0 0 X X 0 0 X 0 1 1 0 0 1 0 X
S 0 S1 R 0 R 1
S 1 = Q0 C D’+ Q’Q’C D
1 0
[cost = 18, delay = 3.6]
R1 = Q1 C = (Q’1 + C’)’ [cost = 9, delay = 1.4]
S 0 = Q1 C D + Q’Q’C D’ [cost = 18, delay = 3.6]
1 0
R0 = Q0 C = (Q’0 + C’)’ [cost = 9, delay = 1.4]
(c) Implementation with SR flip−flops
Figure 30: Mod-3 counter using SR FFs [Gajski].
CD
Q1 Q0 00 01 11 10
00 0 X 0 X 0 X 0 X 1 X 0 X 0 X 1 X
01 0 X X 0 0 X X 0 0 X X 1 1 X X 1
11 X X X X X X X X X X X X X X X X
10 X 0 0 X X 0 0 X X 1 1 X X 1 0 X
J0 K 1 J0 K1
J1 = Q0 C D’+ Q’C D = (C’+ Q0 D + Q0’D’ )’ [cost = 12, delay = 2.4]

0
K1= C [cost = 0, delay = 0]
J0 = Q1 C D + Q’Q’C D’ = (C’+ Q’1 D + Q1 D’ )’
1 0
[cost = 12, delay = 2.4]
K0= C [cost = 0, delay = 0]
(d) Implementation with JK flip−flops

CD CD
Q1 Q0 00 01 11 10 Q1 Q0 00 01 11 10
00 0 0 0 0 1 0 0 1 00 0 0 0 0 1 0 0 1
01 0 0 0 0 0 1 1 1 01 0 1 0 1 0 0 1 0
11 XX XX XX XX 11 XX XX XX XX
10 0 0 0 0 1 1 1 0 10 1 0 1 0 0 1 0 0
T0 T1 D0 D1
T1 = Q1 C + Q’0 C D + Q0 C D’ [cost = 22, delay = 3.6] D1 = Q C ’+ Q0 C D’+ Q’Q0’C D [cost = 24, delay = 4.0]
1 1
T0 = Q0 C + Q1 C D + Q1’C D’ [cost = 22, delay = 3.6] D1 = Q C’+ Q0 C D + Q’Q0’C D’ [cost = 24, delay = 4.0]
0 1
(e) Implementation with T flip−flops (f) Implementation with D flip−flops
Figure 31: Mod-3 counter using other types of FFs [Gajski].
Optimization and Timing Diagram

C D
1 1
1 1
2.4 J1 Q1
4.0
K1 Q’1
1.8
1.4 Y
2.2
Input−output delays
2.4 J0 Q0 C, D to Clk 5.4

4.0
Clk to Y 7.6
K0 Q’0
C, D to Y 5.6
Clk Clk to Clk 7.4
(a) Logic schematic (b) Delay table
Clk
4.0 4.0 4.0 4.0

Q1
Q0 4.0 4.0
7.6 7.6 5.6 7.6

Y
t0 t1 t2 t3 t4 t5 t6
Figure 32: Schematic and a timing diagram of mod-3 counter [Gajski].
Design Example: Counters
✯ A counter is a sequential circuit that goes through a prescribed sequence of

states upon the application of input/clock pulses (the count pulses).
✯ A banary counter is one that follows the binary sequence.
✏ An n-bit counter counts from 00 0 up to 11 1 (2n 1), and then reset

to 00 0.
✏ What is a self-correcting FSM? What has it to do with unused states?
We are going to design a divide-by-6 counter (modulo-6 counter) with the counting
sequence (0,1,2,3,4,5), which produces a ‘1’ if the state ‘5’ is encountered, and ‘0’
otherwise. We are going to use T FFs. The state diagram and table are shown
below.
PS NS O/P Excitation
ABC ABC y TA TB TC
0 -/0 1 000 001 0 0 0 1
-/1 -/0 001 010 0 0 1 1
010 011 0 0 0 1
5 2 011 100 0 1 1 1
100 101 0 0 0 1
-/0 -/0 101 000 1 1 0 1
4 -/0 3 110 XXX X X X X
111 XXX X X X X
From the table, the simplified output function and the excitation functions can be
derived using the K-maps:
BC BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
0 0 1 0 1 1 0 1 1 1 1
1 1 X X 1 1 X X 1 X X 1 1 1 X X
y = AC TA = AC + BC TB = A C 0
TC = 1
TA = A B
And the schematic of the counter is shown below.
T Q T Q 1 T Q y
Q0
Q0
Q 0
A B C
✍ What if we use JK FFs? Work the details out.

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6.

Synchronous Sequential Logic 6-1

Chapter 6. Synchronous Sequential Logic

Mealy’s Model Moore’s Model

Figure 1: Synchronous sequential circuit models.

✯ A sequential circuit is a logic circuit that employ memory elements in addi-

✯ A synchronous sequential circuit changes their states and output values at

Clock Rising edge

Figure 2: Clock signal [Gajski].

☞ In the NOR-type SR latch, if S ,

(a) Logic schematic (c) Truth table

Q’ 1.4 1.4 1.4

(b) Timing diagram

(a) Logic schematic (c) Truth table

1.4 1.4 1.4 Undefined

(b) Timing diagram

Figure 3: NOR-type and NAND-type SR latches [Gajski].

Gated SR Latch (Clocked SR Latch)

t12 t11  tsetup

t13 t12  thold

(a) Logic diagram (b) Function table

Fig. 4-7 SR Latch with Control Input

Figure 4: Gated SR latch (NAND-type) [Mano & Kime].

(a) Graphic symbol (b) Logic schematic (c) Truth table

reset state set state reset state

(d) Timing diagram

Figure 5: Gated SR latch (NOR-type) [Gajski].

✩ Avoiding S = R = 1 (for NOR-type latch).

(a) Graphic symbol (b) Logic schematic (c) Truth table

reset state set state reset state

(d) Timing diagram

Figure 6: Gated D latch [Gajski].

☞ A latch which is enabled whenever C = 1 is called a level-sensitive latch (or

(a) Logic schematic

(b) Timing diagram

Figure 7: Erroneous shifting with D latches [Gajski].

✯ A master-slave flop-flop is implemented with two latches—a master latch and

✩ The input to the master latch is the input to the FF.

(a) Logic schematic

Qm 4.0 3.0 5.0 3.0

Qs 4.0 3.0 4.0

(b) Timing diagram

Figure 8: Master-slave flip-flop [Gajski].

Master−slave flip−flop Master−slave flip−flop Master−slave flip−flop

(a) Logic schematic

Q1m 4.0 3.0

Q1s 4.0 3.0

Q2m 5.0 3.0

Q2s 4.0 3.0

Q3m 5.0 3.0

(b) Timing diagram

Figure 9: Shifting with master-slave flip-flops [Gajski].

✯ An edge-triggered FF is implemented with three interconnected SR latches:

A 2.8 2.8 4.2 2.8

S 1.4 1.4 1.4 1.4

B 1.4 1.4 2.8 1.4

(b) Timing diagram

Figure 10: Edge-triggered flip-flop [Gajski].

Table 1: Flip-flop types [Gajski].

☞ We assume only positive (rising) edge-triggered FFs.

Table 2: State diagrams for various flip-flops [Gajski].

J,K = 1,0 or 1,1

✯ A flip-flop can have asynchronous inputs: P RS (preset) and C LR (clear or

t12 t11 tsetup

t13 t12 thold