Free Scale

Nov.
6, 2008
Quality/Zero Defect: Freescale Strategies,
Measures and Tools
PA101
Peter Kang
China Automotive FAE Manager
TM
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective
owners. © Freescale Semiconductor, Inc. 2008.
Freescale Quality Vision
Vision Zero = Zero
• Zero Defects for the Automotive Market

Mission • Safe Launch on New Product Introductions
Defects
• Containment
• Analysis
• Improvement
Strategy Spill Elimination

Safe Launch
• New Technology Introduction
• New Product Development
• Technology and Product Transfers
TM
owners. © Freescale Semiconductor, Inc. 2008. 2
Looking Back on the Journey
TM
TSPG ZD: Management Frame Work
NPI ZERO DEFECT
► In 2004/ 2005 we started the NPI
Sea of Full
ATPG
Full Mixed
Design
Rules vs Prevention
journey for Zero defects
Gates Design BIST SOC Scan Mode Simul
Fab Process
► We set a management framework :

DETECTION/PREVENTION
TSPG Fab Assy/Test Test S/W Current

Web Prevention
• Classical: i.e, Containment and MGMT
Review DSS
Device A
Device B
Device A
Device B
Device A
Device B
screens Device C Device C Device C
• Detection and Prevention Current Production Classical

Maverick Product Test Hole Flash Reliab. Approach
Containment Elimination Screens
• Focus on Zero Defect techniques Device A Device A Device A
Device B Device B Device B
for New Products Device C Device C Device C
ZD Elements
► We defined a set of ZD elements

NPI ELEMENTS
JVT DFM(accuracy of device models for process)
Design for Test
Design
VCT/HVST
in the Manufacturing, Product and Product Zero Defect

Iddq
Test Coverage (AEC Spec)
Design for FA
Full Chip STA vs Module
Test and Design

Program Lessons learned Look Across Flash & SRAM ECC
Standardized NVM test methods Independent Verification Team
Verification
Burn-In Verification at module , platform , system level
WebDSS CQI Entry Random Pattern generation at Module level
► These were constantly upgraded Manufacturing Zero

PAT (Unit Probe)
BMY
100% RTL block & expression coverage
Spec Tagging
and carried forward as ‘ZD base’

Defect Program SBL Phase1 SRAM & Flash BIST
SBL Phase 2 Trace Matrix
Test
PAT (Final Test) Full Chip AC & DC Scan >98% Stuck Fault coverage
for each new technology and Division Specific

Elements
Gate Stress
100% Cold Test
Code execution memory tests
Reliability Lookahead(ESD/ NVM/ HTOL/TV)
Product
100% Hot Test
product.
Burn-in Scan* & BIST
Inductive Load Matrix CZ prior to launch & or 2nd tape out
Continuos Improvement- Particle Failure Analysis Capability
Continuos Improvement- Defect Density
► In manufacturing we raised the bar

Smoke alarm / Volt storm
SPC- Process, Particles
Top level simulation - mixed signal
SPC- Class Probe
Peer reviews
SPC- Unit Probe
successively
Analog HVST (SOA, inductive load, gate stress, bvdss
ISTAB- Process, Particles
ISTAB- Class Probe
Factory Driven
Problem Solving- 8D/ 5 Why's
Problem Solving- FMEA
Problem Solving- CAB
Maverick Prevention- Lot
Maverick Prevention- Wafer BMY
Maverick Anamolous- Process, Particles
Maverick Anamolous- Class Probe
TM
Freescale TSPG ZD Approach
► Institutionalize ZD elements as the foundation and add new learnings’
Defect Detection • Design for Manufacturability

• Defect Detection • Enhanced design rules
• HVST, ULV •BIST, SCAN • Line Spreading
• Application specific test
• Design for Functionality
• “Look Across” • State of art verification /
• In-line and burn-in FA. validation
• Defect Reduction • Design for Test
• Fab In-Line Monitors • AC/DC SCAN, ATPG,
• KLA, AIT’s, lot reviews • Partnership “Launch”
ZD Foundation
• Outlier Controls
• SBL, PAT, Cockpit Charts
#1
• Design for
Manufacturability ZD Foundation
• Lone Via Fix #2
• Introduce ‘Safe launch’ process with the customer

• Continue to raise the ZD requirements every year for manufacturing
TM
What is the ZD Methodology in Freescale?
TM
Freescale Zero Defects Methodology
ZERO DEFECTS
Design for Mfg Containment

Mfg Discipline
Design for Test Safe Launch
Process
TM
Design
for Mfg
DFM in Freescale
TM
Design for Manufacturability Strategy
► Freescale has invested substantially to advance DFM

• A dedicated group is assigned to develop and aggressively deploy advanced
techniques to impact our products
► Target quality throughout the design lifecycle

• Standard cells are scored and corrected. Newer cells must ensure that area /
quality is maximized
• SoC: Physical design flow is continuously updated to incorporate latest
techniques nearly as transparently as possible
► Continuously improve DTMS process

• DRC, DFM compliance are checked prior to tape-out
• Due diligence checks are added to ensure corrective actions have been
successful
► Drive the “Designed for Reality’ initiative

• Close the gap between predicted and true product results Design
for Mfg
TM
DFM Techniques
• Random particle induced • Inability to print desired • Occurrence of devices that

opens & shorts shapes due to physical fail to meet power and timing
• Resistive vias & via opens limitations of the litho process requirements
due to copper cladding and • Chemical & mechanical
litho process impacts of the mfg process on
wafer/die planarity
• Model based parasitic

extraction
• Statistical static timing
analysis and optimization
• More intelligent margining
• Variation robust design
Chip Design
Surface
for Mfg
TM
SoC DFM Methodology by Technology
Defect DFM Technique 0.35um 0.18/0.25um 0.13um 90nm 65nm 45nm

Class SMOS8, 25SGF, HiP7, LP/GP, LP/GP LP/GP,
CDR3 LL18, SMOS10 NVM, RF, SOI
HiP6WRF SOI
Via Recommend Required Required Required Required Required

Random
Optimization Wire Required Required Required Required
Synthesis Recommend Recommend Recommend

for yield
Timing Aware Tiling
Systematic
Recommend Recommend Recommend

(Metal Fill)
Model Based Required Required
Lithography and CMP
SSTA Pilot
Parametric
Variation
Tolerant
Model
Design
based Pilot
extraction
TM
Design
for Test
Design-for-Test
TM
Test Methodologies
►Digital Logic
• Scan is dominant test method with SA fault
coverage goal of >99%
Scan test through I/O pads increases die area
covered and through RAM increases
coverage in RAM surrounding logic
Inter clock domain scan increases transition
fault coverage
On-chip decompression / compression logic
enables high parallel test and test pattern
increase required for advanced fault models.
• Functional test patterns on top of scan
MCU
Test basic functionality on module basis
Covers what scan missed 0
data,
• Defect based tests IDDq, HVST addr, SRAM
Pseudo stuck at fault coverage control
RAMBIST
1
►SRAM and ROMs BIST mode
• Memory BIST implemented for all SRAM and
SDPRAM hard macros. Design
for Test
• Test Algorithms cover applicable Fault Models in
SRAMs and SDPRAMs:
TM
Test Methodologies
► NVMBIST for Non-Volatile Memories
• Flexible, embedded test of NVM controlled via a
dedicated test interface
Next generation NVM BIST engine combines hard coded
algorithm elements on chip in combination with pattern
selectable features
BIST serial scan chain loaded / unloaded via the 4 pin
interface
• Benefits Example NVM BIST LL18
Highly parallel NVM test at Sort-1 (x16 already). BIST INTERFACE
Test all P-Flash and D-Flash blocks on a die in parallel. HOLD FAIL
Provides means for easy test standardization/control INVOKE DONE
NVM
► Analog
CONTROLLER
& BIST ENGINE
• Approach
• Test specification derived from electrical D-FLASH FLASH-1S FLASH-1N FLASH-0
specification, test guide, and module characterization 16K x 22 16K x 72 16K x 72 32K x 72
results
• Functional patterns/functional tests development
according to test development process
• Test Quality
• Fault coverage achieved through functional coverage
of tests Design
for Test
TM
DFT Maturity Matrix–Clear standard for Design-for-Test
Design
for
Test
DFT Maturity Level 0 Level 1 Level 2 Level 3 Level 4 Level 5

• Ext. generated • SAF > 90% • SAF > 95% • SAF > 98% • Transition > 90% • SAF > 99.5%
functional • Transition >85% • SAF > 99% • Transition > 95%
• Path Delay >= 200 out of 1000 • Bridge > 70%
Digital most critical • 70% SI CFs
• Massively parallel test
enabler (UTI like)
• Ext. generated • Partial Scan • Full Scan Wrapper (DC) • Additional signals to increase • Appropriate level of critical test • Quantifiable boundary
functional Wrapper • Ad-hoc analog test analog testability points and test modes with coverage > 99%
Analog
modes (based on • DC scan stuck-at > 95% Appropriate level of Analog • 100% SAF & 95%Transition
(ADC, DAC, PLL, designer intuition) BIST testing of logic
Oscillators) • AC Scan Wrapper • Structural test of analog
• Full Analog BIST
• Externally generated • Large Array • Data Retention support • All RAMs BIST tested with same • Sep BIST for DP RAMS • Programmable BIST capable
MBIST generated • Checkerboard & Inverse BIST type • BIST Intra-Word Coverage of running up to 40+ N
• March C- or tests • BIST March LR/LA better • BIST Any-bit-fast tests March tests
SRAM PMOVI algorithm • Different data • BIST X/Y fast addressing • Cell Stability Test • In the Field BISR
backgrounds run on the • BIST Bit Mapping • Cell Stress Test
March • SCAN write through • BIST paths >= Func paths.
• Externally generated • MBIST tested • 100% AF (inc and dec • BIST X/Y fast addressing • BIST Any-bit-fast tests
• 100% SAF addressing) • MBIST Bit Mapping Support • BIST paths >= Functional paths.
ROM • Scan read support • BIST MISR Aliasing probability
• BIST MISR Aliasing probability < < 0.1PPM (>=24-bit MISR)
1PPM (>= 20-bit MISR)
• Ext. generated • Array Test Modes • Basic BIST supported by • Configurable BIST • Code Execution BIST that • BIST include decode error
functional based State Machine • DC Scan logic > 98% detects Address Decode SOF detection
NVM, Flash • User modes only • Independent erasable • Massively parallel test enabler and Address Coupling Faults • 100% testpoints or BISTs of
test row (UTI or BDM based) • BIST paths >= Functional paths embedded analog
• MBIST Bit Mapping Support • DC Scan logic part > 99% • Scan read support
• Ad hoc, functionally • Most I/Os • Full control* of all pads • Full control* of all pad electricals • All pad electrical controls • I/O DFT/BIST
generated controllable via I/O state (jtag or • High speed IO 2^^7-1 random observable via ATPG scan
I/O register registers) sequence for BER (PRBS
loopback to PRSA):
• No DFT support for • Power down • Limited / Partial support • Scan based ATPG for IDDq • DFT techniques to enable HVT • Self monitoring Burn In
Parametric,
IDDQ, High Voltage mode for IDDQ • MBIST used for Burn IN • Burn In Mode covering Memories and voltage margin test for • Burn-in Self Test
IDDQ, HVST, Stress, Burn in, and partial scan designs including level shifters
Burn-in, Voltage Voltage Margin, Low • PLL Bypass for low frequency • Burn In Mode covering 100%
Margin, JVT Frequency and JVT memories and scan
Support
TM
Design For Test – Continuous Improvement
Oaks→S12→S12X → S12Xe Design
→ MPC5500 → next Gen @ 90nm for Test
Spanish Oak DFT Maturity
DFT Maturity Level 0 Level 1 Level 2 Level 3 Level 4 Level 5
• Ext. generated functional • DC Scan • DC scan (TC > 95%) • AC scan (TC > 70%) • AC scan (> 80%), • AC scan (> 85%),
Digital (TC > 90%) • DC ( > 98%) • DC ( > 99%)
enabler (UTI like)
Ext. generated functional • Partial Scan Wrapper Ad-hoc analog test • Additional signals to increase • Partial Analog BIST • Full Analog BIST
Analog analog testability complemented by test points or
modes.
(ADC, DAC, PLL, • Full Scan Wrapper (DC) • DC scan stuck-at > 95% exhaustive test points /
• AC Scan Wrapper testbench
Oscillators)
• Externally generated • Large Array MBIST • Data Retention support • All RAMs BIST tested with • Intra-Word March tests • Programmable BIST capable
SRAM generated • Checkerboard & Inverse tests same BIST type • Any-bit-fast tests of running up to 40+ N March
• March C- or PMOVI • Different data backgrounds run •March LR, LA, or better • SDD Support tests
algorithm on the March • X-fast option • LWSH support
• BIST Bit Mapping support • BIST paths >= Functional
• SCAN write through paths.
• Ext. generated functional •Array Test Modes • Basic BIST supported by State • Configurable BIST • Code Execution BIST that • BIST include decode error
NVM, Flash based Machine • DC Scan of logic part > 90% detects Address Decode SOF detection
• User modes only • Independent erasable test row • Massively parallel test
enabler (UTI or BDM based)
• MBIST Bit Mapping Support
and Address Coupling Faults
• BIST paths >= Functional paths
• DC Scan of logic part > 98%
• 100% testpoints or BISTs of
embedded analog Copperhead DFT Maturity
• Scan read support
DFT Maturity Level 0 Level 1 Level 2 (L1 +) Level 3 (L2 +) Level 4 (L3 +) Level 5 (L4 +)
• Ad hoc, functionally generated • Most I/Os controllable via • Full control* of all pads I/O state •Full control* of all pad • All pad electrical controls • I/O DFT/BIST
I/O register (jtag or registers) electricals observable via ATPG scan
Digital • Ext. generated functional • DC Scan • DC scan (TC > 95%) • AC scan (TC > 70%) • AC scan (> 80%), • AC scan (> 85%),
(TC > 90%) • DC ( > 98%) • DC ( > 99%)
Parametric, IDDQ, • No DFT support for IDDQ, • Power down mode for IDDQ • Limited / Partial support • Scan based ATPG for IDDq • DFT techniques to enable HVT • Self monitoring Burn In enabler (UTI like)
High Voltage Stress, Burn in, MBIST used for Burn IN • Burn In Mode covering and voltage margin test for • Burn-in Self Test
HVST, Burn-in, Voltage Margin, Low Frequency Memories and partial scan designs including level shifters
Voltage Margin, and JVT • PLL Bypass for low frequency • Burn In Mode covering 100% Ext. generated functional • Partial Scan Wrapper • Full Scan Wrapper (DC) • Additional signals to • Partial Analog BIST • Full Analog BIST
memories and scan
Analog
JVT Support • Ad-hoc analog test modes. increase analog testability complemented by test
(ADC, DAC, PLL, • DC scan stuck-at > 95% points or exhaustive test
Oscillators) • AC Scan Wrapper points / testbench
SRAM • Externally generated • Large Array MBIST • Data Retention support • All RAMs BIST tested • Intra-Word Coverage • Programmable BIST
generated • Checkerboard & Inverse with same BIST type • Any-bit-fast tests capable of running up to
• March C- or PMOVI tests •March LR, LA, or better • SDD Support ** 40+ N March tests
Slide 0 algorithm • Different data backgrounds • X and Y fast addressing • LWSH support ** • In the Field BISR
TM Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale run on the March • BIST Bit Mapping • BIST paths >= Functional
Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005. support paths.
• SCAN write through ** - only required if RAM
has test mode
NVM, Flash • Ext. generated functional •Array Test Modes • Basic BIST supported by • Configurable BIST • Code Execution BIST that • BIST include decode
based State Machine • DC Scan of logic part > detects Address Decode error detection
• User modes only • Independent erasable test 95% SOF and Address Coupling • 100% testpoints or
row • Massively parallel test Faults BISTs of embedded
enabler (UTI or BDM • BIST paths >= Functional analog
based) paths • Scan read support
• MBIST Bit Mapping • DC Scan of logic part >
Support 98%
I/O • Ad hoc, functionally • Most I/Os controllable • Full control* of all pads I/O •Full control* of all pad • All pad electrical controls • I/O DFT/BIST
generated via register state (jtag or registers) electricals observable via ATPG scan
Parametric, IDDQ, • No DFT support for IDDQ, • Power down mode for • Limited / Partial support • Scan based ATPG for • DFT techniques to enable • Self monitoring Burn In
High Voltage Stress, Burn IDDQ MBIST used for Burn IN IDDq HVT and voltage margin • Burn-in Self Test
HVST, Burn-in, in, Voltage Margin, Low • Burn In Mode covering test for designs including
Voltage Margin, Frequency and JVT Memories and partial scan level shifters
JVT Support • PLL Bypass for low • Burn In Mode covering
frequency 100% memories and scan
Slide 13
TM Freescale™
Freescale Semiconductor
and the Freescale
Confidential
logo areand
trademarks
Proprietary
of Freescale
Information.
Semiconductor,
Freescale™ and Inc.the
All Freescale
other product
logo are trademarks of Freescale
Semiconductor,
or service namesInc.
areAll
theother
property
product
of their
or service
respective
namesowners.
are the
© property
Freescaleof Semiconductor,
their respective owners.
Inc. 2005.
© Freescale Semiconductor, Inc. 2005.
TM
Planned DFT Maturity for New NPIs
DFT Maturity Level 0 Level 1 Level 2 Level 3 Level 4
• Ext. generated • SAF > 90% • SAF > 95% • Transition >85% • Transition > 90%
functional • Path Delay >= 200 out of • SAF > 99%
Digital 1000 most critical • Bridge > 80%
• Small-delay defect coverage
• Selective path-delay testing
• Ext. generated • Partial Scan • Full Scan Wrapper • Additional signals to • Partial Analog BIST and/or
Analog functional Wrapper (DC) increase analog testability critical test points (tool
(ADC, DAC,PLL, • Ad-hoc analog test • DC scan stuck-at > 95% determined test points)
modes (based on • AC Scan Wrapper if module
Oscillators) designer intuition) running near Fsys.
• Externally • Large Array MBIST • Data Retention • All RAMs BIST tested with • Programmable BIST based on
generated generated support same BIST type 14N coverage
• March C- or PMOVI • Checkerboard & • BIST March LR/LA better • Sep BIST for DP RAMS
algorithm Inverse tests • BIST X/Y fast addressing • BIST Intra-Word Coverage
• Different data • BIST Bit Mapping • BIST Any-bit-fast tests
SRAM backgrounds run on • SCAN write through • SDD BIST Support **
the March • LWSH BIST support **
• BIST paths >= Func paths.
• ** - Only required if RAM has
test mode
• Ext. generated • Array Test Modes • Basic BIST • Configurable BIST • Code Execution BIST that
functional based supported by State • DC Scan logic > 98% detects Address Decode SOF
• User modes Machine • Massively parallel test and Address Coupling Faults
NVM, Flash only • Independent enabler (UTI or BDM based) • BIST paths >= Functional paths
erasable test row • MBIST Bit Mapping Support • DC Scan logic part > 99%
• Transition delay on logic > 85%
• Ad hoc, • Most I/Os • Full control* of all • Full control* of all pad • All pad electrical controls
I/O functionally controllable via pads I/O state (jtag electricals observable via ATPG scan
generated register or registers)
Parametric, • No DFT support • Power down mode • Limited / Partial • Scan based ATPG for IDDq • DFT techniques to enable HVT
for IDDQ, High for IDDQ support • Burn In Mode covering and voltage margin test for
IDDQ, Voltage Stress, • MBIST used for Burn Memories and partial scan designs including level shifters
HVST,Burn- Burn in, Voltage IN • PLL Bypass for low • Burn In Mode covering 100%
Margin, Low frequency memories and scan
in, Voltage Frequency and
Margin, JVT JVT
Support
TM
Ongoing
► FSL uses best-in-class Design-for-Test technology, test engineering
processes to proactively enable Zero Defect Quality for NPIs.
► Statistical analysis through volume diagnosis ensures efficiency of
institutionalized methods and enables further improvements through
‘lessons learned’.
► FSL working with leading EDA vendors and universities and investing in
research for new DFT technology:
• New Fault Models to better model silicon defects:
Bridging Fault Model (statistical and layout based)
Timing Aware ATPG - Small Delay Defects
Opens Defects
• New DFT architectures:
Field Programmable BIST for SRAMs
Core Self Test for Safety Critical applications
► New technology is integrated into DFT Maturity Matrix

as standard best practice and rolled out world wide. Design
for Test
TM
Containment
Mfg Discipline
Safe Launch
Process
Manufacturing & Continuous Improvement
TM
Zero Defects Methods in Manufacturing
► Manufacturing uses a structured ZD Elements
approach to institutionalize zero JVT
VCT/HVST
defect elements Product Iddq
Test Coverage (AEC Spec)
Zero Defect
Lessons learned Look Across Containment
► Die and Final Manufacturing SPC Program
Standardized NVM test methods
programs and specification limits Burn-In

WebDSS CQI Entry
Safe Launch
Process
identify rogue product & processes Manufacturing Zero
PAT (Unit Probe)
BMY
Defect Program SBL Phase1
► Specification limits are used as the SBL Phase 2
PAT (Final Test)
gauge to determine if product is fit for Division Specific
Gate Stress
use. Elements
100% Cold Test
100% Hot Test
Inductive Load
► Capability (CpK) studies are Continuos Improvement- Particle

Continuos Improvement- Defect Density
performed monthly on various inline SPC- Process, Particles
SPC- Class Probe
process and class probe parameters SPC- Unit Probe
ISTAB- Process, Particles
Mfg
► Advanced Intelligent Manufacturing ISTAB- Class Probe
Factory Driven Problem Solving- 8D/ 5 Why's Discipline
techniques such ‘input controls’ and Problem Solving- FMEA
Problem Solving- CAB
Fault Detection Control are being Maverick Prevention- Lot
deployed Maverick Prevention- Wafer BMY

Maverick Anamolous- Process, Particles
Maverick Anamolous- Class Probe
TM
Zero Defects: Continuous Improvement
"WAFER FAB PROGRAMS"
Continuous Excursion Prevention Prevention
WAFER FABS
Location
Improvement
SPC
Statistical Tools
ISTAB Data Analysis
Problem Solving &
BMY
"Maverick"
"Anomalous" Mfg
Achieved 1st Discipline
Unit Probe (SBA)
PAT (Unit Probe)

SODA / Others
Defect Density
Dashboard /
Class Probe
Class Probe
Class Probe
Unit Probe
Particles
baseline ZD Criteria
Particles
Particles
Process
Process
Process
ANOVA
Particle
FMEA
Wafer
CAB
CQI
Lot
8D
MOS9 EKB, Scotland YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES
MOS11 Austin, TX YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES Q2 '04 Q2 '04
MOS12 Chandler, AZ YES YES YES YES YES Q4 '03 Q4 '03 YES YES YES YES Q1 '04 Q4 '03 Q4 '03 YES YES YES YES YES YES Q4 '03 Q4 '03
MOS13 Austin, TX YES YES YES YES YES Q1 '04 Q4 '03 YES YES Q1 '04 YES YES YES YES YES YES YES YES YES YES Q4 '03 Q1 '04
MOS20 Tolouse, France YES YES YES YES YES YES YES YES YES Q4 '03 YES YES YES YES YES YES YES YES YES YES Q4 '03 YES
TSC6 Sendai, Japan YES YES YES Q2 '04 Q2 '04 Q2 '04 Q2 '04 Q2 '04 Q2 '04 Q2 '04 YES YES"WAFER
YESFAB PROGRAMS"
YES YES YES YES YES YES YES
Q4 '03 Q2 '04 Last Update
TSMC Hsinchu, Taiwan YES YES Continuous
YES YES YES YES YES Q4 '03 Q4 '03 Q4 '03 YES Excursion Prevention
YES YES YES YES YES YES YES Prevention
YES YES
Q4 '03 YES Collaboration
WAFER FABS Improvement Statistical Tools Problem Solving & prev "Maverick"
Location SPC ISTAB Data Analysis BMY "Anomalous" FMO PFO
Institutionalized
DRA/PRA /detection matrix

Actions Identified for missing elements required to meet ZD challenge
Raised the bar –
Advance Outlier Techniques

Actions identified for all elements required to meet ZD challenge
Test Program Release

Dashboard / ANOVA
added
Sharing of BKMs'
Unit Probe (SBA)
PAT (Unit Probe)
Test Coverage
SODA / Others
Defect Density
Class Probe
Class Probe
requirements
Particles
Particles
Particles
Process
Process
Process
Burn-In
Particle
FMEA
Wafer
DFM
CAB
CQI
Lot
8D
5S
MOS9 EKB, Scotland YES YES YES YES YES YES YES YES YES YES YES WW04 2004
MOS11 Austin, TX YES YES YES YES YES YES YES YES YES YES YES Q2 '04 Q2 '04 WW04 2004
MOS12 Chandler, AZ YES YES YES YES YES Q1 '04 YES Q4 '03 YES
YES YES Q4 '03 WW04 2004
MOS13 Austin, TX YES YES YES
Q1 '04 YES YES YES YES YES YES YES Q1 '04 WW04 2004
MOS20 Tolouse, France YES YES YES
YES YES YES YES YES YES YES YES Q2 '04 WW04 2004
TSC6 Sendai, Japan YES Q2 '04 Q2 '04 Q2 '04 Q2 '04 Q2 '04 YES YES YES YES YES YES YES Q2 '04 WW04 2004
CS1 ** Tempe Az "WAFER FAB PROGRAMS" Collaboration
TSMC Hsinchu, Taiwan YES YES YES YES YES YES YES YES YES YES YES Q2Continuous
'04 WW04 2004
Excursion Prevention Prevention
WAFER FABS Improvement Statistical Tools Problem Solving & prev "Maverick"
Institutionalized Location SPC ISTAB Data Analysis BMY "Anomalous" FMO PFO
DRA/PRA /detection matrix
Advance Outlier Techniques

Test Program Release

=
Dashboard / ANOVA
Maintenance Items from Phase 2 activity
Sharing of BKMs'
Unit Probe (SBA)
PAT (Unit Probe)
Test Coverage
SODA / Others
Defect Density
Class Probe
Class Probe
Particles
Particles
Particles
Burn-In
Process
Process
Process
Particle
FMEA
Wafer
DFM
CAB
CQI
Lot
8D
5S
MOS9 EKB, Scotland Jun YES YES YES Jun Jun Jun YES YES YES YES YES YES YES YES YES YES YES YES Dec Dec YES Q4'05
MOS11 Austin, TX YES Jun Jan Jun Jun Jun Jun Jun Jun Jun YES YES YES
MOS12 Chandler, AZ YES YES YES YES Jun Jun TBD Mar Mar YES YES YES Jul YES YES YES YES Jun Jun Dec Dec Dec YES YES
MOS13 Austin, TX Jun YES Dec YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES Jun YES YES Dec
MOS20 Tolouse, France YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES Dec YES Sep
TSC6 Sendai, Japan Jun YES YES YES Jun Jun Jun Jun Jun Jun YES YES YES YES YES YES YES YES YES YES YES Dec
TSMC Hsinchu, Taiwan YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES Jun Jun
Institutionalized
= Maintenance Items from Phase 2 activity
TM
Safe Launch Plan Template
► The Safe Launch Template defines elements to be reviewed
1. Information Overview
• Goal, Team, Module info, Part info
2. Shipment Plan Review
3. IC Manufacturing Review
4. Module Design Review
5. Module Manufacturing Review
6. Failure Analysis Plan Review
7. Returns History Review
8. Risk Assessment
► Actions items are captured and tracked Containment

within each section
Safe Launch
Process
TM
Freescale Zero Defects Methodology
ZERO DEFECTS
Containment
Design for Mfg
Safe Launch
Design for Test Process
Mfg Discipline
TM
Results
TM
New Product Launch PPM
NPI PPM
►Launch PPM 40
• First unit shipped through 100K 35

30
units shipped, plus six months 25
ppm
20
15
10
5
0
2005 2006 2007 2008 YTD
►Improving Launch PPM through: NPI's AT ZERO PPM
• Design for Zero 100%
% of NPI's at Zero Defects

Defect Methodology 80%
• Improved Test Maturity Prior 60%
to Launch 40%
20%
• Manufacturing
0%
• Safe Launch Partnerships 2005 2006 2007 2008 YTD
TM
Microcontroller History
2um 1um 0.35um 0.25um 0.13um 90nm

1982: 20,000
Transistors 1990:
8-bit CPU 200,000
Transistors 1998:
32-bit CPU 7,000,000
Transistors 2000:
32 Bit RISC 14,000,000
Launch ppm
CPU Transistors 2003:

32 Bit RISC 34,000,000
CPU 1.0MB Transistors
Flash Memory MCU/DSP/IO 2008:
2.0MByte 65,000,000
Flash Memory Transistors
Z7 Core >250MHz
4.0MByte
Flash Memory
2MB
Embedded
32bit µC Flash
with
peripherals
Zero Defects Focus
TM
Microcontroller Zero-Defect Strategy
eSYS C90
2003 design 2008 design
S12 <1 ppm capability
2000 design <1 ppm capability
<10 ppm capability
Oaks Q4’07 ~ 5.0 ppm
1996 design
50 ppm capability
4Q07 ~10 ppm • Design for Manufacturability • 4th Cycle of Zero
• Defect Detection • Enhanced design rules Defect Learning
• BIST, SCAN • Line spreading • Enhanced tools
• Design for and processes improve
• Design for Functionality maturity of our DFx
Manufacturability
• State of art capabilities.
• Lone Via Fix
verification/validation • Design for Test
• Design for
• Design for Test Manufacturability
• Defect Detection • AC/DC SCAN, • Design for
•HVST, ULV ATPG, IDDQ Functionality
•Application specific test • Design for
•“Look across” • Partnership “Launch” Failure analysis
•In-line and burn-in FA • Zero Defects Foundation
• Outlier Controls
•SBL, PAT, cockpit charts
• Zero Defects Foundation

• Defect Reduction Zero Defect Foundation
• Fab in-line monitors
• KLA, AIT’s, lot reviews
TM
Copperhead PPM Trend
10.00 4.50
9.00 4.00
8.00 3.50
Overall PPM: 3.1
Cum ship volume (M)

7.00 Confirmed FSL Defect
3.00
Cum Ship Volume
Qty Returned
6.00
2.50
5.00
2.00
4.00
1.50
3.00
2.00 1.00
1.00 0.50
0.00 0.00
ec 6
ec 7
6
ar 8
a 6
Ap r-06
a 7
Ap r-07
8
6
Ju -06
Ju -07
8
Ju -06
Ju -07
6
c 6
p 7
O -07
Ja -06
Ja -07
ay 6
ay 7
N t-06
N t-07
D v-0
D v-0
Au l-0
Au l-0
M b-0
M b-0
M b-0
-0
Fen-0
Fen-0
Fen-0
Seg-0
O p-0
Seg-0
M r-0
M r-0
n
n
o
c
o
Ja
Dates are “As Manufactured” by Freescale
TM
IMX31 Auto 27x27mm PPM Trend
10 600
Thousands
Overall PPM = 2.0 500
8
Confirmed FSL Defect
400
Cum Ship Volume
Qty Returned
Cum Ship Qty

300
4
200
2
100
0 0
7
7
8
7
07
08
8
08
8
07
7
-0
-0
-0
l-0
-0
-0
r-0
-0
n-
b-
g-
p-
n
ov
ar
ct
ay
ec
Ju
Ap
Ju
Au
Ja
Fe
Se
M
N
M
D
Dates are “As Manufactured” by Freescale
TM
Freescale Zero Defects Summary
Sort, Set, Shine, Standardize and Sustain (5S)

Product Quality/ Risk Assessment
Part Average Testing and Statistical Bin Limits
Outlier Detection
Fab Defect Reduction
Design for Manufacturing
Design for Test
Enhanced Reliability Methodology
Safe Launch
Application/Test Correlation
(Trouble not indicated reduction)
TM
Moving Forward on this Journey
TM
Challenges for Semiconductor Reliability in the
Automotive Industry
As technology advances, gate oxides and transistor channel lengths are
shrunk at a faster rate than voltage is decreased, and material compositions
are changing (nitrogen content in oxides, etc.); thus, the wear out portion of
the curve generally shifts to the left.
Reliability Bath Tub Curve
Screen (if necessary)
Early Life Failure Rate

Failure
Rate Wearout Failure Rate
(Intrinsic Failures, currently
Long Term Failure Rate dominated by NBTI and HCI)
(Extrinsic Failures)
Product Useful Life Time

0 Time
Intrinsic reliability lifetimes of new technologies are now on the order of

expected product use times in the field.
TM
Advanced CMOS Intrinsic Wearout Mechanisms
Dominant intrinsic reliability failure mechanisms in advanced CMOS technologies are
Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) which
cause parametric shifts with some distribution, instead of hard failures.
Vdd Vdd
h+ e- Gate e- h+ Gate
Gate Oxide Gate Oxide
Source h+e- e- h+ Drain Source e- Drain

e- e-
GND GND GND Vdd
Negative Bias Temperature Instability (NBTI): Hot Carrier Injection (HCI):

Physical Mechanism: Physical Mechanism:
• Electrons/holes that tunnel across the gate oxide create • Electrons/Holes scatter as they go from source to drain.
energetic positive charges that damage or get trapped in the • Damaging the interface and oxide.
gate oxide.
Effect:
Effect: • Reduction of mobility (conductance) of the transistor.
• Primarily an increase in Vt due to trapped charges. • Change in Vt due to charge build-up in oxide.
• Occurs in PMOS only. • Occurs in both NMOS and PMOS
TM
Performance Shift Mitigation
Activities at Freescale
1) Life Test Simulation Optimization
Life Test stress conditions (voltage, temperature) are optimized to ensure AEC required stress time
simulates expected field-use time.
2) Life Test Shift Analysis

Critical AC/DC parameters are measured before and after required life test to check for general shifts
due to extrinsic or intrinsic failure mechanisms.
3) Intrinsic Reliability Shift Analysis

Required for products in CMOS090 and newer technologies. The general procedure is as follows:
a) Measure performance before and after life test, preferably at a readpoint that simulates expected
field-use time assuming the NBTI failure mechanism (may be different readpoint than (1) )
b) Extrapolate life test performance shifts to expected field shifts, based on NBTI models developed
during intrinsic reliability testing. Control sample data is taken into account at this step.
c) Add HCI effects based on NBTI versus HCI shifts observed during intrinsic reliability testing,
since HCI effects are not generally observed during low frequency life testing.
d) Create product test guardbands based on statistical distribution of normalized shifts.
TM
Performance Robustness Validation
Activities Moving Forward
1) Split Lot Analysis
Performance data is being taken on nominal versus slow PMOS transistor lots to check which patterns
may be affected by NBTI. Split lot results will be checked against life test results to determine correlation.
2) Aging Simulation in Design

Aged transistor models are being input to design simulation tools and performance estimates checked
against split lot and life test results.
3) Test Vehicle Evaluations

Stress ring oscillators and other test circuits are being stressed in parallel to device stresses to check for
shift correlation.
Performance Shifts for Automotive Products

• At this time, performance shift concerns are minimal for Automotive devices, since they generally
lag in technology and do not push performance limits.
• To minimize future risks and to assure Zero Defects for Automotive devices in advanced
technologies, proactive steps are being taken to understand, minimize, and mitigate risks of
performance shifts. Advanced reliability robustness validation techniques will be applied.
TM
Robustness Validation
ZVEI Robustness
There are several techniques under Validation Diagram
evaluation in Freescale to understand
Die, Die / Package, and Package VERY
ROBUST
wear out mechanisms
Fail A
M od
ure
ROBUST
e
• ESD testing at multiple voltages LEAST
followed by Operation Life studied to ROBUST
determine failure curves
(ex: voltage)
Parameter B
Margin
Application
Application
• Test intrinsic silicon mechanisms to 1
2
failure Specification
• Extend traditional package level
Fa de
od re
Mo
ilu C
B
stresses to failure M ailu
e
re
F
Parameter A
(ex: temperature)
TM
It’s Impossible.
Zero=Zero.
► Freescale is committed to Zero Defects for Automotive
► Proven commitment to Drive Quality Improvement
► Demonstrated the Ability to Launch Products at Zero Defect Levels
► Continue to Develop and Implement New Zero Defect Strategies on
Next Generation Products
TM
Related Session Resources
Session Location – Online Literature Library

http://www.freescale.com/webapp/sps/site/homepage.jsp?nodeId=052577903644CB
Sessions
Session ID Title
Demos
Pedestal ID Demo Title
TM
TM

Free Scale

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Nov.

Vision Zero = Zero

• Zero Defects for the Automotive Market

Strategy Spill Elimination

► We set a management framework :

TSPG Fab Assy/Test Test S/W Current

screens Device C Device C Device C

• Detection and Prevention Current Production Classical

► We defined a set of ZD elements

in the Manufacturing, Product and Product Zero Defect

Test and Design

► These were constantly upgraded Manufacturing Zero

and carried forward as ‘ZD base’

for each new technology and Division Specific

► In manufacturing we raised the bar

► Institutionalize ZD elements as the foundation and add new learnings’

Defect Detection • Design for Manufacturability

• Introduce ‘Safe launch’ process with the customer

Design for Mfg Containment

► Freescale has invested substantially to advance DFM

► Target quality throughout the design lifecycle

► Continuously improve DTMS process

► Drive the “Designed for Reality’ initiative

• Random particle induced • Inability to print desired • Occurrence of devices that

• Model based parasitic

Defect DFM Technique 0.35um 0.18/0.25um 0.13um 90nm 65nm 45nm

Via Recommend Required Required Required Required Required

Optimization Wire Required Required Required Required

Synthesis Recommend Recommend Recommend

Recommend Recommend Recommend

DFT Maturity Level 0 Level 1 Level 2 Level 3 Level 4 Level 5

► New technology is integrated into DFT Maturity Matrix

Manufacturing & Continuous Improvement

programs and specification limits Burn-In

► Capability (CpK) studies are Continuos Improvement- Particle

deployed Maverick Prevention- Wafer BMY

Unit Probe (SBA)

PAT (Unit Probe)

DRA/PRA /detection matrix

Advance Outlier Techniques

Test Program Release

PAT (Unit Probe)

DRA/PRA /detection matrix

Advance Outlier Techniques

Test Program Release

PAT (Unit Probe)

= Maintenance Items from Phase 2 activity

► The Safe Launch Template defines elements to be reviewed

► Actions items are captured and tracked Containment

• First unit shipped through 100K 35

►Improving Launch PPM through: NPI's AT ZERO PPM

• Design for Zero 100%

% of NPI's at Zero Defects

• Improved Test Maturity Prior 60%

2um 1um 0.35um 0.25um 0.13um 90nm

CPU Transistors 2003:

Zero Defects Focus

• Zero Defects Foundation

Cum ship volume (M)

Dates are “As Manufactured” by Freescale

Cum Ship Qty

Dates are “As Manufactured” by Freescale

Sort, Set, Shine, Standardize and Sustain (5S)