TECHNICAL FEATURE

AVE JOU
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MIC

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REVIEWED

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R
OR A
IAL B O

UNDERSTANDING
PHASE-LOCKED DRO
DESIGN ASPECTS

P
hase-locked dielectric resonator oscilla- in an ordinary synthesized frequency genera-
tors (DRO) are essential components in tor is avoided within the loop band. In addi-
high frequency microwave links where tion, the free-running phase noise characteris-
phase noise is a crucial parameter. The main tic of the Vt-DRO gives the advantage of low
advantage of a phase-locked DRO (PLDRO) phase noise performance outside the loop
source over an ordinary synthesizer is its bandwidth at high offset frequencies. This
phase noise characteristic. This is due to the characteristic is most evident with GaAsFET
voltage-tuned DRO’s (Vt-DRO) high quality DROs, where the free-running phase noise
factor tank circuit (a dielectric resonator) on spectrum rolls off at a –30 dB per decade rate.
one hand, and direct locking to a high fre- Furthermore, the possibility of wideband
quency reference harmonic by means of a mi- phase locking of the Vt-DRO provides good
crowave sampling phase detector (SPD) on short-term stability (for instance, low micro-
the other. In this way, the noise floor contribu- phonicity) for this frequency source. However,
Fig. 1 The PLDRO block tion of prescalers and frequency dividers used unlike a standard synthesizer, a PLDRO re-
diagram concept. ▼
quires a special frequency acquisition and
TUNING SCREW locking technique for correct and reliable op-
eration. In this article, phase noise considera-
tions, a loop optimization procedure and a
fPLO = NxfREF PLDRO specific acquisition technique for PLDROs
Vt-DRO OUTPUT
are explained.
Vtune HIGH STABILITY AND ACQUISITION CIRCUIT REQUIREMENTS
LOW PHASE NOISE Sweeping Range Considerations
REFERENCE SOURCE
(TCXO) Frequency acquisition can be accom-
R1
plished by sweeping the Vt-DRO, as shown in
fREF the block diagram in Figure 1. The SPD dri-
C R2 LOOP FILTER MICROWAVE ven by the reference signal generates a comb-
AND AIDED SAMPLING like spectrum. At the instant the Vt-DRO fre-
SEARCH/ PHASE
ACQUISITION DETECTOR quency coincides with the reference signal’s
LOCK
ISW CIRCUIT desired harmonic, the loop will acquire a sta-
DETECT ble lock and will remained locked as long as
CIRCUIT the search signal is not too fast or large. The
CURRENT INJECTION
FOR SWEEP/SEARCH
SIGNAL

LOCK AVI BRILLANT

DETECT
ALARM
Optomic Microwaves Ltd.
Migdal Ha’Emek, Israel
 TECHNICAL FEATURE
frequency spacing between each In the case of a second-order PLL
EQUATION 17 EQUATION 18
comb harmonic is equal to the tem- with an active loop filter, H(s) is given

NORMALIZED SWEEP
perature-compensated crystal oscilla- by 0.59
tor’s (TCXO) frequency as defined in 0.49

()

RATE SRi, SRj

Vo s
H(s ) =
0.39
f(n) = f(TCXO)• n • δ(n – N) (1)
Vi (s )
0.30

f(TCXO) = f(TCXO) 0.20

• {n • δ(n – N) – [(n – 1) 1 + sτ1 0.10

• δ([n – 1] – [N – 1])} (2) = – (5) 0

sτ 2
Hence, to prevent false lock on an where
undesired comb harmonic, the tuning
τ1 = R1C
range ∆f of the Vt-DRO should satis-
τ2 = R2C
fy the condition
Substituting these expressions into
∆f < 2 • f(TCXO) (3)
Equation 4 and using the LaPlace fi-
For a symmetrical search, the opti- nal value theorem produces
mum Vtune value of the Vt-DRO (that
()
s 2θi s
()
is, the value at which the desired
θe s =
phase-locked oscillator frequency is
s + 2ξω ns + ω 2n
2 ∆˙ω
reached) should be half of the control
voltage swing range (for instance, 1/2 where the natural loop frequency ωn
Vcc, where Vcc is the supply voltage to and the loop damping factor ξ are
the active loop filter). This value can given by
be easily obtained by mechanically
tuning the Vt-DRO tuning screw. In K VKd
the same way, the search signal volt- ωn =
τ1
age should be properly offset
(through a suitable bias voltage at the ω nτ2
ξ= (10)
acquisition and lock circuitry) by a 2 factory; Viterbi discovered that acqui-
value equal to the same optimum Now suppose that the input frequen-
Vtune. It is also important to use a suf- cy is linearly changing with time at
the rate of ∆ω⋅ rad/sec2 such that
ficiently high frequency reference
signal so that the sweep can be made
wide enough to cover the tempera- θ i = ∫ ∫ ωdt
ture drifts of the Vt-DRO. ⇒ θi t ()
Frequency Acquisition
1 ˙ 2
The sweep can be applied as an ∆ωt
= (11)
2 cal data that indicate the sweep rate
up-down ramp voltage directly to the Hence, θ(s) is given by the relevant
Vt-DRO tuning input. For a perfect
LaPlace transform
second-order loop with active inte-
∆˙ω
()
grator, a constant current Isw is insert-
ed to create a triangle sweep voltage θi s = (12)
with switching polarities. Such a tri- s3
Substituting Equation 12 into Equa-
angle sweep signal is due to tracking
tion 8 using the final value theorem
considerations.
The steady-state phase error θe = θi – yields the steady-state phase error ac-
θo after all transient effects have ter- cumulated during a linear frequency
minated (t→∞) is given by sweep
()
sθ i s
()
θe s = (4) s2
() () s3
s + K V K dH s lim θe t = lim s
t →∞ s →0 s 2 + 2ξω ns + ω n2
where
⇒ θe t ()
KV = Vt-DRO modulation
sensitivity (in radians/second ∆˙ω
= rad
per volt) ω n2
Kd = sampling phase detector
output sensitivity (in volts per (also called dynamic tracking error).
radian) Such input behavior might arise from
H(s) = loop filter transfer function accelerated motion between a trans-
2 3 4 5 6 7 8 9 10 11 12
SIGNAL-TO-NOISE RATIO ρi, ρj
▲ Fig. 2 Normalized sweep rate
(6)
as a function of SNRL.
(7)
mitter and receiver, Doppler fre-
quency shift or frequency sweep
modulation, which is the case here.
For a sinusoidal characteristic
phase detector, this expression is
(8)
sin θe = (14)
ω 2n
Note that the sinus function cannot
exceed ±1. Thus, the maximum per-
mitted sweep rate limit is given by
(9)
∆˙ω = ω 2n ⇒ ∆˙ω < ω 2n (15)
However, this condition is not satis-
sition is not certain even if the loop is
noise free, and there is a possibility
for acquisition only if
ω2
∆˙ω < n
2
Otherwise, it will not be locked.
Frazier and Page provided empiri-
should satisfy a particular condition
for acquisition in the presence of
noise. Gardner’s experience added
some changes, resulting in
1  1–2 
∆˙ω < ω 2n   (16)
2  SNRL 
 
In this case, 0.707 ≤ ξ ≤ 1 and the
loop signal-to-noise ratio (SNR L) is
less than 6 dB.
∆˙ω Two other experimental formulas
were suggested by Frazier and Page.
∆˙ω 2
ω N2 90%
≈1–
ρ
∀ ξ > 0.707 (17)
for 90 percent acquisition probability,
(13)
while ρ represents SNR L. In most
cases, a probability of 0.9 is too low.
For a better design where E(BLTS) =
104 cycle slips, the normalized sweep
rate is given by
 TECHNICAL FEATURE
VCC R4 • f − FVt-DROmin
∆ω = 4π Vt-DROmax

Vt-DRO FREQUENCY
R6 T
0V fVt-DRO max VCC
+ R5
fVt-DRO locked
−
OPA1 R2 C1 VCC/2
ISW
•
∆ω
− R1 VCC fVt-DRO min
−
NULL + T/2 T
OPA3 0V
ADJUST + OPA2 TIME (t)
SAMPLER
BEAT
NOTE ▲ Fig. 4 The triangle sweep signal.
R9
where
OFFSET FOR
Vt OPTIMUM VCC Vo(t)OPA2 = the output voltage from OPA2
R3 at a given time t
When, during the negative-going ramp of OPA2, the volt-
Vtune age V(t)OPA1+ at the comparator noninverting input be-
comes smaller than Vref at the comparator OPA1 inverting
Vt-DRO
input, its output switches to 0 V. At that moment the cur-
rent to the inverting input of the integrator OPA2 be-
comes
▲ Fig. 3 The aided search/acquisition circuit.
– Voffset
ISW = (21)
  1/2 
∆˙ω  2   R5
= 1 –   6 < ρ < 9.5 0.4 ρ > 9.5 (18)
ω 2n   ρ – 4   Since Voffset was chosen to be 1/2 Vcc, the current changes

its sign and the capacitor C is discharged. When the volt-
Figure 2 shows the normalized sweeping rate as a func- age V(t)OPA1+ reaches a higher value than Vref, the charge
tion of loop SNRL. of C1 will begin and vice versa. Figure 4 shows the trian-
gle sweep signal generated by this circuit. The sweep rate
Sweeping and Locking ∆⋅ω is defined by the triangle signal slope. Thus, the trian-
The PLDRO search and locking circuit, shown in Fig- gle frequency is one-half the sweep rate.
ure 3, consists of two feedback paths: a negative feedback The next objective is to calculate the sweep frequency
path, which is the locking circuit (OPA2-loop filter OPA3 from the circuit parameters. The current ISW through R5
high input impedance buffer), and a sweeping circuit for is equal to the charging current of C1 and is related to the
aided acquisition as the positive feedback (OPA1-Schmitt voltage Vc(t) across the capacitor C1 by
trigger comparator, OPA2-integrator). A better under-
standing of this circuit is possible by referring to it as a tri- VCC – Voffset
=–
dVC1 t
C1
() (22)
angle wave generator circuit. Hence, the second-order
R5 dt
loop design formulas together with the triangle generator
design formulas are applicable. On the other hand,
Suppose that in the moment t0 = 0 the output of OPA1
is Vcc while OPA1 is in its positive saturation (OPA1 is a dVC1 t ( )C R
comparator). Hence, the current to the invert input of Voffset –
dt
1 2 ()
– VC1 t = VO t ( )OPA 2 (23)
OPA2 is
VCC – Voffset
ISW = (19) Since VCC and Voffset are constants, the charge is linear as
R5
already observed. Substituting Equation 22 into Equation
(This offset voltage has several names and meanings, for 23 and deriving it by t yields, as expected,
example, Voffset = Vtune-locking = Vbias.)
The constant positive current in Equation 19 will cause
dVO t ( )OPA 2 = – dVC1 (24)
a negative-going liner voltage ramp at the output of OPA2 dt dt
due to the charge of C1. At that time (using superposition)
the voltage at the noninverting input of the comparator Hence, the charging equation (after substituting Equation
OPA1 is given by 24 into Equation 22 and integrating the result) is
t1
VO t R () ( )OPA 2 =
VCC – Voffset
∫ dt
( )OPA1+
V t
V R
= CC 4 +
R6 + R 4
OPA 2 6
R6 + R 4
(20)
VO t
R 5C1
t0
(25)
 TECHNICAL FEATURE
The result is a linear ramp that cre- Combining Equation 26 with Equa- PHASE NOISE
ates the triangle wave described by tion 28 and writing the expression (t1 Phase noise at the output of a phase-
– t0) as ∆T and assuming VO(0) = 0 locked loop (PLL) can be calculated as
VO t ( )OPA 2 = results in a root mean square summation of all
the noise generators’ variances. The
1
(VCC – Voffset )(t1 – t0 ) + V0 (0)  V R 
∆T =  Vref – CC 4  noise generators considered here are
6 + R4 
R C 5 1  R the phase detector, VCO prescalers and
(26) dividers (if any), loop filter (operational
 R + R 4  R 5C1 amplifier), reference dividers or step
•  6  (29)
To calculate T/2, which is half of  R6  VCC – Vref recovery diode (SRD) that drive the
the triangle duration, there is a need microwave sampler in the case of PL-
to calculate the charging time until Therefore, the triangle frequency is DROs, VCOs and TCXOs.
the voltage at the noninverting input given by The noise contributions injected
of the comparator OPA1 reaches the into a PLL are shown in Figure 6.
reference voltage value applied at the 1 For convenience, these noise __ term
f= (30)
inverting input of the same opera- 2∆T variances (rms values) in V/√Hz have
tional amplifier. This equation is ex- been indicated as
pressed as Bearing in mind that optimum Vtune
for locking is VCC/2 and that Vref = φnR = reference TCXO phase noise
V t ( )OPA1– = Vref = VCC/2 since a symmetrical sweep is re- φnM = reference divider or SRD
phase noise
quired, Equation 29 can be simplified
VCCR 4
+
()
VO t R
OPA 2 6
(27)
so the triangle frequency is given by φnO = total output phase noise
φnN = emitter-coupled logic (ECL)
R6 + R 4 R6 + R 4 divider phase noise
R6
f= (31) φNvco = VCO phase noise
( )
Thus,
2 R6 – R 4 R 5C1 variance
VnD = phase detector phase
VO t ( )OPA 2 = In some cases the sweep circuit
may not operate due to improper de- noise
R6 + R 4  VCCR 4  sign of the comparator’s OPA1 hys- VnLPF = loop amplifier phase
 Vref –  (28) teresys. The hysteresis plot, generat- noise
R6  R6 + R 4 
ed using superposition calculation, is The objective now is to determine
shown in Figure 5. the phase noise transmission function
When the loop is locked the signal for each noise generator. Using con-
VCC
voltage coming from the sampling trol theory notation, the applicable
VO(t)OPA1 (V)

2R4 phase detector is at its maximum value.

SWEEP Vref noise equations are
RANGE R6 The current through R4 is higher than
the current through R5 and, hence, the φ nR
φ ni = + φ nM (32)
negative feedback becomes dominant. M
0 However, when the loop is out of lock,
the sampler output voltage drops. The
( )
φ neq = φ ni – φ'nO K PD (33)

[(φ ) ( )] K s
0 < VTr-min < VO-OPA2 VTr-rmar < VO-OPA2 current through R5 generated by the
R6 − R4 R6 + R 4 Schmitt trigger OPA1 becomes domi- neq + VPD + VnLPF H s VCO

R6 Vref R6 Vref nant and a new search triangle signal

VO (t)OPA2 (V) begins until the loop acquires lock. + φ nVCO = φ nO (34)
▲ Fig. 5 The OPA1 comparator’s hysteresis. When the loop is locked the negative φ nO
feedback becomes dominant, the posi- φ'nO = + φ nN (35)
N
tive feedback path is
θ'i
suppressed and the where
φnR θi VnLPF triangle sweep wave
φnM VnPD
is stopped. This de- KVCO = Vt-DRO modulation
H(s)
KPD KVCO/S scription dem- sensitivity (in radians/second
onstrates how a con- per volt)
Σ 1/M Σ Σ Σ
trol system automati- KPD = phase detector or sampling
TCXO
θ'nO φneq, θe cally operates its phase detector output
φnVCO positive feedback to sensitivity (in volts per
φnN θ'oφ bring the system to a radian)
stable point where H(s) = loop filter transfer function
the negative feed- N = prescaler (and VCO
Σ 1/N Σ
back suppresses the frequency divider) ratio
φnO positive feedback, M = reference divider ratio
θo
stabilizing the sys- After some manipulations, the ex-
▲ Fig. 6 Noise generators within a synthesizer. tem. pression becomes
 TECHNICAL FEATURE
 φ same conclusion also holds for the reference dividers or
 φ 
φ nO =  nR + φ nM  –  nO + φ nN   SRD, prescalers, loop amplifier and phase detector.
 M   N   Well inside the loop bandwidth (where the loop gain is
high — KPDKVCOH(s) → ∞), the output phase noise stan-
} ( )}
K
•K PD + VnPD + VnLPF H s • VCO + φ nVCO
s
(36) dard due to the TCXO can be approximated as
N
Rearranging the variables in a way that φnO is the subject σ nTCXO = φ nR (40)
of the formula, the PLL phase noise at its output becomes M
where
 K PDK VCOH s 

()  N = divider and prescaler ratio
 φ nR   s  M = reference divider ratio
φ nO =  + φ nM – φ nN  •
 M  
1 +
()
K PDK VCOH s 

In the actual case of a PLDRO, N = 1 and M = 1/MSRD,
where MSRD is the order of the reference frequency har-
 Ns  monic at which the Vt-DRO is locked. Thus, for a PLDRO it

()
holds that
 H s K VCO 
  σnTCXO = MSRDφnR (41)
 s 
[
+ VnPD + VnLPF • ] Frequency Divider

1 +
()
K PDK VCOH s 

Noise Contribution
The 1/N and 1/M frequency dividers’ contribution to
 Ns 
the output phase noise is given by a similar expression
1 that is almost identical (lowpass filtering action), such that
+ φ nVCO
()
(37)

1 +
K PDK VCOH s  () 
 K PDK VCOH s 
 
 Ns   s 
σ nN = φ nN • (42)
This result is interesting because it gives the transfer
function for each noise generator within the loop referred

1 +
()
K PDK VCOH s 

to the output. Furthermore, it can be easily investigated  Ns 
for phase noise optimization.
Since each noise term is uncorrelated, the phase noise
power spectral density may be obtained from Equation 37 by
mean square addition of the individual sources. The first ex- 
()
 K PDK VCOH s 

pression of this formula should be changed in sign from φnM  s 
– φnN to φnM + φnN since these variances are not correlated. σ nM = φ nM • (43)
Reference Source Noise Contribution

1 +
K PDK VCOH s( ) 
The TCXO output phase noise contribution to the out-  Ns 
put phase noise is given by
Like before, when the loop gain is high, the frequency di-
 K PDK VCOH s 
 
() viders’ noise contributions at the loop output are given by
 s  σnN = NφnN
φ nR σnM = NφnM
σ nTCXO = • (38) (44)
M 
1 +
K PDK VCOH s ( )  As already discussed, in the PLDRO, N = 1 and φNr =
 Ns  0 (no VCO dividers are used). Thus, the noise term that
remains is the SRD contribution σnM = φnM. As a result,
Assuming that H(s) describes an active filter, using Equa- the PLDRO has the benefit of a lower noise floor within
tions 5, 6, 7, 9 and 10 transforms Equation 38 into the loop compared to the usual PLLs.

φ nR 2ξω nS + ω 2n Phase Detector Noise Contribution

σ nTCXO = • 2 (39) By changing the notation of the phase detector expres-
M s + 2ξω ns + ω n2 sion in Equation 37, the phase detector noise contribution
Equation 39 shows that the reference source (TCXO) phase can be written as

()
noise within the loop is multiplied by the closed-loop lowpass
 K PDK VCOH s 
transmission function with a –20 dB per decade slope, and  
will be attenuated outside the loop. Hence, the closed-loop  s 
VnPD
sharpness defines the amount of the TCXO phase noise that σ nPD = • (45)
is enhanced outside the loop bandwidth. For this reason, the K PD 
1 +
K PDK VCOH s ( ) 
damping factor ξ of the loop has a significant impact on the
phase noise characteristic outside the loop bandwidth. This  Ns 
 TECHNICAL FEATURE
Again, this expression is a lowpass function as seen previ-
ously. In the same way, inside the loop band (where the
loop gain is high) the phase detector rms noise contribu-
tion at the PLL output is expressed as
N phase noise of the free-running VCO coincides with the
σ nPD = VnPD (46)
K PD
In the case of a PLDRO, N = 1 (no VCO divider is used)
— another reason why the noise floor within the loop is
much lower compared to a classical synthesizer. Additional-
ly (both in a PLDRO and synthesizer), a higher phase de-
tector gain will reduce the noise floor within the loop band-
width. In the case of a PLDRO, a higher phase detector
gain means that a higher beat note output is required from
the microwave sampler. The disadvantage is that the sam-
pler must be driven with a higher power signal at mi-
crowave frequencies. In an ordinary charge-pump synthe-
sizer, this increase of phase detector gain will usually affect
the level of spurious signals around the output carrier.
Loop Amplifier Noise Contribution
In the same manner, the loop amplifier noise contribu-
tion is expressed as
()
 K PDK VCOH s 
 
General Considerations
It can be demonstrated that the optimum choice for
the loop bandwidth (that is, the one that minimizes the
output phase noise variance) is the frequency at which the
total noise floor coming from the reference and phase de-
tector side. In the transition region close to the loop cor-
ner frequency, the output phase noise can become higher
than the free-running VCO noise. In fact, since the HPF
function is given by HPF(s) = 1 – LPF(s) where LPF(s) is
the closed-loop transfer function, the optimization of in-
band phase noise will affect the out-of-band phase noise
and vice versa. For example, a sharp lowpass filter (LPF)
function means a sharp HPF function and better suppres-
sion of the VCO or Vt-DRO noise inside the loop fre-
quency limits. Of course, this condition will require a high
damping factor ξ and higher overshoot of the transfer
function with subsequent increase of the phase noise in
that offset frequency range.
With the previously described method, each phase
noise contribution can be calculated separately by using
an appropriate CAD method. The total output phase
noise then can be obtained using the root mean square
notation:

VnLPF  s  σ = σ 2nPD + σ 2nTCXO + σ 2nN + σ 2nM + σ 2nVCO + σ 2nLPF (51)

σ nLPF = • (47)
K PD 
1 +
K PDK VCOH s( ) 
This frequency-dependent function gives the overall
 Ns 
phase noise spectrum log.
Since the noise generators’ contributions are expressed in
As explained previously, inside the loop band (where the rms terms, each contribution X can be expressed in logarith-
loop gain is high), the loop active filter rms noise contri- mic units by calculating 20logX. For example, considering
bution at the PLL output is given by the phase detector noise expressed by Equation 46 yields
N
σ nLPF = VnLPF (48) N
K PD σ nPD = 20 log VnP + 20 log (52)
K PD
Again, a high phase detector gain will improve the phase In this manner, so-called single-sideband phase noise can
noise characteristic within the loop bandwidth. be obtained in dBc/Hz just as it would be displayed by a
VCO Phase Noise Contribution spectrum analyzer. (Note that the parameter 20logVnPD
The VCO phase noise transfer function is given by should be given by the manufacturer of the device or can
be evaluated.) The overall phase noise (PN) within the
1
σ nVCO = φ nVCO • (49) loop bandwidth or outside the loop bandwidth in dBc/Hz
1+
K PDK VCOH s () notation is given by
Ns PN(dBc/Hz) = 20logσ (53)
Replacing H(s) as in Equation 5 produces
LOOP FILTER
s2 AND ACQUISITION CIRCUIT OPTIMIZATION
σ nVCO = φ nVCO (50)
s 2 + 2ξω ns + ω 2n Design Procedure
The loop filter is a second-order integrator with opti-
This expression describes a highpass filter (HPF) charac- mized ω3dB to obtain good phase noise matching between
teristic with a 40 dB per decade slope, which means that the loop noise floor and free-running Vt-DRO phase noise.
the phase noise generated by the VCO (or Vt-DRO) is Following the PLDRO design steps, the ω3dB of the loop
strongly attenuated within the loop limits. At higher offset (and the damping factor ξ) is defined considering phase
frequencies (far from the carrier) where there is no more noise requirements. Next, the SPD beat note peak-to-peak
feedback action, the output phase noise becomes equal to output voltage VBN is measured (or determined from the
the free-running phase noise of the VCO or Vt-DRO data sheet) and KPD of the SPD is calculated using
alone. Hence, the best phase noise limit of a synthesizer
or PLDRO is defined by the free-running VCO or Vt- VBN
K PD =
DRO phase noise characteristic. 2
 TECHNICAL FEATURE
the middle of the sweep voltage the positive feedback such that
swing range by using the tuning
120 120
screw. This point is defined by the VCC – Vref beat notemax
LOOP DELAY
<
GAIN (dB)

PHASE (°)
60 60
hysteresis of the OPA1 comparator. R5 R1
0 0
80° PHASE C1 is selected and the remaining loop
−60 −60 VCCR 9
MARGIN parameters are calculated using Vref =
−120 −120 R3 + R9
K dK V If necessary, R5 is increased in value
1 1K 10M τ1 =
FREQUENCY (Hz) ω 2n to slow down the sweep rate.
2ξ Lock Indication Circuit
▲ Fig. 7 Phase and gain margin. τ2 =
ωn The lock indication circuit samples
▼ Fig. 8 Phase noise simulation.
τ1 the output of the comparator amplifi-
R1 = er or the tuning voltage Vtune. When-
−25 C1
ever the loop is out of lock the square
PHASE NOISE (dBc/Hz)

τ2 wave voltage will generate a 0 (low

R2 =
−85 C1 level). When the loop is locked the
−100 square wave stops and the output lev-
−102.5 The maximum allowable sweep rate el is 1. However, the level indicating a
is defined using Viterbi’s condition correct lock can be 0 and then a 1 will
indicate the unlocked state, depend-
−170 ω2 ing on the system requirements.
1 1K 400K 1M ∆˙ω < n
FREQUENCY (Hz)
2 There are several ways to implement
More margin is added if needed. (For such a circuit. For example, a sample-
example, and-hold circuit or an absolute value
10 circuit, where the fluctuating voltage
ω 2
is detected, may be used.
TRANSMISSION (dB)

3 dB ∆˙ω = 0.1 n
2
may be used.) The required triangle MEASURED RESULTS
−20 half-period T/2, expressed in seconds, Three very low cost PLDROs
is calculated using were designed, built and tested at
9.5, 11.3 and 15.5 GHz. The refer-
−50
48K T 2π • SR ence frequency was 50 MHz. CAE
=
1 1K 10K 10M
2 ∆˙ω optimization techniques were used to
FREQUENCY (Hz) optimize the loop stability, phase
where noise and acquisition performance,
▲ Fig. 9 The closed-loop
showing good agreement with the
transmission function. SR = sweep range of the Vt-DRO
(Hz) measured results. The performance
Fig. 10 Phase noise at 11.3 GHz measured of a 11.3 GHz low cost PLDRO ex-
in a 3 kHz bandwidth. ▼
Next, the OPA2 comparator feedback ample for a local multipoint distribu-
values are calculated and optimized tion system application is shown in
NOISE (dBc/3 kHz)

0 for the required sweep time. Arbi- Figures 7, 8, 9 and 10.

RETURN PHASE

−20 trary initial values are selected for R4

−40 or R6 and final values are calculated CONCLUSION
−60
from the relation of the SR voltage When designing an aided search/
−101 dB/Hz swing VSR defined by the comparator acquisition PLDRO, the rise and fall
−80
hysteresis limitations times of the sweep signal are crucial
−110 0 110
parameters. A low frequency sweep
OFFSET FREQUENCY (kHz) 2R 4 V signal with fast rise and fall times such
VSR = Vref at Vref = CC
R6 2 as a square wave or exponential wave
Bear in mind that a high beat note is not adequate because the sweep
voltage is required for good phase Remembering that Vref = VCC/2, R5 is rate is much too fast and will be inter-
noise. The loop natural frequency ω calculated using preted as a chirp modulation. The
then is calculated using phase error θe transmission function
R6 – R 4 of a PLL is an HPF so the fast tran-
ω 3dB ∆T = R 5C1
ωn = R6 sient interrupt will pass directly to the
VCO output and the feedback path
( 2 ξ + 1)
2
2ξ 2 + 1 + 2
+1 Finally, the current through R 5 is will not be able to track it. Dual-feed-
compared with the current through back circuits such as a classical Wien
Next, the Vt-DRO sweep range (SR) R1 (beat notemax is the peak voltage at bridge are not recommended due to
in Hertz is defined. The locking Vt the SPD output) to verify that the their temperature sensitivity. Finally,
must be optimized to be located at negative feedback can prevail over special consideration should be taken
 TECHNICAL FEATURE
when selecting the SPD to optimize
References
phase noise performance.
ACKNOWLEDGMENT
The author would like to thank
Boris Vainer, the project develop-
ment technician, for his aid on tests
and help in carrying out the project’s
tasks from its conception to success-
ful completion. Thanks also go to Mr.
Kondoh, Mr. Onoda and Mr. Rolhoff
for the samples, and A. Villa for re-
viewing this article. ■
Avi Brillant received
his BSc degree in
1. Gardner Phaselock Techniques, Second electrical engineering
Edition, John Wiley and Sons, New York. from the Technion
2. Heinrich Meyr and Gerd Ascheid, Syn- Israel Institute of
chronization in Digital Communications, Technology, Haifa in
Vol. 1, John Wiley and Sons, New York. 1986. From September
3. Alex Hodisan, Ziv Hellman and Avi Bril- 1986 to July 1993, he
lant, “Method Optimizes Performance of was employed at
PLLs,” Microwaves & RF, September MicroKim Ltd. in
1994, pp. 87–96. Haifa as a design
4. Alex Hodisan, Ziv Hellman and Avi Bril- engineer in the
lant, “CAE Software Predicts PLL Phase amplifiers and sources group. In 1993, Brillant
Noise,” Microwaves & RF, November joined MTI Technology and Engineering Ltd.
1994, pp. 95–102. in Tel-Aviv as a system engineer. He was also a
5. V.F. Kroupa, “Noise Properties of PLL Sys- consulting engineer for BreezCom. In July
tems,” IEEE Transactions on Communica- 1995, he joined Optomic Microwaves Ltd. in
tions, October 1982, pp. 2244–2251. Migdal Ha’Emek as a senior engineer in charge
6. Millman Halkias, Integrated Electronics, of communications products for VSAT, LMDS,
McGraw-Hill. microwave, mm-wave link and cellular
applications. Brillant is a member of the Israeli
MMIC Consortium.