4885 – P.
1 To Appear in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Using Launch-on-Capture for Testing BIST
Designs Containing Synchronous and
Asynchronous Clock Domains
Laung-Terng Wang, Fellow, IEEE, Xiaoqing Wen, Senior Member, IEEE,
Shianling Wu, Member, IEEE, Hiroshi Furukawa, Hao-Jan Chao, Member, IEEE, Boryau Sheu,
Jianghao Guo, and Wen-Ben Jone, Senior Member, IEEE
Abstract—This paper presents a new at-speed logic
Built-In Self-Test (BIST) architecture supporting two
launch-on-capture schemes, namely aligned
double-capture and staggered double-capture, for
testing multi-frequency synchronous and asynchronous
clock domains in a scan-based BIST design. The
proposed architecture also includes BIST debug and
diagnosis circuitry to help locate BIST failures. The
aligned scheme detects and allows diagnosis of
structural and delay faults among all synchronous clock
domains, whereas the staggered scheme detects and
allows diagnosis of structural and delay faults among all
asynchronous clock domains. Both schemes solve the
long-standing problem of using the conventional one-hot
scheme which requires testing each clock domain one at
a time or the simultaneous scheme which requires
adding isolation logic to normal functional paths across
interacting clock domains. Physical implementation is
easily achieved by the proposed solution due to the use of
a slow-speed, global scan enable signal and reduced
timing-critical design requirements. Application results
Manuscript received May 12, 2008; revised November 12, 2008.
Laung-Terng Wang is with Dept. of Electrical Engineering and
Graduate Institute of Electronics Engineering at National Taiwan
University, and SynTest Technologies, Inc., 505 S. Pastoria Ave., Suite
101, Sunnyvale, CA 94086, USA (1-408-720-9956x200; fax:
1-408-720-9960; e-mail: wang@syntest.com).
Xiaoqing Wen is with Dept. of Creative Informatics, Kyushu Institute of
Technology, Iizuka, Fukuoka 820-8502, Japan (e-mail:
wen@cse.kyutech.ac.jp).
Shianling Wu is with SynTest Technologies, Inc., Princeton Junction,
NJ 08550, USA (e-mail: shianlingwu@syntest.com).
Hiroshi Furukawa is with Dept. of Creative Informatics, Kyushu
Institute of Technology, Iizuka, Fukuoka 820-8502, Japan (e-mail:
hiroshi.furukawa@nms.necel.com).
Hao-Jan Chao is with SynTest Technologies, Inc., 2F, No. 27, Industry
E. Road 9, Science-Based Industrial Park Hsinchu, Taiwan (e-mail:
tom_chao@syntest.com.tw).
Boryau Sheu was formerly with SynTest Technologies, 505 S. Pastoria
Ave., Suite 101, Sunnyvale, CA 94086, USA (e-mail:
jack_sheu@sdesigns.com).
Jianghao Guo is with Dept. of Electrical and Computer Engineering,
University of Cincinnati, OH 45221, USA (e-mail: guojh@email.uc.edu).
Wen-Ben Jone is with Dept. of Electrical and Computer Engineering,
University of Cincinnati, OH 45221, USA (e-mail: wjone@ececs.uc.edu).
Digital Object Identifier 09.0909/TCAD.2009.826558
for industrial designs demonstrate the effectiveness of
the proposed architecture.
Index Terms—Aligned Double-Capture, At-Speed
Self-Test, Double-Capture, Launch-on-Capture, Logic
BIST, Staggered Double-Capture
I. INTRODUCTION
L OGIC Built-In Self-Test (BIST) [1]-[7] is a
Design-for-Testability (DFT) technique in which a
portion of a circuit on a chip, board, or system is used to test
the digital logic circuit itself. Logic BIST is crucial for many
applications, in particular, for life-critical and
mission-critical applications. These applications commonly
found in the aerospace/defense, automotive, banking,
computer, health care, networking, and telecommunications
industries require on-chip, on-board, in-system, and in-field
self-test to ensure the reliability of the entire system, as well
as its ability to perform remote test and diagnosis.
The logic BIST technique widely used in industry is based
on the STUMPS (Self-Test Using a MISR and Parallel Shift
register sequence generator) structure [8]. In the STUMPS
architecture, a Pseudorandom Pattern Generator (PRPG) is
used to generate pseudorandom patterns and shift each
pattern in parallel to the inputs of the scan chains embedded
in a scan-based design, and a Multiple-Input Signature
Register (MISR) is used to compact the test responses
shifted out of the scan chain outputs to create a signature.
After a pre-determined number of test cycles are executed,
the final signature is then compared against an embedded
golden (good circuit) signature to judge whether the circuit
under test (CUT) passes or fails. As no test patterns are
supplied externally, logic BIST can reduce test cost and also
allow the circuit to perform in-field self-test.
While logic BIST offers many benefits, its real value is in
providing at-speed testing for high-speed and
high-performance circuits. These circuits often contain
multiple clock domains, each running at a frequency that is
either synchronous or asynchronous to the other clock
domains. Two clock domains are said to be synchronous if
the active edges of both clocks controlling the two clock
domains can be aligned precisely or triggered
4885 – P. 2 To Appear in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
simultaneously. Two clock domains are said to be
asynchronous if they are not synchronous.
Despite its conceptual simplicity, logic BIST faces many
practical hurdles, especially in at-speed testing for
multi-clock, multi-frequency circuits. Each clock in such a
circuit controls a clock domain, whose clock skew is
minimized and which runs at a frequency either synchronous
or asynchronous to other clock domains. The most critical
yet difficult part of logic BIST is how to detect
intra-clock-domain faults and inter-clock-domain faults
thoroughly and efficiently with a proper capture-clocking
scheme. An intra-clock-domain fault originates at one
clock domain and terminates at the same clock domain. An
inter-clock-domain fault originates at one clock domain
but terminates at another clock domain.
Previous STUMPS-based logic BIST schemes [9]-[11]
have not been effectively applied in practice. The reasons
are mainly due to the need to manipulate test frequency when
the CUT contains asynchronous clock domains, and the
difficulty in timing control and physical implementation.
Alternatively, a conventional at-speed BIST scheme using
one-hot clocking or simultaneous clocking would need to
test one clock domain at a time resulting in long test time or
add isolation logic to normal functional paths across
interacting clock domains resulting in fault coverage loss
across these clock domains.
These problems will be addressed in this paper, with a new
logic BIST architecture using launch-on-capture schemes -
aligned clocking and staggered clocking - that achieves
true at-speed test quality for any multi-clock,
multi-frequency design and that is easy for physical
implementation.
It should be noted that all above-mentioned
capture-clocking schemes are applicable for both BIST
designs and scan designs. The main difference is that for
BIST designs no unknown (X) values are allowed to
propagate through the scan chains to reach the MISR.
Throughout this paper, we will assume that a
STUMPS-based architecture is used and that each clock
domain contains one test clock and one scan enable signal.
The faults we will consider for comparison include
structural faults, such as stuck-at faults and bridging faults,
as well as timing-related delay faults, such as path-delay
faults and transition faults.
The rest of the paper is organized as follows: Section 2
describes the background. Section 3 presents the logic BIST
architecture. Section 4 discusses at-speed timing control
issues, and Section 5 focuses on physical implementation
issues. Section 6 shows results on several industrial designs,
and Section 7 concludes the paper.
II. BACKGROUND
There are two basic capture-clocking schemes for testing
multiple clock domains at-speed: (1) skewed-load (which is
now commonly called launch-on-shift [LOS]) [12] and (2)
double-capture (which was called broad-side in [13] but is
now commonly called launch-on-capture [LOC]). Both
schemes are helpful for detecting structural faults and delay
faults within each clock domain (called intra-clock-domain
faults) or across clock domains (called inter-clock-domain
faults). Skewed-load uses the last shift clock pulse followed
immediately by a capture clock pulse to launch a transition
and capture its output test response, respectively.
Double-capture uses two consecutive capture clock pulses to
launch the transition and capture the output test response,
respectively. In either scheme, both launch and capture clock
pulses must be running at the domain’s operating speed or
at-speed. The difference is that skewed-load requires the
domain’s scan enable signal SE to switch its value between
the launch and capture clock pulses making SE function as a
clock signal. Figure 1 shows sample waveforms using the
basic skewed-load and double-capture at-speed test
schemes.
Typically, testing a scan-based BIST design based on
skewed-load for at-speed delay fault testing can achieve
higher fault coverage with shorter test length [14]-[20].
Although some novel DFT techniques as proposed in [21]
and [22] have addressed the timing problem of operating the
scan enable signal SE at-speed for each clock domain,
skewed-load can cause unwanted over-testing because more
false paths can be exercised, and incur higher
implementation cost associated with the at-speed scan
enable signal SE. This is in sharp contrast to double-capture
in which only a slow-speed, global scan enable signal GSE
for all clock domains is needed.
Therefore, this paper will focus on logic BIST architecture
based on double-capture. There are two known at-speed
Capture
Launch
CK
SE
Shift Shift Last Shift
Shift
capture-clocking schemes: (1) one-hot double-capture that
conducts capture for one clock domain at a time and (2)
Capture
Launch
CK
SE
Shift Shift Dead Shift
Cycles
simultaneous double-capture that allows testing to be
performed on all clock domains in parallel.
(a) Skewed-load (a.k.a. Launch-on-shift)
(b) Double-capture (a.k.a. Launch-on-capture)
Fig. 1. Basic at-speed test schemes.
A. One-Hot Double-Capture
The one-hot double-capture scheme tests clock domains
one by one. A sample timing diagram for two clocks is
shown in Fig. 2. The main advantages are that (1) two
consecutive capture pulses are applied (C1-followed-by-C2
or C3-followed-by-C4) at their respective clock domains’
4885 – P. 3 To Appear in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

frequencies (of period d1 or d2) to test intra-clock-domain main focus of this paper. In the following, we propose novel
delay faults, and (2) a single, slow-speed global scan enable logic BIST architecture and launch-on-capture schemes for
signal GSE is used to drive both clock domains. detecting intra-clock-domain faults and inter-clock-domain
faults in a multi-frequency circuit containing both
Shift Window Capture Window Shift Window Capture Window Shift Window
C1 C2 synchronous and asynchronous clock domains. The
CK1 … … …
d1 proposed launch-on-capture (or double-capture) schemes
C3 C4
CK2 … … … are intended to increase the fault coverage of the circuit. The
d2
GSE new architecture implemented with the schemes is intended
to facilitate physical implementation as well as debug and
Fig. 2. One-hot double-capture. diagnosis of ASIC devices from the system level down to the
Hence, this scheme can be used for true at-speed testing of chip level [23]-[26]. The architecture requires a BIST-ready
intra-clock-domain delay faults in both synchronous and core that has complied with all scan and BIST design rules.
asynchronous clock domains. However, this scheme suffers
from two drawbacks in that (1) it cannot be used to detect III. LOGIC BIST ARCHITECTURE USING
inter-clock-domain delay faults and (2) it has long test time. LAUNCH-ON-CAPTURE
B. Simultaneous Double-Capture
A. General Architecture
The long test time problem of one-hot double-capture can The proposed logic BIST architecture is illustrated in Fig.
be resolved by using the simultaneous double-capture 4. The BIST architecture for testing the BIST-ready core
scheme illustrated in Fig. 3. The simultaneous consists of a test pattern generator (TPG) for generating test
double-capture scheme allows testing to be performed on
stimuli, an input selector for providing pseudorandom or
all clock domains in parallel. However, since data may
top-up ATPG patterns for the core-under-test, an output
propagate from one clock domain to the other clock domain,
response analyzer (ORA) for compacting test responses, a
isolation logic (or capture-disabling circuitry), such as
AND/OR gates or multiplexers, must be added at the clock gating block (discussed in Section IV-C) for
sources, sinks, or along the normal functional paths to force generating test clocks from original or functional clocks, and
all inter-clock-domain paths to exhibit constant values of 0’s a BIST controller for coordinating the whole BIST
or 1’s at the receiver side. operation. The top-up ATPG patterns can include
compressed ATPG patterns to improve the circuit’s fault
Shift Window Capture Window Shift Window coverage during manufacturing test, when the
C1 C2 combinational-logic-based scan compression architecture as
CK1 … …
proposed in [27]-[29] is embedded in the design. The test
C3 C4 clocks are placed in a predetermined order of sequence (see
CK2 … … Section IV) so that single-capture or double-capture clock
GSE pulses can be supplied to the BIST-ready core. The self-test
operation is started by asserting the Start signal, its end is
Fig. 3. Simultaneous double-capture. indicated by the Finish signal, and its result is shown by the
Result signal. A standard IEEE 1149.1 Boundary-Scan
The major advantages of this approach are that (1) all interface under the control of the test access port (TAP)
intra-clock-domain (structural and delay) faults can be tested controller is used for loading initialization and configuration
simultaneously thus yielding much shorter test time and (2) data or for downloading internal states for fault diagnosis.
there is no need to worry about the clock skew issue between
any two clock domains, be they synchronous or TPG
asynchronous. This approach, however, requires that CK1
PRPG1 PRPG2
isolation logic be inserted across all interacting clock CK2
PS1/SpE1 PS2/SpE2
domains so each clock domain can be tested independent of
Start
all other clock domains. The insertion of isolation logic into Finish Input Selector PIs/SIs
Result
the domain boundary exposes the design to one major
TDI CCK1 TCK
drawback which is not present in one-hot double-capture: TDO Clock 1
Clock Clock
Controller CCK2 Gating TCK2 Domain C Domain POs/SOs
the added circuitry to isolate all interacting clock domains TCK Block #1 #
#2
TMS
may increase the propagation delay of the design in normal BIST-Ready Core
mode and will prevent all inter-clock-domain faults -
structural faults and delay faults - from being detected. SpC1 SpC2
As the one-hot double-capture or simultaneous MISR1 MISR2
double-capture scheme cannot detect inter-clock-domain ORA
delay faults, how to preserve all benefits of both schemes
while at the same time remove all of their drawbacks is the Fig. 4. Logic BIST architecture.
4885 – P. 4 To Appear in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
B. BIST-Ready Core
The BIST-ready core is a full-scan circuit (scan design)
that satisfies all scan design rules. Additional circuitry may
need to be added for preventing bus conflicts at tri-state
buses and for disabling asynchronous set/reset signals and
false paths. In addition to scan design rules, the BIST-ready
core must also satisfy all BIST-specific design rules, such as
X-blocking and for test point insertion (TPI). X-blocking
which blocks all unknowns (X’s) from reaching the scan
outputs is conducted in an intelligent way so that critical
paths are avoided and that the X-blocking circuitry is placed
as close to the X-source as possible. TPI is guided by fault
simulation results. In addition, all multi-cycle paths and false
paths may be selected or blocked depending on test needs.
C. TPG Circuitry and ORA Circuitry
In general, clock skews between two interacting clock
domains in a BIST-ready core, as shown in Fig. 4, are not
aggressively managed. In order to avoid additional design
efforts for clock skew management in logic BIST, two
PRPG-MISR pairs, one for each clock domain, can be used,
even though both clock domains may operate at the same
frequency. However, if hardware overhead is a major
concern, one PRPG-MISR pair can be used. Also, linear
phase shifters, (PS1 and PS2) (a.k.a. space expanders [SpE1
and SpE2]) can be used to reduce the length of PRPGs, and
space compactors (SpC1 and SpC2) can be used to reduce the
length of MISRs.
D. Test Control Circuitry
The test control circuitry consists of a BIST controller and a
clock gating block. The inputs to the clock gating block are
system clocks CK1 and CK2, which become CCK1 and CCK2
after going through some buffers. The two clocks CCK1 and
CCK2 are in fact used by the PRPG and MISR pair as will be
discussed in Section V. In addition, the clock gating block is
controlled by signals from the BIST controller to generate
test clocks TCK1 and TCK2. The timings of TCK1 and TCK2,
especially in capture mode, play a critical role in determining
the test capability and physical implementation easiness of
the logic BIST scheme. The BIST controller works in tandem
with an embedded TAP controller, which complies with the
IEEE 1149.1 Boundary-Scan standard to coordinate the test,
debug, and diagnosis tasks.
E. Debug and Diagnosis Circuitry
In addition to Logic BIST, diagnosis of the BIST-ready
core at the core level and then down to the failed scan chain
and signature cycle levels, to locate faulty scan cells and
logic gates, is also important. Many innovative BIST debug
and diagnosis approaches have been proposed and surveyed
in [5], [6], [30], and [31]. This subsection details a few
unique design for debug and diagnosis (DFD) features.
E-1. Core-Level Diagnosis
To facilitate test, debug, and diagnosis, each clock domain
(core) is embedded with a unique core-identifier (CID) bit to
decide whether this clock domain will be targeted or not [32].
A design for debug and diagnosis (DFD) circuitry including
the CID bit register will be surrounding all BIST cores that
have been synthesized with their respective logic BIST
controllers under boundary-scan control. There will be an
isolation wrapper for each core. With the objective to enable
end-to-end debug and diagnosis from core to in-field
applications, these CID bits are stitched to form a shift
register, a CID register, so during test, debug, and diagnosis,
these bits can be programmed on-the-fly and these cores are
tested either in series or in parallel.
In order to debug or diagnose logic BIST cores in an
integrated circuit, one first sets the CID bits of the BIST
cores to be diagnosed to all 1’s. These cores can then be
processed in parallel. In addition to single error diagnosis,
the CID register can further include additional bits in each
logic BIST core, when desired, to increase diagnostic
resolution for multiple errors that may arise from different
faults, such as stuck-type faults, delay faults, or bridging
faults.
There are a number of benefits with this CID approach.
First, it allows designers to enable or disable diagnosis of
selected BIST cores at any time. Second, it allows designers
to skip the failed BIST cores and focus on diagnosis of other
BIST cores. Third, it allows designers to perform multiple
error diagnosis. Finally, it allows test engineers to manage
power consumption during production testing by selectively
choosing BIST cores for serial/parallel testing.
E-2. Signature Diagnosis
The logic BIST (LBIST) architecture includes special DFD
circuitry to help locate BIST failures down to all failed
signature cycles. When BIST does not pass a manufacturing
test or a system test, designers can utilize the DFD circuitry to
enter the signature diagnosis mode by loading initial seeds
into the PRPG and the MISR, as well as the required number
of LBIST cycles to perform signature diagnosis.
When the logic BIST operation in the logic BIST
controller completes the selected LBIST cycles, the
controller will issue a cycle-end signal, halt the BIST
operation, and begin to wait for a continue signal to resume
its BIST operation and to reset the cycle-end signal. During
this period, all LBIST output responses are captured
repeatedly into a test-and-diagnosis (TDR) register to form
an intermediate signature that will be shifted out for analysis.
If the intermediate signature does not agree with the expected
signature during analysis, designers can further instruct the
TAP controller to inform the controller to issue the continue
signal to resume the logic BIST operation. The BIST
operations are repeated until designers have located the first
failed BIST pattern (signature cycle) or all failed BIST
patterns.
This cycle-based signature diagnosis approach indicates
that the contents of the TDR register are only sampled after a
cycle-end signal is received. If there are many BIST
operations to be performed in parallel, the TAP controller
must wait until all cycle-end signals have been generated. In
addition to loading the initial seeds for the PRPG and the
MISR, the TDR register shown in Fig. 5 stores additional
LBIST data including the golden signature for comparison
with the MISR, pattern counter, scan-chain mask, cycle-mask
4885 – P. 5 To Appear in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
start index, cycle-mask stop index, and programmable shift
and capture modes. Additional seeds can also be
pre-computed ahead of time. Those seeds are then loaded
into the BIST core to run multiple, short, logic BIST test
sessions to further help with diagnosis.
TDO
P/F Pass/Fail Indicator
X Scan -Chain Mask
Y Cycle -Mask Start Index
Z Cycle -Mask Stop Index
PSM1
PC Pattern Counter
Programmable Shift Mode
PSM2
PSM
PCM Programmable Capture Mode
SEED Initial seeds for PRPG and MISR
SIG Final Signature of MISR
TDI
Fig. 5. Contents of the test-and-diagnosis (TDR) register.
There are a number of advantages in using this
test-and-diagnosis (TDR) register for signature diagnosis.
First, it can locate failed patterns. Second, it can further
locate multiple capture errors in the scan chain. Finally,
linear search or binary search can be employed to reduce the
diagnosis time.
Since the TDR register contains a pattern counter in
support of the cycle-based approach, the LBIST controller is
capable of launching test sessions with varying pattern counts,
i.e., a test session with its required test patterns derived from
pre-computed logic/fault simulation, or a test session with a
predetermined pattern count. For diagnosis purposes, a test
session can be of a single pattern, thereby allowing designers
to apply test patterns one-by-one to sort and identify failed
patterns for the entire test set. Alternatively, a binary search
can be used to speed up finding the failed patterns through
interactive test sessions between the device-under-debug and
the tester (or system). As the TDR register supports reseeding
of the PRPG/MISR, designers can adjust the starting and
ending points of a test session according to test and diagnosis
needs. The identification of failed patterns must be done
before proceeding to masked-chain or one-chain diagnosis to
minimize the time-consuming diagnosis effort.
E-3. Masked-Chain Diagnosis
The DFD circuitry also includes the XYZ diagnosis
structure proposed in [33] and the improved masking
methods developed in [34] to locate the failed scan chain(s)
and the associated failed scan cells in each failed scan chain.
An LBIST TDR register for debug or diagnosis of LBIST
failures is embedded in each core. The XYZ operation using
the contents of the TDR register shown in Fig. 5 in support of
XYZ diagnosis is illustrated in Fig. 6, where the X field
indicates which scan chain(s) to mask; Y and Z fields indicate
which ranges of scan cells in the scan chain(s) to mask.
For n scan chains, there will be n bits in the X field and n
AND gates in the masked-scan diagnosis (MCD) logic
feeding the MISR. A 0 set to the ith bit of the X field, X(i)=0,
where 0<i<n, causes the MISR to receive a constant 0 for the
ith chain. The method of feeding constant values to the MISR
is called a masking mechanism. With this embedded
scan-chain masking logic, designers can run test sessions in a
linear or binary search fashion to locate faulty chain(s).
PRPG Scan Chain MISR
&
&
S
S
E
& I
E
G
D
Scan Chain
Scan-Chain
Masking Logic
TDI TDO
PCM PSM PSM1
PC Z Y X P/F
Fig. 6. Masked-chain diagnosis (MCD) logic diagram.
Once a faulty chain is identified, the next task is to locate
the faulty scan flip-flops within the chain. The Y and Z fields
specify the start and stop indices of the scan flip-flops. The
cycle-mask start index and cycle-mask stop index will allow
the logic BIST controller to skip the region (cycles) where
failed scan flip-flops reside so BIST diagnosis can still be
performed on the remaining fault-free scan cells. The
masked-chain diagnosis feature is also helpful for unknown
(X) masking in case the X-sources fall within a small fraction
of the scan index or range. The programmable shift and
capture modes are to shift the scan chains at a selected,
reduced frequency to avoid overheating as well as to select
the number of capture clock pulses for stuck-at or delay fault
testing during capture, respectively.
E-4. One-Chain Diagnosis
The DFD circuitry further includes additional test
mechanism to dump all scan values from the reconfigured
scan chains. Assume a failed pattern (signature cycle) has
been located during signature diagnosis or XYZ diagnosis.
The TAP controller can then load an instruction to the TDR
register and instruct the logic BIST controller to (1) set the
TDR register to one-chain diagnosis (OCD) mode, and (2)
shift out the contents of all scan cells in the scan chains which
are reconfigured as an OCD register for analysis. The
reconfigured OCD register is treated as one of the several
data register chains of the TAP controller after the diagnostic
instruction register has been decoded.
As the number of failed patterns could be large, all failed
patterns are fault graded such that the number of diagnostic
patterns being applied in OCD mode can be reduced without
affecting the resolution of finding the root cause from the
failed combinational logic. Additional diagnostic patterns
can then be shifted into the scan chains to pinpoint the failed
combinational logic gates. This allows the BIST core to be
debugged and diagnosed at the board or system level,
enabling in-field diagnosis [35].
4885 – P. 6 To Appear in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
IV. TEST TIMING CONTROL
This section proposes test timing control methods for
capture clocking. Techniques to improve fault coverage and
ease physical implementation are then discussed.
A. Basic Approach
The basic idea is to use an ordered sequence of capture
clocks for all clock domains in each capture window
[23]-[26]. The order can be properly selected based on test
requirements.
A-1. Staggered Single-Capture
Single-capture is a slow-speed test technique in which
only one capture pulse is applied to each clock domain. It is
the simplest approach for detecting all intra-clock-domain
and inter-clock-domain structural faults. No
intra-clock-domain delay faults can be detected within each
clock domain. An example of low-speed test timing control
is shown in Fig. 7, where test clocks TCK1 and TCK2 are
staggered and generated by the clock gating block shown in
Fig. 4. In this approach, capture pulses C1 and C2 are applied
in a sequential or staggered order within the capture window
to test all intra-clock-domain and inter-clock-domain
structural faults in the two clock domains. For synchronous
clock domains, adjusting d2 will allow us to detect
inter-clock-domain delay faults between the two clock
domains at-speed.
For asynchronous clock domains, we often can only detect
inter-clock-domain structural faults, not inter-clock-domain
delay faults. As synchronization circuits (or two-flop
synchronizers) are mostly used as a handshaking protocol to
transfer data between two asynchronous clock domains in
normal mode [36]-[37], it is still possible to detect
inter-clock-domain delay faults as long as the delay d2 can be
properly adjusted (or programmed) via the logic BIST
controller. Theoretically, a synchronizer can tolerate any
delay, so testing of an inter-clock-domain delay fault across
asynchronous clock domains appears to be not required.
However, an excessive delay in the “request” circuit
(including the synchronizer) or the data path across the two
asynchronous clock domains might not be allowed in a
design which implements a real-time system. Thus, by
adjusting the d2 value, the excessive delay can also be
detected by this clocking scheme. The value of d2 depends
on the circuit delay across the two asynchronous clock
domains under consideration, and the allowed delay between
the two clock domains which mainly depends on the system
requirement.
Since d1 and d3 can be as long as desired, a single,
slow-speed global scan enable signal GSE can be used. This
significantly simplifies the logic BIST physical
implementation for designs with multiple clock domains.
There may be some structural fault coverage loss between
clock domains if the ordered sequence of capture clocks is
fixed for all capture cycles. The reason is because the ordered
sequence may create sequentially untestable faults which
could be detected when the sequence is reversed.
Shift Window Capture Window Shift Window
C1
TCK1 … …
d1 d2 d3
C2
TCK2 … …
GSE
Fig. 7. Timing control using staggered single-capture.
A-2. Aligned Double-Capture
The inability of staggered single-capture to detect
intra-clock-domain delay faults as well as simultaneous
double-capture to detect inter-clock-domain delay faults
among synchronous clock domains can be resolved by using
the aligned double-capture scheme. One aligned
double-capture approach that aligns all capture edges
together is illustrated in Fig. 8. The approach is referred to as
capture aligned double-capture. The major advantage of
using this approach is that all intra-clock-domain and
inter-clock-domain faults for synchronous clock domains
can be tested. The arrows shown in Fig. 8 indicate the delay
faults that can be detected. For example, the three arrows
from TCK1 to C are used to test all intra-clock-domain delay
faults in the clock domain controlled by TCK1, and all
inter-clock-domain delay faults from TCK1 to TCK2 and
TCK3. The remaining six arrows shown from TCK2 to C, and
TCK3 to C are used to test the remaining delay faults.
C1 C
C2
C3
TCK1
TCK2
TCK3
GSE
Fig. 8. Capture aligned double-capture.
Since the active edges (rising edges) of the three capture
pulses (see vertical dashed line C) must be aligned precisely,
the circuit must contain one reference clock, and the
frequency of all remaining test clocks must be derived from
the reference clock. In the example given here, TCK1 is the
reference clock operating at the highest frequency, and TCK2
and TCK3 are derived from TCK1 and designed to operate at
1/2 and 1/4 the frequency of TCK1, respectively. Therefore,
this approach is only applicable for at-speed testing of
intra-clock-domain and inter-clock-domain delay faults in
synchronous clock domains.
A similar aligned double-capture approach is shown in
Fig. 9 that aligns all first capture edges rather than second
capture edges. This approach is referred to as launch
aligned double-capture. Similar to capture aligned
double-capture, it is also only applicable for at-speed testing
of intra-clock-domain and inter-clock-domain delay faults in
synchronous domains.
4885 – P. 7 To Appear in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Consider the three clock domains, driven by TCK1, TCK2,
and TCK3, again. The eight arrows among the dashed line C
and the three capture pulses, C1, C2, and C3, indicate that the
intra-clock-domain and inter-clock-domain delay faults that
can be tested. Unlike Fig. 8, however, in order to detect the
inter-clock-domain delay faults from TCK1 to TCK3, a
special shift pulse C4 is required. As this method requires a
much more complex timing-control scheme, a clock
suppression circuit similar to that proposed in [38] needs to
be used to enable or disable the selected capture pulses. The
dotted clock pulses shown in the figure indicate the
suppressed capture pulses.
The main advantages of both aligned double-capture
approaches are that (1) all intra-clock-domain faults and
inter-clock-domain faults can be detected and (2) a single,
slow-speed global scan enable signal GSE is used. Hence,
both approaches can be used for true at-speed testing of
synchronous clock domains. However, one major drawback
is that precise alignment of the capture pulses is still
required.
C
Capture Window
C1 C4
TCK1
C2
TCK2
C3
TCK3
GSE
Fig. 9. Launch aligned double-capture.
A-3. Staggered Double-Capture
The staggered double-capture scheme solves the capture
alignment problem in the aligned double-capture approach.
An example at-speed timing control diagram is shown in Fig.
10. In the capture window, two capture pulses are generated
for each clock domain. The first two capture pulses (C1 and
C3) are used to create transitions at the outputs of scan cells,
and the output responses to the transitions are captured by
the second two capture pulses (C2 and C4), respectively.
Both delays d2 and d4 are set to their respective domains’
operating frequencies. Since d1, d3, and d5 can be adjusted to
any length, we can simply use a single, slow-speed global
scan enable signal GSE for driving all clock domains. Hence,
this approach can provide at-speed testing of
intra-clock-domain delay faults within each clock domain.
Similar to staggered single-capture, for both synchronous
and asynchronous clock domains, adjusting d3 will enable
detection of inter-clock-domain delay faults and
inter-clock-domain structural faults. Since a single GSE
signal is used, this scheme significantly eases physical
implementation and allows designers to integrate logic BIST
with scan/ATPG easily in order to improve the circuit’s
manufacturing fault coverage.
Shift Window Capture Window Shift Window
C1 C2
TCK1 … …
d1 d2 d3 d4 d5
C3 C4
TCK2 … …
GSE
Fig. 10. Timing control using staggered double-capture.
B. Fault Detection Capability
Modern VLSI designs often contain synchronous and
asynchronous clock domains. To maximize BIST (structural
and delay) fault coverage, this section discusses the fault
detection capability associated with each timing control
diagram.
B-1. Intra-Clock-Domain Fault Detection
Intra-clock-domain fault detection is relatively easy by
using an ordered sequence of capture clocks for all clock
domains in each capture window. For each clock domain, a
single clock pulse is used to detect structural faults in
low-speed testing, while two at-speed clock pulses are used
to detect timing-related faults in at-speed testing. It is
preferable to use the double-capture scheme as it detects not
only structural faults but also timing-related faults.
B-2. Inter-Clock-Domain Fault Detection
Inter-clock-domain fault detection is more complex,
especially for timing-related delay faults. Figure 10 shows
four timing waveforms for detecting inter-clock-domain
faults from the clock domain driven by TCK1 to the clock
domain driven by TCK2.
If structural faults are to be detected, then delay d can be
adjusted to be larger than the clock-skew between the two
clock domains. This adjustment is easy. On the other hand, if
timing-related delay faults also need to be detected, then
delay d should be further adjusted to satisfy the specified
timing relation between the two clock domains. Generally,
the waveform of Fig. 11d can achieve higher
inter-clock-domain delay fault coverage since a pattern of
higher randomness is applied and fault effects can be
captured immediately.
We conducted an experiment using the logic BIST
product TurboBIST-Logic [39] developed by SynTest
Technologies to compare the transition delay fault detection
capabilities of the waveforms shown in Fig. 11. The circuit
consisted of 11K primitives (instances) and had three clock
domains driven by cclk, mclk, and pclk, respectively. For the
sake of clarity, we disabled cclk and only explored the fault
detection capabilities for the transition delay faults across
the clock-domain logic block between the clock domain
driven by mclk and the one driven by pclk. As shown in
Table I, the waveform shown in Fig. 11d can achieve the
highest inter-clock-domain transition fault coverage. If cclk
is enabled, one would expect the resulting transition fault
coverage to be much higher than that reported in Table I.
4885 – P. 8 To Appear in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

(1) One-hot double-capture can yield the highest fault

Shift Window Capture Window Shift Window coverage for intra-clock-domain delay faults, but cannot
C1 C2 detect inter-clock-domain delay faults.
TCK1 … … (2) Simultaneous double-capture can only detect
d
C3 C4 intra-clock- domain structural and delay faults, but
TCK2 … … cannot detect any inter-clock-domain structural or delay
GSE faults.
(a) Two capture pulses followed by two capture pulses (3) Staggered single-capture can yield the highest fault
(staggered double-capture) coverage for detecting intra-clock-domain structural
faults in both synchronous and asynchronous clock
Shift Window Capture Window Shift Window
C1 C2
domains, but cannot detect any intra-clock-domain
TCK1 … … delay faults.
d (4) Aligned double-capture can yield the highest fault
C3
… … coverage for detecting all intra-clock-domain and
TCK2
inter-clock- domain delay faults in synchronous clock
GSE
domains, but is not applicable for testing asynchronous
clock domains; hence, it is best suited for testing
(b) Two capture pulses followed by one capture pulse
synchronous clock domains.
Shift Window Capture Window Shift Window (5) Staggered double-capture can also detect inter-clock-
C1 domain structural and delay faults that aligned double-
TCK1 … … capture cannot detect; hence, it is best suited for testing
d
C2 C3 asynchronous clock domains.
TCK2 … …
GSE The summary further indicates that it is preferred to use a
hybrid clocking scheme that includes aligned double-capture
(c) One capture pulse followed by two capture pulses for testing synchronous clock domains and staggered
double-capture for testing asynchronous clock domains.
Shift Window Capture Window Shift Window
C1 Alternatively, one may consider testing all synchronous and
TCK1 … … asynchronous clock domains in multiple test sessions using a
d hybrid scheme that includes simultaneous double-capture
C2
… … and staggered single-capture. The drawbacks are the
TCK2
GSE
complexity of the BIST controller for providing multiple test
sessions and the need to add isolation logic across all
(d) One capture pulse followed by one capture pulse interacting clock domains.
(staggered single-capture) TABLE II
INTRA-CLOCK-DOMAIN FAULT DETECTION CAPABILITY
Fig. 11. Inter-clock-domain delay fault test timing.
(S: STRUCTURAL FAULTS DETECTED; D: DELAY FAULTS
TABLE I DETECTED)
INTER-CLOCK-DOMAIN DELAY FAULT DETECTION Timing Control Scheme Synchronous Asynchronous
CAPABILITY Intra-domain Intra-domain
One-hot double-capture (S, D) (S, D)
Test Timing Fault Coverage Simultaneous double-capture (S, D) (S, D)
Fig. 11a 61.11% Staggered single-capture (S) (S)
Aligned double-capture (S, D) −
Fig. 11b 61.11% Staggered double-capture (S, D) (S, D)
Fig. 11c 84.92%
TABLE III
Fig. 11d 87.70% INTER-CLOCK-DOMAIN FAULT DETECTION CAPABILITY
B-3. Fault Detection Summary (S: STRUCTURAL FAULTS DETECTED; D: DELAY FAULTS
DETECTED)
Tables II and III show the type of intra-clock-domain and
inter-clock-domain faults in synchronous and asynchronous Synchronous Asynchronous
clock domains that can be detected by the above-mentioned Inter-domain Inter-domain
timing control schemes described in Sections II and IV. One-hot double-capture (S) (S)
Each scheme has its advantages and disadvantages. For Simultaneous double-capture − −
Staggered single-capture (S, D) (S, D)
example:
Aligned double-capture (S, D) −
Staggered double-capture (S, D) (S, D)
4885 – P. 9 To Appear in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
C. Capture Clock Generation
In order to generate an ordered sequence of
double-capture clocks, one can use clock suppression,
daisy-chain clock-triggering, or token-ring clock-enabling.
Generally, the clock suppression technique as proposed in
[38] is more suitable for testing synchronous clock domains,
whereas the daisy-chain clock-triggering technique or the
token-ring clock-enabling technique as proposed in
[23]-[25] is more suitable for testing asynchronous clock
domains. Other design flavors of on-chip clock controllers
can also be found in [40] and [41].
The clock suppression scheme typically requires using a
reference clock operating at the highest frequency. Figure 12
shows an example launch aligned double-capture for two
interacting clocks. Figure 13 shows a clock suppression
circuit for generating the launch aligned double-capture
waveform given in Fig. 12. This circuit uses a reference
clock (CK1) to program the capture window. The contents of
the 8-bit shift register are preset to {0011, 1111} during each
shift window. Due to its programmability, the approach can
also be used to generate timing waveforms for testing
asynchronous designs. One major requirement is that
depending on needs, the delay measured by the number of
reference clock pulses be equal to or longer than delay d
between C2 and C3 as shown in Fig. 11a. A novel clock
gating circuit for generating staggered single-capture clocks
for inter-clock-domain at-speed testing of synchronous
clock domains can also be found in [42].
Shift Window Capture Window Shift Window
C1 C2
TCK1 … …
C3 C4
… …
TCK2
GSE
Fig. 12. An example launch aligned double-capture
clocking.
‘0’
0 0 1 1
CK1
CK1
BIST GSE ‘0’ 1 1 1 1
GSE CK1
mode Generator
CK2
Fig. 13. A clock suppression circuit for generating the
waveform given in Fig. 12.
The daisy-chain clock-triggering technique means that the
completion of the shift-in operation triggers the GSE signal
to become 0, switching operation mode from shift to capture.
This in turn triggers the generation of two at-speed clock
pulses for the first clock domain, the rising edge of the
second capture clock pulse triggers the generation of two
at-speed clock pulses for the second clock domain, and so
on. Finally, the rising edge of second capture clock pulse for
the last clock domain triggers the GSE signal to become 1,
switching operation mode from capture to shift. A timing
waveform is shown in Fig. 14 where the delay d is properly
adjusted depending on whether inter-clock-domain
structural or delay faults are to be detected or not.
GSE
TCK1
TCK2
d
Fig. 14. Daisy-chain clock-triggering.
The token-ring clock-enabling technique is very similar to
the daisy-chain clock-triggering technique. The only
difference between them is that the former uses a clock edge
to trigger the next event, while the latter uses a signal level to
enable the next event. Figure 15 shows a daisy-chain
clock-triggering circuit for generating the staggered
double-capture waveform given in Fig. 14. When the BIST
mode is activated, the SE1/SE2 generators and 2-pulse
controllers will generate the required scan enable and
double-capture clock pulses per the arrows shown in Fig. 14.
Each SE1/SE2 can be treated as a GSE signal for CD1/CD2.
SE1
BIST SE1 2-Pulse TCK1
mode Generator Controller
CK1
CK1
SE2
SE2 2-Pulse
TCK2
Generator Controller
CK2
CK2
Fig. 15. A daisy-chain clock-triggering circuit for
generating the waveform given in Fig. 14.
V. PHYSICAL IMPLEMENTATION ISSUES
A major difference between ATE-based scan test and
logic BIST is that the latter requires a more complex self-test
circuitry be implemented together with the functional
TCK1 circuitry. Successfully conducting the physical
implementation of the functional circuitry for a high-speed
and high-performance design is in itself a big challenge. If
TCK2 the self-test circuitry adds a large number of critical signals
and requires strict clock-skew management, the physical
implementation of logic BIST can become prohibitively
difficult.
The proposed logic BIST scheme employs several
techniques to ease physical implementation. Of the most
significance, a slow-speed global scan enable signal GSE is
used to greatly reduce the clock-skew management
complexity and a PRPG-MISR pair is used for each clock
domain to avoid layout routing congestion. One more
technique using re-timing logic to control clock skew among
each group of PRPG, scan chain, and MISR is illustrated in
Fig. 16 is illustrated in Fig. 16.
4885 – P. 10 To Appear in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Shift
PRPG1 PS1/SpE1 Scan Chain A SpC1
CCK1 TCK1 C Capture CCK1
PRPG2 PS2/SpE2 Scan Chain B SpC2
CCK2 TCK
Fig. 16. Controlled clock 2skew management.
For the sake of clarity, Fig. 16 shows only two scan chains,
one each in two different clock domains. During shifting, the
PRPG-MISR pair and its associated scan chain are
reconfigured as one shift register. Since the PRPG and the
MISR are mostly placed far from the scan chain, timing
violations may occur between the PRPG and the scan chain
inputs as well as between the scan chain outputs and the
MISR.
To facilitate physical design, we propose a technique that
always makes the CCK clock that drives the PRPG and the
MISR arrive earlier than the TCK shift clock that drives the
scan chain. With this approach, only hold-time violations
may occur from the PRPG to the scan chain inputs, while
only setup-time violations may occur from the scan chain
outputs to the MISR. In this case, the hold-time violations
can be corrected with re-timing D flip-flops, whereas the
setup-time violations can be avoided by reducing logic
levels from the scan chain outputs to the MISR or be
corrected with re-timing D flip-flops. The re-timing logic
should consist of at least one negative-edge pipelining
register (D flip-flop) and one positive-edge pipelining
register (D flip-flop).
Figure 16 illustrates an example re-timing logic among the
PRPG, a scan chain, and the MISR, using two pipelining
registers on each end. Note that the two clocks, CCK and
TCK, could belong to one clock tree with a small phase shift;
the space expander and space compactor as shown in Fig. 16
can then be ignored. By making the clock-skew problem
under control in this way, we can significantly simplify
physical implementation.
Most importantly, the proposed logic BIST scheme does
not add any isolation logic along the paths from scan chain B
to scan chain A through the combinational logic block C.
This greatly reduces design complexity and avoids potential
performance degradation.
P D Q D Q D Q D Q
R I
P Scan Chain
CK CK CK
G R
CCK
TCK
Fig. 17. Re-timing logic among the PRPG, a scan chain,
and the MISR.
VI. EXPERIMENTAL RESULTS
The logic BIST architecture proposed in this paper has
been successfully implemented in many industrial designs
MISR1
[23], [26], [42]. The TurboBIST-Logic tool [39] developed
by SynTest Technologies was used for logic BIST
implementation. The tool allows for designing a logic BIST
MISR2 system at the register-transfer level (RTL) or gate level
based on:
CCK2
• The type of logic BIST architecture to adopt.
• The number of PRPG-MISR pairs to use.
• The length of each PRPG-MISR (or PEPG-MISR) pair.
• The stuck-at and transition faults to be detected and
BIST timing control diagrams to be used for detecting
these faults in synchronous clock domains and
asynchronous clock domains.
• The types of optional logic to be added in the BIST
system to ease physical implementation, facilitate debug
and diagnosis, as well as improve the circuit’s fault
coverage.
The tool consists of three major steps in designing the
logic BIST system once all decisions regarding the logic
BIST architecture are made. They are described below.
A. BIST Rule Checking and Violation Repair
The first step is to perform logic BIST design rule
checking on the RTL or gate-level design. All DFT rule
violations of the scan design rules and BIST-specific design
rules as given in [39] must be repaired. Once all DFT rule
violations are repaired, the design which is referred to as a
BIST-ready core is considered to have followed all scan and
logic BIST design rules.
B. RTL BIST Synthesis
Then, the tool automatically creates the RTL logic BIST
controller. The capture-clocking schemes supported in the
BIST controller includes capture aligned double-capture for
synchronous clock domains and staggered double-capture
for asynchronous clock domains. The number of scan chains
for each clock domain is specified along with the names of
their associated scan inputs (SIs) and scan outputs (SOs)
without inserting the actual scan chains into the circuit. The
scan synthesis task can be handled as part of the general
synthesis task, implemented using any (commercially
available) synthesis tool for converting the RTL BIST-ready
core and the logic BIST system into a gate-level netlist.
M
C. Design Verification and Fault Coverage
S Enhancement
CK
Finally, Verilog testbenches are generated and the
synthesized netlist is verified with functional and/or timing
CCK
verification to ensure that the logic BIST system functions as
intended. Fault simulation is then performed on the
pseudorandom patterns generated by the PRPGs to
determine the circuit’s fault coverage. If the circuit does not
reach the target fault coverage goal, additional test points
(including control points and/or observation points) can be
4885 – P. 11 To Appear in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

selected and inserted in the BIST-ready core, or top-up results indicate that it is possible to achieve more than 93%
ATPG patterns (including compressed ATPG patterns when BIST intra-clock-domain transition fault coverage (in all
available) can be used during manufacturing test, to increase synchronous and asynchronous clock domains) when 1000
the circuit’s fault coverage. The tool allows adding extra test observation points were inserted into the design. Because
points in advance at the RTL design with the hope to achieve each core has already implemented scan chains, we can only
the target fault coverage goal. Otherwise, the test point obtain the BIST area overhead that includes the
insertion can be inserted at the gate-level and the fault PRPG/MISR pairs, the BIST controller, and additional
simulation process is repeated until the final fault coverage circuits to insert the space expanders and observation points,
goal is reached. An example fault simulation and test point block all unknown (X) signals potentially propagated to the
insertion flow is illustrated in Fig. 18. MISRs, and mask off all multi-cycle paths and false paths.
In addition, we implemented logic BIST on two large
Test Point Selection at RTL Design industrial designs, ranging from 15 to 20 million primitives.
Table V shows the experimental results. Again, we
implemented the staggered double-capture architecture in all
Logic/Scan Synthesis
clock domains of each design to reduce physical
implementation efforts. We calculated both BIST transition
Fault Simulation fault coverage in all synchronous and asynchronous clock
domains using the intra-clock-domain transition fault model
Gate-Level Test No Coverage and the BIST stuck-at fault coverage using the staggered
Point Insertion Acceptable ? double-capture patterns in each design. Knowing these BIST
Yes coverage numbers allows for top-up (transition and stuck-at)
ATPG patterns to be added at a later stage to increase the
Done
circuit’s fault coverage during manufacturing test. Both
Fig. 18. Fault simulation and test point insertion flow. designs have been successfully taped out and worked the
first time on manufactured chips.
D. Industrial Design Examples
TABLE V
Based on the TurboBIST-Logic tool capabilities, we have EXPERIMENTAL RESULTS FOR INDUSTRIAL DESIGNS
implemented the staggered double-capture architecture in CKT1 CKT2
two commercially popular CPU cores [23] and added # of Primitives 15M 20M
observation points to improve the fault coverage of each # of Flip-Flops 673K 1.61M
core. The circuit statistics and experimental results for the # of Clock Domains 6 9
two IP cores are shown in Table IV. Operating Frequency 266MHz 533MHz
TABLE IV # of PRPG/MISR Pairs 6 9
EXPERIMENTAL RESULTS FOR IP CORES X and Y PRPG Length Range 19-27 19-24
MISR Length Range 19-253 21-220
Core X Core Y
# of BIST Patterns 64,000 64,000
# of Primitives 218,100 633,400
BIST Fault Coverage
# of Flip-Flops 10,300 33,200 – Stuck-At Faults 87.79% 89.38%
# of Clock Domains 2 8 – Transition Faults 86.63% 82.32%
Operating Frequency 250MHz 330MHz
# of PRPG/MISR Pairs 2 8 BIST Area Overhead 2.39% 2.07%
PRPG Length Range 19 19
MISR Length Range 1: 19 / 1: 99 7: 19 / 1: 80 The results show that each design can run at its intended
# of Observation Points 1,000 1,000 operating frequency. For a design containing millions of
# of BIST Patterns 20,000 20,000 gates, the BIST overhead becomes a fraction of the design.
BIST Fault Coverage Once again, because each circuit has already implemented
– Transition Faults 93.82% 93.22% scan chains, the BIST area overhead is computed similar to
BIST Area Overhead 4.40% 3.20% that used in the two CPU cores. However, obtaining better
BIST fault coverage, for example, 95% or higher, is a
During the implementation, we also chose to: (1) construct
challenge without adding additional fault coverage
one PRPG-MISR pair for each clock domain because there
improvement features, such as test point insertion or other
were crossing clock-domain logic between any two clock
techniques discussed in [5]-[6] and [43]-[45]. This is typical
domains, (2) insert scan cells into all PIs and POs so as to
for BIST designs when only pseudorandom patterns and
increase intra-clock-domain transition fault coverage, and
launch-on-capture schemes are used.
(3) skip inserting space compactors between scan chain
Table VI shows the circuit statistics and the combined
outputs and the MISRs in order to avoid setup-time
BIST and ATPG experimental results for another industrial
violations. This is why there were two long MISRs, one with
design that has been in production [42]. The results
99 bits in Core X and the other with 80 bits in Core Y. Such a
demonstrated how the BIST design is coupled with top-up
MISR is generally related to the main and large clock
ATPG to detect 96.9% intra-clock-domain transition faults
domain that contains a larger number of scan chains. The
4885 – P. 12 To Appear in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

in all synchronous and asynchronous clock domains. In this inter-clock-domain transition faults between two
experiment, 64K random patterns using logic BIST and synchronous (or two asynchronous) clock domains.
8,183 deterministic patterns using top-up ATPG were
applied to the design. VII. CONCLUSIONS
To detect inter-clock-domain transition faults in all Delay fault testing based on launch-on-capture is
synchronous clock domains, additional top-up ATPG commonly practiced in industry due to the ease of using a
patterns were also generated and applied using the slow-speed global scan enable signal. When a BIST design
inter-clock at-speed control scheme proposed in [42]. The contains a mix of synchronous and asynchronous clock
results are shown in Table VII. In this case, 6 inter-clock domains, the conventional one-hot or simultaneous
logic blocks, A ~ F, were targeted. For example, A is a logic double-capture scheme cannot detect any
block from a 100MHz clock to a 300MHz clock, and inter-clock-domain delay faults. This makes logic BIST
contains 36,858 transition faults. Table VII shows the even more difficult to achieve high BIST fault coverage
generated ATPG patterns, fault coverage, and CPU time. when pseudorandom patterns are mainly used for testing.
Furthermore, the area overhead in this application was This paper presented new at-speed logic BIST
mainly due to 6 inter-clock enable generators, each architecture using double-capture (a.k.a. launch-on-capture)
containing 20 flip-flops and consuming an area of roughly for testing BIST designs containing multi-frequency
124 equivalent 2-input NAND gates. synchronous and asynchronous clock domains. To facilitate
TABLE VI debug and diagnosis, the BIST architecture also includes
INTRA-DOMAIN FAULT DETECTION FOR BIST DESIGN CKT3 BIST diagnosis logic to help locate BIST failures.
CKT3 It was shown that the aligned double-capture scheme
# of Primitives 11.1M employed in the architecture is most suitable for testing
# of Flip-Flops 404.9K synchronous clock domains to achieve true at-speed test
# of Clock Domains 11 quality, whereas the staggered double-capture scheme
Min. Frequency 66MHz employed is most suitable for testing asynchronous clock
Max. Frequency 533MHz domains. Physical implementation becomes easier due to the
# of Scan Chains 32
use of a slow-speed global scan enable signal and reduced
Maximum Chain Length 13,598
# of BIST Patterns 64,000
timing-critical design requirements. If structural faults are
# of Top-Up ATPG Patterns 8,183 only considered for detection and diagnosis, the BIST
Intra-Domain Fault Coverage architecture built upon the staggered single-capture scheme
– Transition Faults 96.9% can result in highest fault coverage with lowest BIST
overhead. Application results for several industrial designs
TABLE VII
INTER-DOMAIN FAULT DETECTION FOR BIST DESIGN CKT3 have demonstrated the effectiveness of the proposed
architecture. These results further indicated that the
Inter- proposed double-capture schemes can reach high BIST fault
ATPG
Clock From To # of coverage. For designs containing both synchronous and
Logic (MHz) (MHz) Faults # of Fault CPU
Blocks Vec. Cov. (h:m) asynchronous clock domains, a hybrid clocking scheme
A 100 300 36858 232 86.4 4:30 using aligned double-capture and staggered double-capture
B 133 533 8350 32 100 0:15 is proposed; however, challenges still lie ahead with regard
C 133 266 4942 36 100 0:14 to how to increase the BIST transition fault coverage of the
D 533 133 1940 9 100 0:10 design to a much more acceptable level, say 95% or above,
E 266 533 732 9 100 0:10 and how to locate BIST failures more effectively during
F 266 133 64 3 100 0:09 debug and diagnosis from the system level down to the chip
level.
In the case of detecting inter-clock-domain delay faults in
asynchronous clock domains, unfortunately, we have not ACKNOWLEDGMENTS
been able to conduct true experiments because all industrial The authors are grateful to the anonymous referees for
chips taped out as of today have not been designed for such pointing out unclear descriptions of the paper and giving
purpose. However, as discussed earlier, our proposed constructive suggestions. The authors also would like to
staggered single or double capture scheme can deal with thank Dr. B. Cheon and E. Lee of Samsung Electronics in
such cases by carefully adjusting the d value given in Figs. Korea, Tomotaka Odajima of Marubeni Information
10a or 10d. Consequently, delay fault testing of Systems in Japan, and many colleagues of SynTest
inter-clock-domain faults in asynchronous clock domains is Technologies in the US, Korea, China, and Taiwan for
exactly the same as that in synchronous clock domains. providing the experimental results listed in Tables IV to VII.
Table I has demonstrated via an industrial design how This work was supported in part by National Science
various clocking schemes affect the fault coverage of Foundation of USA under grant CCF-0541103.
4885 – P. 13 To Appear in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
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4885 – P. 14 To Appear in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Laung-Terng (L.-T.) Wang (M’87–SM’04–F’08) received his BSEE and
MSEE degrees from National Taiwan University in 1975 and 1977,
respectively, and his MSEE and EE Ph.D. degrees under the Honors
Cooperative Program (HCP) from Stanford University in 1982 and 1987,
respectively.
He has been chairman and chief executive officer (CEO) of SynTest
Technologies, Inc. (Sunnyvale, CA) since January 1990, and a visiting
professor in the Department of Electrical Engineering and the Graduate
Institute of Electronics Engineering at National Taiwan University since
July 2009. Prior to founding SynTest in 1990, he worked in the industry,
including Intel (Santa Clara, CA) from 1980 to 1983 and Daisy Systems
(Mountain View, CA) from 1983 to 1986, and was with the Department of
Electrical Engineering at Stanford University as Research Associate and
Lecturer from 1987 to 1991.
Dr. Wang currently holds 21 U.S. Patents, 15 European Patents, one
Japan Patent, and one China Patent, in the areas of scan synthesis, test
generation, at-speed scan testing, test compression, logic built-in self-test
(BIST), and design for debug-and-diagnosis (DFD). The
design-for-testability (DFT) technologies Dr. Wang has developed have
been successfully implemented in thousands of ASIC designs worldwide.
He has also co-authored and co-edited three internationally used DFT/EDA
textbooks – VLSI Test Principles and Architectures (2006),
System-on-Chip Test Architectures (2007), and Electronic Design
Automation (2009).
A member of Sigma Xi, Dr. Wang received a 2007 Meritorious Service
Award from the IEEE Computer Society and is a co-recipient of the 2008
IEICE Information and Systems Society Excellent Paper Award for an
excellent series of papers that appeared in IEICE Transactions on
Information and Systems during a period of five years. He is a Fellow of the
IEEE and a Golden Core Member of the IEEE Computer Society.
Xiaoqing Wen (S’89–M’93–SM’08) received his B.S. degree in
Computer Science and Technology from Tsinghua University, Beijing,
China, in 1986, his M.S. degree in Information Engineering from
Hiroshima University, Hiroshima, Japan, in 1990, and his Ph.D. degree in
Applied Physics from Osaka University, Osaka, Japan, in 1993.
From 1993 to 1997, he was a Lecturer at Akita University. He was a
Visiting Researcher at University of Wisconsin - Madison from October
1995 to March 1996. He joined SynTest Technologies, Inc. (Sunnyvale,
CA) in 1998 and served as its chief technology officer (CTO) until 2003. In
2004, he joined the Kyushu Institute of Technology, Iizuka, Japan, where
he is currently a Professor and Chair of the Department of Creative
Informatics. His research interests include design, test, and diagnosis of
integrated circuits.
Prof. Wen currently holds 15 U.S. Patents, 2 Japan Patents, and 22
pending U.S. and Japan Patents in logic built-in self-test (BIST), test
compression, and low-capture-power (LCP) test generation. He has also
co-authored and co-edited two textbooks – VLSI Test Principles and
Architectures (2006) and Power-Aware Testing and Test Strategies for
Low Power Devices (2009). He received the 2008 IEICE Information and
Systems Society Excellent Paper Award for LCP X-filling and test
generation. He is a senior member of the IEEE, a member of the IEICE, and
a member of the REAJ.
Shianling Wu (A’88–M’09) has an M.S. in Computer Science from
Columbia University. She joined SynTest Technologies, Inc. (Princeton
Junction, NJ) in 2003 and is presently Vice President of Engineering
focusing on advanced VLSI DFT research and development. Prior to
SynTest, she was with Bell Laboratories for over 23 years. She currently
holds 5 U.S. Patents and has 3 pending U.S. Patents. She has published over
15 DFT papers and contributed chapters to two DFT textbooks – VLSI Test
Principles and Architectures (2006) and Electronic Design Automation
(2009).
She has served as a program committee member for IEEE International
Test Conference, Asian Test Symposium, and North Atlantic Test
Workshop. She won numerous AT&T and Lucent Awards and received a
Best Panel Award in the 2005 IEEE International Test Conference. She was
a member of SEMATECH, SRC, GSRC, STARC-International, VSIA, and
the IEEE1500 Standard Committee. She is a member of the IEEE.
Hiroshi Furukawa received his B.S. degree in Electrical Engineering from
Kumamoto University, Japan, in 1992.
He joined NEC Micro Systems (Kumamoto, Japan) in 1992 and is
currently a design manager. He is also a Ph.D. student in the Department of
Creation Informatics at the Graduate School of Computer Science and
Systems Engineering, Kyushu Institute of Technology, Japan. His research
interests include VLSI testing and logic built-in self-test (BIST).
Hao-Jan Chao (M’09) graduated from the Department of Electronic
Engineering at National Taipei University of Technology (formerly,
National Taipei Institute of Technology), Taipei, Taiwan, in 1990. He
further received his B.S. degree in Nautical Technology at National Taiwan
Ocean University, Keelung, Taiwan, in 1995, and his M.S. degree in
Electrical Engineering from National Central University, Taoyuan, Taiwan,
in 1999.
He has been working at SynTest Technologies, Inc., Hsinchu, Taiwan,
since 1999, and is currently an R&D Manger responsible for the logic
built-in self-test (BIST) as well as silicon debug and fault diagnosis product
lines. His research interests include logic BIST, core-based design for
testability (DFT), and design for debug-and-diagnosis (DFD).
Boryau (Jack) Sheu received his BSEE and MSEE degrees from National
Taiwan University and Washington University in St. Louis in 1984 and
1991, respectively.
He was Director of Operation and R&D at SynTest Technologies from
January 2001 to April 2009. Prior to SynTest, he held various software
engineering positions in startup companies. He is currently with Sigma
Designs (Milpitas, CA) focusing on DFT flow and implementation. His
research interests include at-speed ATPG, logic BIST, as well as test
strategy and integration for VDSM SOC designs. He is a co-inventor of 6
U.S. Patents related to at-speed scan testing and test compression.
Jianghao Guo received his B.S. and M.S. degrees in Control Science and
Engineering from Shanghai Jiaotong University, Shanghai, China, in 2001
and 2004, respectively. He joined SynTest Technologies, Inc., Shanghai,
China, in 2004, where he served as an engineering manager until 2008.
He is currently a Ph.D. candidate in the Department of Electrical and
Computer Engineering at the University of Cincinnati. His research
interests include VLSI testing, computer architecture, and multi-core
system design.
Wen-Ben Jone (M’84–SM’02) was born in Taipei, Taiwan, Republic of
China. He received the B.S. degree in Computer Science in 1979, the M.S.
degree in Computer Engineering in 1981, both from National Chiao-Tung
University, Hsinchu, Taiwan, and the Ph.D. degree in Computer
Engineering and Science from Case Western Reserve University,
Cleveland, Ohio, in 1987.
In 1987, he joined the Department of Computer Science at New Mexico
Institute of Mining and Technology, Socorro, New Mexico, where he was
promoted to an associate professor in 1992. From 1993 to 2000, he was a
full professor in the Department of Computer Engineering and Information
Science at National Chung-Cheng University, Chiayi, Taiwan, R.O.C.
Since 2001, he has been an associate professor in the Department of
Electrical and Computer Engineering at the University of Cincinnati, Ohio.
His research interests include VLSI design for testability, built-in self-test,
memory testing, high-performance circuit testing, MEMS testing and
repair, and low-power circuit design and test.
Dr. Jone has been a reviewer in these research areas in various technical
journals and conferences. He also served on the program committee of
various technical conferences. He received the Best Thesis Award from The
Chinese Institute of Electrical Engineering (Republic of China) in 1981. He
is a co-recipient of the 2003 IEEE Donald G. Fink Prize Paper Award. He is
also a co-recipient of the Best Paper Award of the 2008 IEEE International
Symposium on Low-Power Electronics & Design. He is a senior member of
the IEEE and the IEEE Computer Society Test Technology Technical
Committee.