Professional Documents
Culture Documents
Field
Computer Engineering
Programmable
Gate
Arrays
Robert Trausmuth
Wiener Neustadt University of Applied Sciences
Summer 2006
Robert Trausmuth
• email: robert.trausmuth@fhwn.ac.at
• phone: +43.2622.89084.240
• fax: +43.2622.89084.99
Computer Engineering
• http://www.fhwn.ac.at/
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Outline
• Introduction to FPGA
• FPGA history
• basic FPGA structure
Computer Engineering
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Why are they called logic circuits?
FPGA
„Programmable Hardware“
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A brief history in time
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Why programmable logic?
total A
costs B
A FPGA
NRE B ASIC
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Why programmable logic?
• PLDs
– AND/OR matrix
– Additional inverters and registers (flip flops)
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Programmable logic arrays (PLAs)
a b c
Predefined link
Programmable link
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N/A
Programmable
&
OR array
N/A
&
N/A
&
l
a !a b !b c !c
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Programmable Logic
Programmable logic
Predominantly
Technology Symbol
associated with ...
Fusible-link SPLDs
Antifuse FPGAs
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Metal
Oxide
Metal
Substrate
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Complex Programmable Logic Devices
• CPLDs
– Combination of a few PLAs and programmable
interconnection lines
– Good for fast logic implementation
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• FPGAs
– Fine grained logic blocks
– Special I/O blocks
– Programmable switching matrix and lots of
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connection lines
Programmable
interconnect
Programmable
logic blocks
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Example: Spartan II architecture
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Switch matrix detail
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16-bit SR
16x1 RAM
a 4-input
LUT
b
• multiplexer
y
c
mux
d flip-flop
q
• 1 bit register
e
clock
clock enable
set/reset
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Control Logic Block
Slice Slice
CLB CLB Logic cell Logic cell
CLB detail
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IOB detail
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FPGA design flow
• Design Entry:
– Create your design files using:
• schematic editor or
• hardware description language (Verilog, VHDL)
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• Design verification:
– Use high language executable functional model (C/C++)
– Use Simulator to check VHDL function
– other software determines max clock frequency
– Load onto FPGA device (cable connects PC to
development board)
• check operation at full speed in real environment.
• History
– 1980: US Department of Defense starts Very High
Speed Integrated Circuit program (VHSIC)
– 1987: Institute of Electrical and Electronics Engineers
ratifies IEEE Standard 1076 (VHDL’87)
– 1993: VHDL language was revised and updated
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Terminology
• Behavioral modeling
– Describes the functionality of a
component/system
– For the purpose of simulation and synthesis
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• Structural modeling
– A component is described by the
interconnection of lower level
components/primitives
– For the purpose of synthesis and simulation
VHDL concepts
• Hierarchy
– Self-contained components
• Abstraction
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– Behavioral description
– Structural description
– Data flow description
• Code Reuse
– libraries
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VHDL entity
A B
entity COMPARE is
port (
A, B: in std_logic; =
C: out std_logic
);
C
end COMPARE;
VHDL architecture
• Structural
• Dataflow
A X
• Behavioral Z X Z C
XOR2 INV
B Y
I
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VHDL architecture – structural description
architecture ARCH_STRUCT of COMPARE is
signal I: std_logic;
end component;
begin
U0: XOR2 port map (X => A, Y => B, Z => I);
U1: INV port map (X => I, Z => C);
end ARCH_STRUCT;
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VHDL architecture – dataflow description
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FPGA design flow
• Design entry
– VHDL text Design Entry
– Schematic tool
Simulation
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structures: Simulation
• Look-up tables (LUT)
• Registers Synthesis
• RAM/ROM
• DSP blocks
• Other device specific Place & Route
components/features
• Logic optimization Simulation
– Implementation analysis
(technology view)
Program device & test
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FPGA design flow
• FPGA fitter
– Tools supplied by the FPGA vendor
– Specific for each FPGA device Design Entry
architecture
Simulation
• Functions
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– Place-and-route
Synthesis
– Constraints editor
– Backannotated netlist for timing Place & Route
simulation
– Configuration bitstream
Simulation
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XILINX FPGA technology
XC2000-XC3000 XC4000, Virtex® Virtex-II Virtex-II Pro™
System Platform
Platform
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• Block RAM
• FPGA Fabric • SelectIO
• Block RAM • XCITE
Glue Logic Technology
• SelectIO
• DCM
• XCITE
Technology • Embedded
Multipliers
• DCM
• PowerPC
• Embedded
• FPGA Fabric Multipliers • RocketIO
• FPGA Fabric • Block RAM
Platform FPGAs
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XILINX FPGA technology
• Spartan II e
I/O Connectivity Logic & Routing
SelectIOTM Technology Flexible logic implementation
DLL IOB IOB DLL
Support major Vector Based Routing
I R CLB ... CLB R I Internal 3-State bussing
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I/O standards
O A A O
B M M B
...
...
I R R I System Clock
Memory Resources O A
... A O
SRL16 registers B M CLB CLB M B Management
Distributed Memory Digital Delay Lock
DLL IOB IOB DLL
Block Memory Loops (DLLs)
External Memory
configurable
IO pins CLBs
fast
hardware
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serial
multipliers
links
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XILINX FPGA technology – Virtex 4
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– Can connect to
multiple cores
– Each decodes
other instructions
– Fast simplex link
(FSL) connections
are easy to do
– But slower than
direct FCB conn
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XILINX FPGA technology - Virtex 4
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• Ethernet MAC
• Supports 10 Mb, 100 Mb
and 1 Gb data per sec
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XILINX FPGA technology
DSOCM
BRAM GPIO
DSPLB
ISPLB
OPB2PLB Ethernet
INTC
PLB2OPB LCD
PPC405
DCR
BRAM
ISOCM
DCR Bus
Data- 32 bits INTC
Address- 10 bits
BRAM
ISOCM Bus
PLB OPB
Data- 64 bits
ARB ARB
Address- 32 bits
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going parallel
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parallel vs serial
37.5 % reduction
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Example: digital filter processing
x
B
D Speed =
F
H
sel Area =
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clock
1 mul, 1 add, 4 T
A
x
B
C
+
x Speed =
D
E
+ Y
x Area =
F
G
+ 2:1
muxes
A
x E
H x Register
B
F
+ D Q Y
+
C
2 mul, 2 add, 2 T
G
x Speed =
D
4 mul, 3 add, 1 T
Area =
sel
clock
Partially reconfigurability
Waveform D
Waveform C
Waveform B
Reconfig
via ICAP
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System-on-chip design
– generic
– operating system
C to HDL tools
• Create C code
• Profile code
• Identify critical code segments
• Translate to VHDL
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hardware/software codesign flow
download.bit
Hardware
hardware/software co-design
• Recent projects
– Wavetable synthesizer
– VHDL code generator + framework
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Wavetable Synthesizer
• Why SOC ?
– Inherent parallelism of multiple voices and filters can be
implemented in logic
– Filter coefficient calculations and modulation parameters
can be done by microcontroller
– Communication to logic will be done via memory
mapped registers and interrupts
Wavetable Synthesizer
slow control
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MIDI, RS232
param calculation
pitch calculation
osc. setup
registers
mapped
Memory
AMP
Register sync
interrupt
FPGA
24 bit
Sync
16 voices à stereo DAC
serial
4 oscillators + 1 filter @ 96 kHz
stereo output
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Wavetable oscillator
mip2
speed
freq
OPB IPIF
OPB - PLB
UART
User Logic Adapter
Effect Synthesizer
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RAM
512 MB RS 232
MIDI
Parameters Parameters
PPC 405
@ 300 MHz
Voice 2 Filterframe
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Wavetable synthesizer pipelined
• One oscillator needs 21 cycles
– 11 cycles for register access
– 13 cycles for wavetable memory access
• One voice needs 66 cycles
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Wavetable Synthesizer sound demos
• Voice sample
• Strings sample
FAUST2HDL compiler
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FAUST2HDL compiler
+ b0 +
I(z) O (z)
1/z
+ -a1 b1 +
1/z
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-a2 b2
import("music.lib");
FAUST2HDL compiler
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FAUST2HDL compiler
FAUST2HDL framework
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FAUST2VHDL code generator
IB M C oreC onnect O nC hip P eripheral B us
O P B IP IF ETH
O PB - PLB UART
M AC
F A U S T _F W
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R S 232
P P C 405 P aram s
@ 300 M H z 100 M bit
E thernet
F A U S T IP A C 97
“process“ C ontrol S tereo A udio
O nC hip
RAM 48 kH z
P rogram &
D ata
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