DES/EDA609 :

Principles of ASIC Design

Jayaraj Narayana
Oct 3rd 2010
 Last Class
• Course Information
• History : Transistors, ICs, Moore’s Law, etc.
• ASICs : Introduction and Types
– Full-custom, semi-custom ICs
– Standard-cell, Gate-array
– Programmable ASICs
• Design Methodology / Flow : ASIC
• FPGAs : Introduction
• ASICs vs FPGAs : A comparison
 Agenda
• ASIC Cell Libraries
• CMOS Logic :Logic Levels, Design Rules
• Layout, Stick diagrams
• Sequential & Data Path Logic Cells
• Residue Number Systems
• I/O Cells
 ASIC Cell Libraries
• Cell Library is key part of ASIC design
• Options: Design kit , ASIC vendor, third party library
• ASIC vendor Library
– Phantom library ( empty boxes)
– ASIC vendor fills empty boxes after layout hand off
• Buy or build library : A Decision
– Target for a qualified cell library ( can buy )
• Develop a cell library in house
– Views : Physical layout, models ( behavioral / timing/ wire-load/routing), Circuit
schematic, test strategy, cell icon.
– Characterization : Simulation of each cell with extracted parasitics to determine
switching delays
CMOS Logic, Layout, Design Rules
3D Perspective of nMOS Transistor

Polysilicon Aluminum
 Complementary CMOS
• Complementary CMOS logic gates
– nMOS pull-down network pMOS
pull-up
network
– pMOS pull-up network inputs
output
– a.k.a. static CMOS
nMOS
pull-down
network

Pull-up OFF Pull-up ON

Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)
 Signal Strength
• nMOS pass strong 0
– But degraded or weak 1
• pMOS pass strong 1
– But degraded or weak 0
• Thus NMOS are best for pull-down network
• Thus PMOS are best for pull-up network
 Conduction Complement
• Complementary CMOS gates always produce 0 or 1
• Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
– Requires parallel pMOS
Y
A
• Rule of Conduction Complements
– Pull-up network is complement of pull-down B
– Parallel -> series, series -> parallel
 CMOS Gate Design
• A 4-input CMOS NOR gate

A
B
C
D
Y
 Example: O3AI
• Y = ( A + B + C) • D
 Example: O3AI
Y = ( A + B + C) • D

A
B
C D
Y
D
A B C
 Layout of Inverter : Detailed Steps
Vp

x x

Gnd
 Inverter Cross-section
• Typically use p-type substrate for nMOS transistors
• Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

 Layer Types
• p-substrate
• n-well
• n+
• p+
• Gate oxide
• Gate (polysilicon)
• Field Oxide
– Insulated glass
– Provide electrical isolation
 CMOS Process Layers
Layer Color Representation

Well (p,n) Yellow

Active Area (n+,p+) Green
Select (p+,n+) Green
Polysilicon Red
Metal1 Blue
Metal2 Magenta
Contact To Poly Black
Contact To Diffusion Black
Via Black
 Gate Layout
• Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
• Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts
 Layout
• Chips are specified with set of masks
• Minimum dimensions of masks determine transistor size (and hence
speed, cost, and power)
• Feature size f = distance between source and drain
– Set by minimum width of polysilicon
• Feature size improves 30% every 3 years or so
• Normalize for feature size when describing design rules
• Express rules in terms of l = f/2
– E.g. l = 0.3 mm in 0.6 mm process
 Inverter Layout
• Transistor dimensions specified as Width / Length
– Minimum size is 4l / 2l, sometimes called 1 unit
– In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long
Example: Inverter
 Example: NAND3
• Horizontal N-diffusion and p-diffusion strips
• Vertical polysilicon gates
• Metal1 VDD rail at top
• Metal1 GND rail at bottom
• 32 λ by 40 λ
NAND3 (using Electric), contd.
 Stick Diagrams
• Cartoon of a layout.
• Shows all components.
• Does not show exact placement, transistor sizes,
wire lengths, wire widths, boundaries, or any
other form of compliance with layout or design rules.
• Useful for interconnect visualization, preliminary layout
layout compaction, power/ground routing, etc.
 Stick Diagrams
• Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
 Stick Diagrams
• Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers

VDD

Vin
Vout

GND
 Stick Diagrams

Metal

poly

ndiff

pdiff
Can also draw
in shades of
gray/line style.
Stick Diagram - Example I
A
OUT

NOR Gate
 Stick Diagrams
• Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
 Sticks Diagram
V DD 3

In Out
• Dimensionless layout entities
• Only topology is important
• Final layout generated by
1 “compaction” program

GND

Stick diagram of inverter

 Activity 2
• Sketch a stick diagram for a 4-input NOR
gate
 Activity 2
• Sketch a stick diagram for a 4-input NOR gate

VDD
A B C D

GND
Design Rules
 Design Rules
• Interface between designer and process engineer
• Guidelines for constructing process masks
• Unit dimension: Minimum line width
– scalable design rules: lambda parameter
– absolute dimensions (micron rules)
 Wiring Tracks
• A wiring track is the space required for a wire
– 4 l width, 4 l spacing from neighbor = 8 l pitch
• Transistors also consume one wiring track
 Well spacing
• Wells must surround transistors by 6 l
– Implies 12 l between opposite transistor flavors
– Leaves room for one wire track
 Area Estimation
• Estimate area by counting wiring tracks
– Multiply by 8 to express in l
 Example: O3AI
Y = ( A + B + C) • D

• Sketch a stick diagram for O3AI and estimate area

–
 Example: O3AI
• Sketch a stick diagram for O3AI and estimate area

Y = ( A + B + C) • D
 Example: O3AI
Sketch a stick diagram for O3AI and estimate area

Y = ( A + B + C) • D
 Simplified Design Rules
• Conservative rules to get you started
 S
Intra-Layer
a m e
Design Rules
P o Dt e in f t f i e a r l e n t P o t e n t i a l
9 2
0
W e l l o r P o l y s i l i c o n
6
1 0 2
3 3
A c t i v e M e t a l 1
C o n t a c t
o r V i a 2
3 H o l e 3
2 2 4
S e l e c t Metal2

3
 Sequential Logic Cells
• Latch
• Flip-Flop
• Clocked Inverter
 D Latch Design
• Multiplexer chooses D or old Q
CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK

Old Q
CLK
 D Latch
• When CLK = 1, latch is transparent
– Q follows D (a buffer with a Delay)
• When CLK = 0, the latch is opaque
– Q holds its last value independent of D
• a.k.a. transparent latch or level-sensitive latch

CLK CLK

D
Latch

D Q
Q
 D Latch Operation
Q Q
D Q D Q

CLK = 1 CLK = 0

CLK

Q
 D Flip-flop
• When CLK rises, D is copied to Q
• At all other times, Q holds its value
• a.k.a. positive edge-triggered flip-flop, master-slave flip-flop

CLK
CLK
D
Flop

D Q
Q
 D Flip-flop Design
• Built from master and slave D latches
CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch
Latch

QM
D Q
CLK CLK

A “negative level-sensitive” latch A “positive level-sensitive” latch

 D Flip-flop Operation
Inverted version of D

QM Q
D

CLK = 0

Holds the last value of NOT(D)

QM
D Q

Q -> NOT(NOT(QM))
CLK = 1

CLK

Q
 Race Condition
• Back-to-back flops can
malfunction from clock skew
– Second flip-flop fires Early
– Sees first flip-flop change
and captures its result
– Called hold-time failure or
race condition
 Timing Constraints
R1 R2
In Combinational
D Q D Q
Logic

CLK tCLK1 tCLK2

tc − q tlogic
tc − q, cd t
tsu, thold

Minimum cycle time:

T - δ = tc-q + tsu + tlogic
Worst case is when receiving edge arrives early (positive δ)
 Timing Constraints
R1 R2
In Combinational
D Q D Q
Logic

CLK tCLK1 tCLK2

tc − q tlogic
tc − q, cd t
tsu, thold

Hold time constraint:

t(c-q, cd) + t(logic, cd) > thold + δ
Worst case is when receiving edge arrives late
Race between data and clock
 Nonoverlapping Clocks
• Nonoverlapping clocks can prevent races
– As long as nonoverlap exceeds clock skew
• Good for safe design
– Industry manages skew more carefully instead
φ2 φ1
QM
D Q

φ2 φ2 φ1 φ1

φ2 φ1

φ1

φ2
 Clocked Inverter
• A series combination of an inverter and a transmission
gate
 Datapath Logic Cells
• Adder
– Ripple, Carry Save, Carry Bypass, Carry Skip
– Carry Look ahead Adders ( Brent-Kung)
– Carry Select and Conditional Sum adder
 Adders
• A. Conventional number system.
– Carry-propagate adders / Ripple carry Adders (CPA / RCA)
– Carry-skip adder
– Carry-lookahead adder
– Carry-select adder
– Conditional-sum adder
• B. Redundant number system : limited carry propagation
– Carry-save adder
 Full-Adder
A B

Cin Full Cout

adder

Sum
Full Adder Implementations
 The Binary Adder
A B

Cin Full Cout

adder

Sum

S = A⊕ B ⊕i
C

= A BCi + A BC i + AB Ci + A B Ci
C o = A B + B Ci + A Ci
Express Sum and Carry as a function of P, G, D

Define 3 new variable which ONLY depend on A, B

Generate (G) = AB
Propagate (P) = A ⊕ B
Delete/Kill= A B

Can also derive expressions for S and C o based on D and P

Note that we will be sometimes using an alternate definition for
Propagate (P) = A + B
 The Ripple-Carry Adder
A0 B0 A1 B1 A2 B2 A3 B3

Ci,0 Co,0 Co,1 Co,2

FA FA FA FA
(= Ci,1)

S0 S1 S2 S3

Worst case delay linear with the number of bits

td = O(N)

tadder = (N-1)tcarry + tsum

Goal: Make the fastest possible carry path circuit

 Carry-Bypass Adder
P0 G1 P0 G1 P2 G2 P3 G3 Also called
Carry-Skip
Ci,0 Co,0 Co ,1 Co,2 C o,3
FA FA FA FA

P0 G 1 P0 G1 P2 G2 P3 G3
BP=P oP1 P2 P3
Ci,0 Co ,0 Co,1 Co,2
FA FA FA FA

Multiplexer
C o,3

Idea: If (P0 and P1 and P2 and P3 = 1)

then C o3 = C 0 , else “kill” or “generate”.
Carry Skip Adder
 LookAhead - Basic Idea
A A1, B1 ••• AN-1, BN-1

Ci,0 P0 Ci,1 P1
Ci, N-1 PN-1

S0 S1 ••• SN-1

C o, k = f ( A k, B k C,o, k – 1 = Gk + P k) Co, k –1
 Look-Ahead: Topology

Expanding Lookahead equations: VDD

C o, k = Gk + Pk ( Gk – 1 + Pk – 1 Co, k –2 )
G2

G1
All the way:
G0
C o, k = Gk + Pk ( Gk – 1 + P k – 1 ( … + P1( G0 + P0 Ci, 0 ) ) )
Ci,0
Co,3

P0

P1

P2

P3
 Carry Lookahead Trees

Co, 0 = G0 + P0Ci, 0
C o, 1 = G1 + P1 G0 + P1P0 Ci, 0
C o, 2 = G2 + P2G1 + P2 P1G0 + P2 P1P0C i, 0
= ( G2 + P2G1 + ( P2P)1 ( G0) + P0Ci, 0 = G 2:1 )+ P2:1 C o, 0

Can continue building the tree hierarchically.

Multipliers
 The Binary Multiplication

1 0 1 0 1 0 Multiplicand
x 1 0 1 1 Multiplier
1 0 1 0 1 0
1 0 1 0 1 0

0 0 0 0 0 0 Partial products

+ 1 0 1 0 1 0

1 1 1 0 0 1 1 1 0 Result
Canonical Signed Digit Vector
Note : B = Binary Number, D= CSD vector
Ci+1 is the Carry from the sum of Bi+1 + Bi + Ci ( start with C0=0)
Booth’s Algorithm
Booth’s Algorithm Rules
Booth’s Algorithm – An Example
Radix-4 Modified Booth’s Algorithm
Radix-4 Booth’s Algorithm Rules
Radix-4 Versus Radix-2 Booth’s Algorithm
 Residue Number System: Continued

A residue number system (RNS)

represents a large integer using a set of
smaller integers, so that computation
may be performed more efficiently

We add, subtract or multiply residue

numbers using modules of each bit
position - without any carry.
 Residue Number System: Continued

A residue number system is defined by a set of N

integer constants, {m1, m2, m3, ... , mN }, referred
to as the moduli.
Let M be the least common multiple of all the mi.
Any arbitrary integer X smaller than M can be
represented in the defined residue number system
as a set of N smaller integers {x1, x2, x3, ... , xN}
with xi = X modulo mi
representing the residue class of X to that
modulus.
 Other Datapath Operators

• Subtracter
• Barrel-Shifter
• Leading-one detector
• Priority Encoder
• Accumulator
• Decrementer
• All-zeros / ones detector
• Register File
• FIFO
 Summary
• ASIC Cell Libraries
• CMOS Logic :Logic Levels, Design Rules
• Layout, Stick diagrams
• Sequential & Data Path Logic Cells
• Residue Number Systems
• I/O Cells
 Next Class

• ASIC Library Design:

• Logical Effort,
• Library-Cell Design,
• Gate-Array Design,
• Standard-Cell Design.