IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO.
10, OCTOBER 2009
Three-Level ZVS Active Clamping PWM for the
DC–DC Buck Converter
Jean Paulo Rodrigues, Samir Ahmad Mussa, Member, IEEE, Marcelo Lobo Heldwein, Member, IEEE,
and Arnaldo José Perin, Member, IEEE
Abstract—This paper presents the study of a dc–dc buck
converter with three-level buck clamping (buck–buck), zero-
voltage switching (ZVS), active clamping, and constant-frequency
pulsewidth modulation (PWM). Other ZVS dc–dc converter
topologies that employ three-level switching cells are introduced,
and their steady-state dc gain is analyzed. This analysis shows
that the buck–buck converter has characteristics that warrant a
more detailed study. A feature that is common to all the intro-
duced topologies is the theoretical reduction of the voltage stresses
across the active semiconductors to 50% of the corresponding two-
level converters. Accordingly, the switches of the buck–buck con-
verter provide 50% of the blocking voltage of a ZVS two-level buck
converter. The steady-state analysis of the converter is performed
according to the description of the operation stages of the con-
verter. Based on the performed analyses, a comparative discussion
to other topologies is given. Furthermore, a topologic derivation of
the circuit is presented, which provides ZVS operation to all semi-
conductors. Finally, a simplified design procedure is proposed, and
used to design and build a prototype. Experimental results from a
laboratory prototype are presented.
Index Terms—Buck, dc–dc converter, pulsewidth modulation
(PWM), soft switching, three levels.
I. INTRODUCTION
UCK-TYPE dc–dc converters are widely employed in the
B power electronics industry. Buck converters are perhaps
most widely used dc–dc converters in the world because no other
topology is as simple. Their applications range from low-power
regulators [1] to very high power step-down converters [2],
which are characterized by a low number of components, low
control complexity, and no insulation. In the conventional buck
topology, which uses a single active switch, the maximum volt-
age applied across the terminals of the semiconductors equals
the input voltage, and hard switching is observed. These con-
verters are often used in high-power and high-input-to-output-
voltage-ratio applications; however, the conventional buck-type
topologies have low efficiencies because of high conduction
losses [3] due to high-voltage-rated devices and high switch-
ing losses. Furthermore, for high input voltages, the choice of
Manuscript received December 5, 2008; revised March 23, 2009. Current
version published September 2, 2009. This work was supported in part by the
National Counsel of Technological and Scientific Development (CNPq), Brazil.
Recommended for publication by Associate Editor M. Ferdowsi.
The authors are with the Department of Electrical Engineering, Power
Electronics Institute, Federal University of Santa Catarina, Florianópolis
88.040-970, Brazil (e-mail: jean.p.r@gmail.com; samir@inep.ufsc.br;
heldwein@inep.ufsc.br; arnaldo.perin@inep.ufsc.br).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2009.2022535
0885-8993/$26.00 © 2009 IEEE
2249
Fig. 1. Two-level ZVS PWM buck–buck converter [6].
switches is limited, which leads to difficulty in selecting tran-
sistors or finding low-cost devices.
IN order to overcome the challenges listed before, researchers
have been working to develop multilevel techniques [4], [5] and
soft switching [6]–[17], which are capable of reducing voltage
stresses and switching losses, and thus, enable higher efficien-
cies, smaller dimensions, and lower system costs. In this context,
the main objective of this paper is to propose a solution that si-
multaneously reduces voltages across the switches and provides
soft switching to a buck-type converter.
The main parameters that impose limits on a buck converter
with high-frequency pulsewidth modulation (PWM) operation
are the junction capacitances of the semiconductors, parasitic
inductances, and the reverse recovery of the diodes. To mini-
mize these effects, many soft-switching techniques have been
presented in the literature. Soft-switching techniques typically
increase the current and/or voltage stresses in the semiconduc-
tor devices. Zero-voltage switching (ZVS) techniques [6]–[17]
typically increase the voltage stress of the active switches,
and zero-current switching (ZCS) techniques increase current
stresses [18]. In the case of two-level buck topologies, if a
two-level ZVS converter topology presents a maximum voltage
across the active switches that is higher than twice the input volt-
age, this topology is not preferable. This condition is considered
as the starting point of this paper, where the concept is to be ex-
tended to a three-level version. In [6], a buck converter topology
employing a two-level ZVS buck-type active clamping circuit
(cf., Fig. 1) was introduced. This topology contains an extra
switch compared to the conventional buck converter. However,
this topology allows for ZVS in the turn-off switches, thus pro-
viding a higher efficiency at higher switching frequencies. An
analysis of the two-level ZVS active clamping techniques pro-
posed in [6] shows that the two-level ZVS buck–buck converter
is the only topology that limits the maximum voltage across the
switches to the same level that is obtained in a conventional
buck converter. This is the main reason for choosing three-level
buck-type clamping for further study in this paper.
2250 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 10, OCTOBER 2009

Fig. 2. Buck converter using different three-level converters for active clamping. (a) Buck–buck. (b) Buck–boost. (c) Buck–cuk. (d) Buck–sepic. (e) Buck–zeta.

Three-level buck nonisolated dc–dc PWM converters have

been proposed in the literature [8], [9] in order to reduce the
voltage across the switches. In [19], even though these convert-
ers operate at constant switching frequency, they do not feature
soft switching. In [20], the converter features soft switching.
However, compared to the conventional buck converter, the the-
oretical maximum voltage across the active devices in [20] is
higher than half of the input voltage. Furthermore, in this topol-
ogy, the converter is frequency-modulated, which is not desir-
able in this paper.
Thus, the proposal and analysis of a three-level buck-type
converter with soft switching is presented in the following sec-
tions, where a family of distinct three-level ZVS active clamping Fig. 3. Input-to-output voltage characteristic of the buck–boost converter.
techniques applied to the dc–dc buck converter is presented. The
different clamping strategies are compared, and the selection
of three-level ZVS buck-type clamping for the buck converter the basic topology from which they are generated, and which
is justified. The advantage of employing the three-level ZVS are introduced in [6].
clamping proposed in this paper is the reduction of the maxi- The input-to-output characteristics, referred to here as static
mum voltage across the active switches by 50% compared to gains, and the basic waveforms of the converters shown in
other two-level ZVS topologies [7]. Nevertheless, in order to Fig. 2 are the same as those for the two-level converters pre-
reduce the voltage stress of the switches, the three-level ZVS sented in [6]. An example of these characteristics is shown
topology uses two active switches in addition to those included in Fig. 3. Furthermore, the two-level buck–boost, buck–cuk,
in other two-level ZVS topologies. buck–sepic, and buck–buck–boost converters present the same
input-to-output ratio as given in
II. THREE-LEVEL ZVS PWM BUCK CONVERTERS Vo
= q = D − 2Ln (1)
A family of buck-type converters is presented in Fig. 2, where Vi
different active clamping strategies are employed in order to where D is the duty cycle, and Ln denotes the normalized output
achieve soft switching and blocking voltage reduction. In Fig. 2, current that has no dimension and is given by
index i relates the source to the input port and o relates the
source to the output ports of the converters. The three-level Io fs
Ln = Lr . (2)
soft-switching active clamping cells are classified according to Vi
RODRIGUES et al.: THREE-LEVEL ZVS ACTIVE CLAMPING PWM FOR THE DC–DC BUCK CONVERTER
Fig. 4. Maximum voltage across the active switches of the buck–boost con-
verter as a function of the input voltage [8].
Among the topologies that present the same static gain, the
buck–boost converter presents a lower component count and
the same or better functionality as the others. Therefore, after
taking the topologies shown in Fig. 2 into account, the following
options will be considered for a buck converter with three-level
ZVS clamping: buck–buck, buck–boost, and buck–zeta.
The transfer function of the buck–buck converter is given in
the next section, while the static gain for the buck–zeta is
Vo D 2Ln
=q= −
Vi 1 − D (1 − D) [2Ln + (1 − D)]
⇒ buck–zeta.
Zeta-type clamping features ZVS operation throughout the
complete load range. However, this type of clamping results in
application of a high voltage across the active switches. There-
fore, based on the comments made in Section I, the buck–zeta
converter is not considered further.
Boost-type clamping is advantageous because of the lower
duty cycle loss. The main drawback of this technique is the
dependence of the maximum voltage across the switches on
duty cycle and power variations. This dependence is clear from
Vo D 2Ln
=q= − and
Vi 1 − D (1 − D) [2Ln + (1 − D)]
Ln Vi
Vswitches = + ⇒ buck –boost.
(1 − D) 2 effects.
This characteristic is depicted in Fig. 4, and it clearly makes
it more difficult to design the circuit components and achieve
the maximum efficiency for a given range of input-to-output
voltage ratios for this type of clamping.
Buck-type clamping features a maximum voltage across the
active switches that is independent of any design parameter. The
voltage across the switches is theoretically clamped to half of
the input voltage. The characteristics of this topology are very
beneficial, and, consequently, the buck–buck converter will be
the focus of analysis in the remainder of this paper.
The two-level converters, forward and flyback, and other
isolated topologies with ZVS have been discussed in the lit-
erature [21]–[29]. The forward-boost three-level design found
in [30] can be expanded to five levels using forward-boost [31].
2251
Fig. 5. Three-level ZVS PWM buck–buck converter.
Clamping buck or clamping boost can be applied in flyback or
forward converters, as presented in [31].
The three-level buck–boost applied in forward-boost [31] and
buck–buck, as presented in this paper, can be applied directly in
a forward-buck, where ZVS and voltage stress reduction have
almost the same characteristics.
III. THREE-LEVEL BUCK–BUCK CONVERTER
For the reasons given in Section II, the topology analyzed
in this section is the buck–buck converter. Fig. 5 presents the
(3) commutation cell for the three-level buck–buck converter and
its basic circuit configuration. In order to ease the understand-
ing of the converter’s operation, the following assumptions are
considered.
1) Switches are ideal.
2) The converter operates in steady state.
3) The output inductance Lo is such that, in conjunction with
output voltage Vo , it can be represented as an ideal current
source (Io ).
4) The resonant inductor Lr stores sufficient energy to com-
plete the charging and discharging of the resonant capac-
itors C1 , C2 ,C3 , and C4 (cf., Fig. 5), with value Cr , dur-
ing the switching transitions and to polarize the intrinsic
diodes of the switches.
5) The passive components are considered free from parasitic
(4)
6) The auxiliary bus capacitance CC is much larger than Cr
and is capable of keeping the voltage unchanged during a
switching cycle. Thus, the auxiliary bus capacitors can be
represented by voltage sources.
A. Converter Operation
Depending on the intervals between the turn-off of the
switches and the value of the resonant capacitors (Cr ), the con-
verter can operate in nine different operation modes. However,
for all cases, the converter operates under ZVS, maintaining its
static-gain characteristic. The differences are noted only in a
few operation stages for very short durations. For this reason,
the analysis developed here is limited to a single representative
case.
2252
Fig. 6. Operation stages of the three-level ZVS buck–buck converter.
In order to simplify the stages, the voltages across capacitors
C5 and C6 are considered balanced and equal to Vi /2. The res-
onant capacitor is chosen so that Cr > Cr lim it , where Cr lim it is
defined in (18). If a voltage imbalance across capacitors C5 and
C6 were considered, the number of operation stages would in-
crease, but the ZVS of the four transistors would be maintained.
The description of the operation stages is summarized shortly,
and they are shown in Fig. 6.
First stage [t1 –t2 ]: Switches S1 and S2 are ON. The current
through inductor Lr is negative. Diode Do is forward-biased.
Second stage [t2 –t3 ]: Switch S1 is turned off, but S2 is still
ON. The current is divided between the resonant capacitors
C1 , C3 , and C4 . The current through Lr is equal to IM
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 10, OCTOBER 2009
(cf., Fig. 8), of which two-thirds circulate through C1 and
one-third through C3 and C4 . The voltage across capacitor
C1 increases from zero to Vx (cf., Fig. 7), which is less than
Vi /2, and the voltages across C3 and C4 decrease from Vi /2
to (Vi /2 − Vx /2). Voltage Vx depends on the interval between
the turning off of switches S1 and S2 .
Third stage [t3 –t4 ]: Switch S2 is turned off, and the current
through the four resonant capacitors is IM /2. When the
voltage across capacitor C1 reaches Vi /2, the fourth stage
begins.
Fourth stage [t4 –t5 ]: A current division occurs as in the second
stage. This stage ends as the voltages across capacitors C3
and C4 reach zero.
RODRIGUES et al.: THREE-LEVEL ZVS ACTIVE CLAMPING PWM FOR THE DC–DC BUCK CONVERTER 2253

Ninth stage [t9 –t10 ]: The current through the four resonant ca-
pacitors is ILr /2. This stage ends when the voltage across C4
reaches Vi /2.
Tenth stage [t10 –t11 ]: The voltage across C1 and C2 continues
to decrease until it reaches VCc /2.
Eleventh stage [t11 –t12 ]: In this stage, diode Do is forward-
biased.
Twelfth stage [t12 –t1 ]: Diodes D1 and D2 are forward-biased
and conduct the resonant inductor current. After this stage,
the circuit is ready to return to first stage again.
Fig. 7 presents the main waveforms of the converter, and the
preceding description is considered for a single switching cycle.
Each operation interval is described using this figure.
From the analysis, the necessary condition for ZVS to occur
is that the switch is turned on only when its parallel capacitor
is discharged. In other words, to achieve zero losses in the
switching intervals, the drive signals of switches S1 and S2
(VG1,G2 ) should transition between t12 and t1 , and the drive
signals of S3 and S4 (VG3,G4 ) should transition between t5 and
t6 . The voltage Vx of Fig. 7 is smaller than VCc /2 and depends
on the turn-off intervals.

B. Static Gain Characteristic

Fig. 7. Main waveforms of the three-level ZVS buck–buck converter. To simplify the derivation of the input-to-output voltage gain
characteristic, the very short time intervals (between t2 and t5
and from t8 to t11 ) are neglected in the following. Therefore,
Fig. 7 can be redrawn as shown in Fig. 8.
Note that duty cycle D is defined as the interval between the
turn-off of switches S1 and S2 and the turn-off of switches S3 and
S4 . The duty cycle is defined in this manner since the drive sig-
nals of the switches are not necessarily complementary. Based
on these assumptions, the static transfer characteristics of the
two- and three-level buck–buck converters are strictly the same.
The inductor current of Fig. 11 shows that the current ripple
at the output is far from being negligible, and the current cannot
be considered constant; however, the equations presented in
this section are sufficiently robust because even under these
conditions, the static gain depends on the average output current.
The average current through capacitor CC , iCc , is computed
using

 
∆1
(Vi − VCc )
Fig. 8. Simplified waveforms of the three-level buck–buck converter.
iCc (t) = iLr (t) = t + IM dt
0 Lr

D T s −∆ 1
(1−D )T s  
−VCc
+ (Io )dt + t + Io dt = 0
0 0 Lr
Fifth stage [t5 –t6 ]: Diodes D3 and D4 are forward-biased. These
diodes conduct the current through inductor Lr . (5)
Sixth stage [t6 –t7 ]: The resonant inductor current becomes pos-
itive and switches S3 and S4 start to conduct. where
Seventh stage [t7 –t8 ]: This stage starts when the resonant in- VCc
ductor current equals Io . The diode Do is reverse-biased. IM = Io − (1 − D)Ts (6)
Lr
Eighth stage [t8 –t9 ]: In this stage, S4 is turned off and the
voltage across C4 increases from zero to Vx , which is less and
than Vi /2, and depends on the interval between the turn-off
of switches S3 and S4 . When switch S3 turns off, the next (IM + Io )Lr
∆1 = . (7)
operation stage begins. (Vi − VCc )
2254 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 10, OCTOBER 2009

1) Vi = 700 V⇒ input voltage.

2) fs = 20 kHz⇒ switching frequency.
3) Vo = 360 V⇒ output voltage.
4) Po = 550 W⇒ output power (Ro ≈ 235 Ω).
5) ∆Vo = 1%⇒ output voltage ripple.
6) t2 –3 = 0.01%/fs ⇒ difference in the turn-off times be-
tween switches S1 and S2 and between S3 and S4 .
In order to choose an adequate value for the resonant in-
ductance, some gate drive timing adjustments were taken into
consideration. The drive signals for switches S1 and S2 were to
be applied right after the resonant capacitors C1 and C2 were
discharged. On the other hand, in order to avoid hard switching,
Fig. 9. Static transfer characteristic. these signals had to be applied before the current of inductor Lr
became positive. In order to allow for a safety margin for the
The normalized load current or normalized resonant induc- drive circuitry, an inductance of 100 µH was chosen. The mini-
tance “Ln ” is defined by mum inductance value for this design was approximately 50 µH.
Io However, this value led to difficulties in the timing adjustment
Ln = Lr . (8) for a wide load variation leading the converter to operate without
Vi Ts
ZVS
The average value of the average current across CC is zero
because the system is under steady-state operation. Thus, by Lr = 100 µH ⇒ Ln = 0.004.
integrating (5) and substituting (6)–(8) into (5), the expression The duty cycle for rated power was computed from (12). Thus
for the relationship between voltages VCc and Vi is obtained
D = 0.557. (13)
2Ln Vi
VCc = . (9)
2Ln + (1 − D)2 The output current was given by

The static gain is given by Vo

Io = = 1.52 A. (14)
Ro
Vo = DVi − VCc . (10)
The output capacitor was sized as for a conventional buck con-
If the system operates in steady state, the gain characteristic verter
is obtained from the sum of the voltages since the average value Vi
of the voltage across inductor Lr is null. Co = 2 ⇒ Co = 78 µF. (15)
fs ∆Vo Vo π 3 Lo
Defining the relationship between input and output voltage as
Because of the current capability of the electrolytic capaci-
Vo tors available for use in the experimental prototype, an output
q= (11)
Vi capacitor of 470 µF was chosen.
and substituting (9) and (11) into (10) gives The low value for output inductance was chosen to increase
the load variation range beyond which the converter can operate
2Ln with ZVS
q=D− . (12)
2Ln + (1 − D)2
Lo = 2 mH. (16)
Fig. 9 presents the static-gain characteristic of the buck con-
verter employing three-level buck-type clamping as a function of The output inductor current ripple was
duty cycle D for different values of normalized inductance Ln . Vo (1 − D)
It is seen that a large voltage drop across the resonant inductor ∆IL o = ⇒ ∆IL o = 3.9 A. (17)
Lo fs
leads to a lower input-to-output voltage ratio. This characteris-
tic reveals that the resonant inductor value should be limited in A resonant frequency ten times larger than the switching
order to obtain a more linear voltage transfer curve. frequency was chosen. Thus, the resonant capacitance was found
with
C. Converter Design 1
Cr = = 8 nF ⇒ Cr = 8.2 nF. (18)
Lr (2π10fs )
The design of the proposed converter is presented in this sec-
tion. The aim was to build a prototype in order to experimentally The auxiliary capacitor operates as a constant voltage source.
verify the theoretical analysis and evaluate the design proce- Thus, from the time analysis
dure. The adopted specifications do not necessarily demand soft √
2π Lr CC (1 − D) 9(1 − D)2
switching due to the relatively low output power. Nevertheless, >3 ⇒ CC > (19)
this design takes advantage of lower voltage switches that offer 2 fs π 2 Lr fs2
lower switching losses and costs. The following specifications
have been employed. CC > 3.9 µF ⇒ CC = 5 µF.
RODRIGUES et al.: THREE-LEVEL ZVS ACTIVE CLAMPING PWM FOR THE DC–DC BUCK CONVERTER 2255

Fig. 10. Schematic of the power circuit for the laboratory prototype.

In order to equally share the voltage in the clamping cell,

the values of capacitors C5 and C6 were chosen to be equal
and were much larger than the resonant capacitors. Thus, C5 =
C6 = 4.4 µF.

D. Experimental Results
A prototype of the three-level buck–buck converter was built
according to the specifications of Section III-D, and its circuit
schematics are presented in Fig. 10. Because the main objective
was to analyze the power circuit performance, the experiments
were conducted with open-loop control, fixing the duty cycle and
observing the circuit’s performance. Furthermore, the control-
oriented modeling of the structures presented here is important
and suitable for a comprehensive study. Gate pulses were gen-
erated by the microcontroller PIC18F4331 and isolated by the
gate drivers SKHI10op.
Due to limitations of the low-cost microcontroller used in
this study, the chosen switching frequency was 20 kHz. The low
resolution can make it difficult to balance the clamping voltages.
On the other hand, closed-loop control of the clamping voltages
can help balance the voltage even with low-resolution PWM.
Thus, in this study, high-frequency operation was made possible
by using closed-loop control of the clamping voltages.
At rated power and a measured dc output voltage Vo =
358.5 V , the waveforms seen in Fig. 11 were recorded. The
voltage across the switches S1 , S2 , S3 , and S4 , and the reso-
nant inductor current are in good agreement with the theoretical Fig. 11. Waveforms for rated power. (a) Voltage across switches S 1 and S 2 ,
waveforms presented in Section II-A, except for the output cur- drive signal of S 1 , and resonant inductor current. (b) Voltage across switches
S 3 and S 4 , drive signal of S 3 , and resonant inductor current.
rent ripple, which causes the current iLr to present a ripple
accordingly.
A detailed view of the commutation turn-on process for
switches S1 and S2 is shown in Fig. 12(a), where ZVS oper- converter. Thus, the aim of reducing voltage stresses by 2 in the
ation can be observed. Fig. 12(b) shows S3 and S4 , which also active switches was achieved in the proposed converter.
operate with ZVS. The measured maximum voltage overshoot The designed converter operates with ZVS from 100% to
for the switches was 375 V, which corresponds to 53% of the 35% of the rated power. Below a 35% load, ZVS transitions
input voltage Vi . This shows that the voltage across the switches were observed only during turn-on commutations. Fig. 13 shows
is effectively halved when compared to a conventional buck the power transfer efficiency curve for three load conditions. A
2256
Fig. 12. Details for the commutations at rated power. (a) Waveforms V S 1 ,
V S 2 , and iL r during the turn-on transition of S 1 and S 2 . (b) Waveforms V S 3 ,
V S 4 , and iL r during the turn-on transition of S 3 and S 4 .
Fig. 13. Buck–buck converter efficiency for 35%, 65%, and 100% of the rated
load.
reduction due to the reactive energy flow generated by the input
inductor current ripple is observed in the efficiency curve.
In order to compare efficiency figures from the built proto-
type to other topologies, it is observed that the efficiency is
close to the one presented in [8]. Duarte and Fiori [11] consider
a two-level ZVS realization and show efficiency data for switch-
ing frequencies that are higher than the ones adopted here. The
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 10, OCTOBER 2009
Fig. 14. Buck–buck converter presenting ZVS at all commutation for all semi-
conductor devices.
tendency, as shown in [11], is for the efficiency of the ZVS
topologies to become higher than the efficiency of conventional
converters at higher switching frequencies, input voltage, and
output power. Consequently, this is highly dependent on appli-
cation and specifications.
During the experiments, the clamping voltages across capac-
itors C5 and C6 , which ultimately define the voltages across the
switches, remained balanced for input voltage variations from
zero to Vi , and full-load variation even though the circuit was
operating in open loop. Thus, no clamping balance strategy was
required.
However, closed-loop simulations have been performed that
show that the clamping voltages can be balanced using a sim-
ple integral controller that controls the time delays between
the gate pulses of different switches. In this context, the out-
put voltage is controllable and well regulated through a PI
controller.
E. ZVS of the Output Diode
Despite the four active switches (S1 , S2 , S3 , and S4 ) that
present ZVS commutations, in the case of the previously pre-
sented buck–buck converter, the turn-off transition for the output
diode Do does not occur under zero-voltage condition, whereas
the turn-on transition does occur. In an application where the as-
sociated switching losses are excessively high, ZVS turn-off can
be a helpful solution. For this situation to occur, a diode Do2 can
be added to the circuit [10], [11], as shown in Fig. 14. With this
configuration, all semiconductor devices present ZVS commu-
tation during both turn-on and turn-off. Furthermore, the static
gain remains unaltered. Considering that the capacitance values
of the capacitors in parallel with diodes Do1 and Do2 are smaller
than or equal to the parasitic capacitances, the current through
inductor Lr will be slightly larger than that for the previously
presented buck–buck converter. If this small increase in current
ILr compared to Io is ignored, the waveforms are basically the
same as those presented in Fig. 7, where the differences are
within the details of the commutations of diodes Do1 and Do2 .
IV. CONCLUSION
This paper has presented a family of high-efficiency buck-
type dc–dc converters that are well suited for high-voltage
RODRIGUES et al.: THREE-LEVEL ZVS ACTIVE CLAMPING PWM FOR THE DC–DC BUCK CONVERTER
applications. The proposed converters combine the advantages
of a reduction of the voltages across the switches, which was
achieved using a three-level commutation cell, with decreased
switching losses obtained from a ZVS technique.
Based on the premise that the converter should limit the volt-
age across the switches to half of the input voltage, a topol-
ogy based on the buck converter and a buck-type three-level
clamping circuit has been identified as the most suitable. This
topology has been theoretically analyzed, and its operation has
been experimentally verified. A limitation posed in this circuit
is the reduction of the input-to-output voltage transfer ratio for
a high duty cycle; however, this is typically not a limiting factor
for step-down converters. A comparison between the proposed
topology and the two-level ZVS buck–buck converter shows that
the voltages across the switches are 50% lower. Nevertheless,
the three-level converter provides two extra bidirectional cur-
rent switches and an additional capacitor for the auxiliary bus
when compared to the two-level converter even though the volt-
age ratings for these devices are halved as well. The three-level
technique provides more gate driver circuits, thus illustrating
another disadvantage of using two-level topologies. In a closed-
loop application, the control of the two clamping voltages needs
to be implemented, and, thus, requires more circuit complexity
and extra voltage sensors. Consequently, the proposed converter
is thought to be a suitable solution in applications where the
switch technology poses a limitation to the available voltage
ratings, no insulation is needed, and a high efficiency at high
switching frequencies is required.
A further modification has been introduced to the proposed
topology for the achievement of ZVS operation for the output
diode as well.
The proposed buck–buck converter can be extended to
corresponding insulated topologies (forward-buck) that are able
to reduce the active switches’ voltage ratings while providing
ZVS. Further extensions are possible which generate five-level
dc–dc converters that reduce the maximum switched voltages
to 25% of the original forward topology. Another advantage of
the forward-buck converter in relation to other converters, such
as the forward- boost, is that capacitor Cc of the buck clamping
circuit is already placed in series with the transformer, which
prevents saturation of the capacitor. For three-level half-bridge
and full-bridge converters with ZVS, the different types of
three-level clamping solutions presented here cannot be directly
employed.
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[1] W. Huang, “A new control for multi-phase buck converter with fast tran-
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2258
Jean Paulo Rodrigues received the B.E. and M.S.
degrees in electrical engineering in 2002 and 2005,
respectively, from the Federal University of Santa
Catarina, Florianópolis, Brazil, where he is currently
working toward the Ph.D. degree at the Power Elec-
tronics Institute.
In 2008, he joined the Mechanic Metal Depart-
ment, Federal Institute of Education, Science and
Technology of Santa Catarina (IFSC), Florianópolis,
where he is currently a Lecturer, and engaged in
education and research on power electronics and
mechatronics. His current research interest is multilevel dc-dc converters for
reduced stresses across power semiconductors.
Samir Ahmad Mussa (M’06) received the B.E. de-
gree in electrical engineering from the Federal Uni-
versity of Santa Maria, Florianópolis, Brazil, in 1988,
and the M.Eng. and Ph.D. degrees in electrical engi-
neering from the Federal University of Santa Catarina
(UFSC), Florianópolis, in 1994 and 2003, respec-
tively.
He is currently a Lecturer at the Power Electronics
Institute (INEP), UFSC. His current research interests
include digital control applied to power electronics,
power factor correction techniques, and digital signal
processing (DSP)/field-programmable gate array (FPGA) applications.
Dr. Mussa is a member of the Brazilian Power Electronics Society
(SOBRAEP).
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 10, OCTOBER 2009
Marcelo Lobo Heldwein (S’99–M’06) received the
B.S. and M.S. degrees in electrical engineering from
Federal University of Santa Catarina, Florianópolis,
Brazil, in 1997 and 1999, respectively, and the Ph.D.
degree from the Swiss Federal Institute of Technol-
ogy (ETH Zurich), Zurich, Switzerland, in 2007.
From 1999 to 2001, he was an R&D Engineer with
the Power Electronics Institute, Federal University of
Santa Catarina, where he is currently a Postdoctoral
Fellow. From 2001 to 2003, he was an Electrical De-
sign Engineer with Emerson Energy Systems, São
José dos Campos, Brazil, and Stockholm, Sweden. His current research interests
include power-factor-correction techniques, static power converters, multilevel
converters, and electromagnetic compatibility for power electronics.
Dr. Heldwein is a member of the Brazilian Power Electronics Society
(SOBRAEP).
Arnaldo José Perin (M’86) received the B.E. degree
in electronic engineering from the Pontificia Univer-
sidade Catolica do Rio Grande do Sul, Porto Alegre,
Brazil, in 1977, the M.Sc. degree in electrical engi-
neering from the Federal University of Santa Catarina
(UFSC), Florianópolis, Brazil, in 1980, and the Dr.
Ing. degree from the Institut National Polytechnique
de Toulouse (INPT), Toulouse, France, in 1984.
In 1980, he joined the Electrical Engineering De-
partment, UFSC, where he is currently engaged in
education and research on power electronics analysis
and design. Since 1993, he has been involved more specifically on electronic
ballast to use with fluorescent lamps, human interface device lamps, and LEDs.
He is the author or coauthor of several research papers presented at Brazilian
and international conferences. His current research interests include power elec-
tronics, modulation, ac converters, and power factor correction.
Dr. Perin is a member of the Brazilian Power Electronics Society
(SOBRAEP).