Philips Semiconductors Linear Products Product specification

Tone decoder/phase-locked loop NE/SE567

DESCRIPTION PIN CONFIGURATIONS

The NE/SE567 tone and frequency decoder is a highly stable
FE, D, N Packages
phase-locked loop with synchronous AM lock detection and power
output circuitry. Its primary function is to drive a load whenever a OUTPUT FILTER 1 8 OUTPUT
CAPACITOR C3
sustained frequency within its detection band is present at the
LOW-PASS FILTER 2 7 GROUND
self-biased input. The bandwidth center frequency and output delay CAPACITOR C2
TIMING
are independently determined by means of four external INPUT 3 6 ELEMENTS R1
AND C1
components. SUPPLY VOLTAGE V+ 4 5 TIMING ELEMENT R1

TOP VIEW
FEATURES F Package
• Wide frequency range (.01Hz to 500kHz)
• High stability of center frequency OUTPUT 1 14 GND

• Independently controllable bandwidth (up to 14%) C3 2 13 NC

• High out-band signal and noise rejection NC 3 12 NC

• Logic-compatible output with 100mA current sinking capability C2 4 11 R1C1

• Inherent immunity to false signals INPUT 5 10 R1

• Frequency adjustment over a 20-to-1 range with an external NC 6 9 NC

resistor VCC 7 8 NC
• Military processing available
TOP VIEW

APPLICATIONS • Frequency monitoring and control

• Touch-Tone decoding • Wireless intercom
• Carrier current remote controls • Precision oscillator
• Ultrasonic controls (remote TV, etc.)
• Communications paging

BLOCK DIAGRAM

R2

3.9k
INPUT 3 PHASE 2
V1 DETECTOR

R1 LOOP
5
CURRENT LOW
CONTROLLED AMP PASS
6 OSCILLATOR FILTER
C1 C2
R3

+
8
QUADRATURE – AMP
PHASE RL
DETECTOR VREF

+V
7 1
C3 OUTPUT
FILTER

Touch-Tone is a registered trademark of AT&T.

April 15, 1992 403 853-0124 06456

 –V 4

R41
R5 R6 R11 R2 R39 R3
R9 R10 R21 5k R42
10k 4.7k
1

April 15, 1992

Q1 Q10 D Q63 Q54 C3

Q14 Q16 Q20

Q8
R7
R26 Q61 Q62 Vref Q55 Q58
Q12
EQUIVALENT SCHEMATIC

Q21 Q56 Q57

Q16 R36 R37
5 Q17 Q18
Philips Semiconductors Linear Products

R48 R49

Q13 2
Q19 B –V
R1 Q59 Q60
–V Q50 C
C2
R19
–V R36 R40 R43
R20 R22 RL
Tone decoder/phase-locked loop

Q6 –V
6
R12 R13 B
C1
EF R45
Q34 Q35 Q36 Q37 F Q47 Q46 Q45 Q44
Q22 Q23

404
R32
Q7
R33
Q30 A E
B R29 R30 Q61
R48 Q40
R14 21k
3 Q33
–V R48
Cc Q32 21k
A
Q43
R15 R16 R23 Vi Q42 Q62
Q3 Q9 R17
R26 R27
Q2 Q25 Q24
R4
Q5
C
Q26
Q30 R34
Q27 Q28

Q41
Q40 B
Q29 B Q31 B Q38

R18 R24 R36 R44

R28

7
NE/SE567
Product specification
Philips Semiconductors Linear Products Product specification

Tone decoder/phase-locked loop NE/SE567

ORDERING INFORMATION
DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG #
8-Pin Plastic SO 0 to +70°C NE567D 0174C
14-Pin Cerdip 0 to +70°C NE567F 0581B
8-Pin Plastic DIP 0 to +70°C NE567N 0404B
8-Pin Plastic SO -55°C to +125°C SE567D 0174C
8-Pin Cerdip -55°C to +125°C SE567FE 0581B
8-Pin Plastic DIP -55°C to +125°C SE567N 0404B

ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER RATING UNIT
TA Operating temperature
NE567 0 to +70 °C
SE567 -55 to +125 °C
VCC Operating voltage 10 V
V+ Positive voltage at input 0.5 +VS V
V- Negative voltage at input -10 VDC
VOUT Output voltage (collector of output transistor) 15 VDC
TSTG Storage temperature range -65 to +150 °C
PD Power dissipation 300 mW

April 15, 1992 405

Philips Semiconductors Linear Products Product specification

Tone decoder/phase-locked loop NE/SE567

DC ELECTRICAL CHARACTERISTICS
V +=5.0V; TA=25°C, unless otherwise specified.
SYM-
PARAMETER TEST CONDITIONS SE567 NE567 UNIT
BOL
Min Typ Max Min Typ Max
Center frequency1
fO Highest center frequency 500 500 kHz
fO Center frequency stability2 -55 to +125°C 35 ±140 35 ±140 ppm/°C
0 to +70°C 35 ±60 35 ±60 ppm/°C
fO Center frequency distribution 1 -10 0 +10 -10 0 +10 %
fO
100kHz

1.1R 1C 1

fO Center frequency shift with supply 1 0.5 1 0.7 2 %/V

f O
100kHz

voltage 1.1R 1C 1
Detection bandwidth
BW Largest detection bandwidth 1 12 14 16 10 14 18 % of fO
f O
100kHz

1.1R 1C 1
BW Largest detection bandwidth skew 2 4 3 6 % of fO
BW Largest detection bandwidth— VI=300mVRMS ±0.1 ±0.1 %/°C
variation with temperature
BW Largest detection bandwidth— VI=300mVRMS ±2 ±2 %/V
variation with supply voltage
Input
RIN Input resistance 15 20 25 15 20 25 kΩ
VI Smallest detectable input voltage4 IL=100mA, fI=fO 20 25 20 25 mVRMS
Largest no-output input voltage4 IL=100mA, fI=fO 10 15 10 15 mVRMS
Greatest simultaneous out-band +6 +6 dB
signal-to-in-band signal ratio
Minimum input signal to wide-band Bn=140kHz -6 -6 dB
noise ratio
Output
Fastest on-off cycling rate fO/20 fO/20
“1” output leakage current V8=15V 0.01 25 0.01 25 µA
“0” output voltage IL=30mA 0.2 0.4 0.2 0.4 V
IL=100mA 0.6 1.0 0.6 1.0 V
tF Output fall time3 RL=50Ω 30 30 ns
tR Output rise time3 RL=50Ω 150 150 ns
General
VCC Operating voltage range 4.75 9.0 4.75 9.0 V
Supply current quiescent 6 8 7 10 mA
Supply current—activated RL=20kΩ 11 13 12 15 mA
tPD Quiescent power dissipation 30 35 mW
NOTES:
1. Frequency determining resistor R1 should be between 2 and 20kΩ
2. Applicable over 4.75V to 5.75V. See graphs for more detailed information.
3. Pin 8 to Pin 1 feedback RL network selected to eliminate pulsing during turn-on and turn-off.
4. With R2=130kΩ from Pin 1 to V+. See Figure 1.

April 15, 1992 406

Philips Semiconductors Linear Products Product specification

Tone decoder/phase-locked loop NE/SE567

TYPICAL PERFORMANCE CHARACTERISTICS

Bandwidth vs Input Largest Detection bandwidth Detection bandwidth as a

Signal Amplitude vs Operating Frequency Function of C2 and C3

(Hz * µ F)
300 15 106

LARGEST BANDWIDTH — % OF O
250

f
INPUT VOLTAGE — mVrms

200 10 105

150

100 5 104

50
C3
C2
0 0 103
0 2 4 6 8 10 12 14 16 0.1 1 10 100 1000 0 2 4 6 8 10 12 14 16
BANDWIDTH — % OF fO CENTER FREQUENCY — kHz BANDWIDTH — % OF fO

Typical Supply Current vs Greatest Number of Cycles Typical Output Voltage vs

Supply Voltage Before Output Temperature

1000 1.0
25
0.9

OUTPUT VOLTAGE PIN 8 — V

500
20 0.8
CUPPLY CURRENT — mA

BANDWIDTH LIMITED BY IL = 100mA

NO LOAD EXTERNAL RESISTOR 0.7
“ON” CURRENT 300
(MINIMUM C2)
0.6
CYCLES

15
100 0.5
10 0.4
QUIESCENT 50
CURRENT 0.3 IL = 30mA
5 BANDWIDTH 0.2
30
LIMITED BY (C2)
0.1
0 10 0
4 5 6 7 8 9 10
1 5 10 50 100 –75 –25 0 25 75 125
BANDWIDTH — % OF fO
SUPPLY VOLTAGE — V TEMPERATURE — °C

Typical Frequency Drift Typical Frequency Drift Typical Frequency Drift

With Temperature With Temperature With Temperature
(Mean and SD) (Mean and SD) (Mean and SD)
1.5 1.5 5.5
+V = 4.75V +V = 5.75V (2) +V = 7.0V (1)
1.0 1.0 2.5 +V = 9.0V (2)

0.5 0.5 0
(1)

0 0 –2.5

–0.5 –0.5 –5.0

–1.0 –1.0 –7.5

–1.5 –1.5 –10

–75 –25 0 25 75 125 –75 –25 0 25 75 125 –75 –25 0 25 75 125

TEMPERATURE — °C TEMPERATURE — °C TEMPERATURE — °C

April 15, 1992 407

Philips Semiconductors Linear Products Product specification

Tone decoder/phase-locked loop NE/SE567

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

Center Frequency
Center Frequency Temperature
Shift With Supply Typical Bandwidth Variation
Coefficient
Voltage Change vs Temperature
(Mean and SD)
Operating Frequency
100
TEMPERATURE COEFFICIENT— ppm/ ° C

1.0 15.0 14
0.9 12
0 12.5
0.8

BANDWIDTH — % OF f O
10
0.7 10.0
8
–100
t 0.6
O
ń V * %ń V 7.5
t 0.5
O 6
0.4
–200 5.0 4
∆t = 0°C to 70°C 0.3
0.2 2
2.5
–300 0.1 BANDWIDTH AT 25°C
4.5 5.0 5.5 6.0 6.5 7.0 0
0
1 2 3 4 5 10 20 40 100 –75 –25 0 25 75 125
SUPPLY VOLTAGE — V
CENTER FREQUENCY — kHz TEMPERATURE – °C

DESIGN FORMULAS OPERATING INSTRUCTIONS

Figure 1 shows a typical connection diagram for the 567. For most
1
fO [ applications, the following three-step procedure will be sufficient for
1.1R 1 C 1
choosing the external components R1, C1, C2 and C3.

BW [
VI v
Where
VI=Input voltage (VRMS)
C2=Low-pass filter capacitor (µF)
PHASE-LOCKED LOOP TERMINOLOGY CENTER
FREQUENCY (fO)
The free-running frequency of the current controlled oscillator (CCO)
in the absence of an input signal.
1070 Ǹ VI
fO C2
in % of f O
1. Select R1 and C1 for the desired center frequency. For best
temperature stability, R1 should be between 2K and 20K ohm,
and the combined temperature coefficient of the R1C1 product
should have sufficient stability over the projected temperature
200mV RMS
range to meet the necessary requirements.
2. Select the low-pass capacitor, C2, by referring to the Bandwidth
versus Input Signal Amplitude graph. If the input amplitude
Variation is known, the appropriate value of fO ⋅ C2 necessary to
give the desired bandwidth may be found. Conversely, an area of
operation may be selected on this graph and the input level and
C2 may be adjusted accordingly. For example, constant
bandwidth operation requires that input amplitude be above
200mVRMS. The bandwidth, as noted on the graph, is then
controlled solely by the fO ⋅ C2 product (fO (Hz), C2(µF)).

Detection Bandwidth (BW)

The frequency range, centered about fO, within which an input signal
above the threshold voltage (typically 20mVRMS) will cause a logical
zero state on the output. The detection bandwidth corresponds to
the loop capture range.

Lock Range
The largest frequency range within which an input signal above the
threshold voltage will hold a logical zero state on the output.

Detection Band Skew

A measure of how well the detection band is centered about the
center frequency, fO. The skew is defined as (fMAX+fMIN-2fO)/2fO
where fmax and fmin are the frequencies corresponding to the
edges of the detection band. The skew can be reduced to zero if
necessary by means of an optional centering adjustment.

April 15, 1992 408

Philips Semiconductors Linear Products Product specification

Tone decoder/phase-locked loop NE/SE567

TYPICAL RESPONSE saturates; its collector voltage being less than 1.0 volt (typically
0.6V) at full output current (100mA). The voltage at Pin 2 is the
phase detector output which is a linear function of frequency over
INPUT
the range of 0.95 to 1.05 fO with a slope of about 20mV per percent
of frequency deviation. The average voltage at Pin 1 is, during lock,
a function of the in-band input amplitude in accordance with the
OUTPUT transfer characteristic given. Pin 5 is the controlled oscillator square
wave output of magnitude (+V -2VBE)≅(+V-1.4V) having a DC
NOTE: average of +V/2. A 1kΩ load may be driven from pin 5. Pin 6 is an
RL = 100Ω exponential triangle of 1VP-P with an average DC level of +V/2. Only
Response to 100mVRMS Tone Burst high impedance loads may be

OUTPUT OUTPUT
(PIN 8) V+
7% 14% BW
0
VCE (SAT) < 1.0V
INPUT

NOTES: 3.9V
S/N = –6dB
RL = 100Ω LOW PASS
Noise Bandwidth = 140Hz FILTER 3.8V
(PIN 2)

Response to Same Input Tone Burst 3.7V

With Wideband Noise
3. The value of C3 is generally non-critical. C3 sets the band edge 0.9fO fO 1.1fO
of a low-pass filter which attenuates frequencies outside the
detection band to eliminate spurious outputs. If C3 is too small,
PIN 1
frequencies just outside the detection band will switch the output VOLTAGE
(AVG) 4.0
stage on and off at the beat frequency, or the output may pulse VREF
on and off during the turn-on transient. If C3 is too large, turn-on THRESHOLD VOLTAGE
3.5
and turn-off of the
3.0
f1 = fO
+V +V 2.5
0 100 200mVrms
IN-BAND
INPUT
4 VOLTAGE
INPUT 3 RL
5 Figure 2. Typical Output Response

567 8
1 R1
f

O R 1C 1
R2
6
2 7 1

C1 C2
C3
LOW OUTPUT
PASS FILTER
FILTER

Figure 1.

output stage will be delayed until the voltage on C3 passes the

threshold voltage. (Such delay may be desirable to avoid spurious
outputs due to transient frequencies.) A typical minimum value for
C3 is 2C2.
4. Optional resistor R2 sets the threshold for the largest “no output”
input voltage. A value of 130kΩ is used to assure the tested limit
of 10mVRMS min. This resistor can be referenced to ground for
increased sensitivity. The explanation can be found in the
“optional controls” section which follows.

AVAILABLE OUTPUTS (Figure 1)

The primary output is the uncommitted output transistor collector,
Pin 8. When an in-band input signal is present, this transistor

April 15, 1992 409

Philips Semiconductors Linear Products Product specification

Tone decoder/phase-locked loop NE/SE567

cause supply voltage fluctuations which could, for example, shift the
V+ detection band of narrow-band systems sufficiently to cause
momentary loss of lock. The result is a low-frequency oscillation into
and out of lock. Such effects can be prevented by supplying heavy
R
load currents from a separate supply or increasing the supply filter
567 1 567 1 capacitor.
C3 R
C3

SPEED OF OPERATION
DECREASE INCREASE Minimum lock-up time is related to the natural frequency of the loop.
SENSITIVITY SENSITIVITY The lower it is, the longer becomes the turn-on transient. Thus,
maximum operating speed is obtained when C2 is at a minimum.
V+
When the signal is first applied, the phase may be such as to initially
DECREASE
RA SENSITIVITY drive the controlled oscillator away from the incoming frequency
RB
567 1 rather than toward it. Under this condition, which is of course
2.5k
50k unpredictable, the lock-up transient is at its worst and the theoretical
INCREASE
C3 SENSITIVITY
RC minimum lock-up time is not achievable. We must simply wait for the
1.0k transient to die out.
SILICON
DIODES FOR The following expressions give the values of C2 and C3 which allow
TEMPERATURE highest operating speeds for various band center frequencies. The
COMPENSATION
(OPTIONAL) minimum rate at which digital information may be detected without
information loss due to the turn-on transient or output chatter is
Figure 3. Sensitivity Adjust about 10 cycles per bit, corresponding to an information transfer rate
connected to pin 6 without affecting the CCO duty cycle or of fO/10 baud.
temperature stability. V+ V+
V+ V+

RA
RL 200 TO 1k
OPERATING PRECAUTIONS RL

A brief review of the following precautions will help the user achieve 567 8 567 8
the high level of performance of which the 567 is capable. 1 1 Rf RL
Cf Rf 10k
1. Operation in the high input level mode (above 200mV) will free 10k
1
C3
the user from bandwidth variations due to changes in the in-band Rf* 567 8
signal amplitude. The input C3 10k
stage is now limiting, however, so that out-band signals or high RA
*OPTIONAL - PERMITS 200 TO
noise levels can cause an apparent bandwidth reduction as the 1k
LOWER VALUE OF Cf
inband signal is suppressed. Also, the limiting action will create
in-band components from sub-harmonic signals, so the 567
Figure 4. Chatter Prevention
becomes sensitive to signals at fO/3, fO/5, etc.
V+
2. The 567 will lock onto signals near (2n+1) fO, and will give an
output for signals near (4n+1) fO where n=0, 1, 2, etc. Thus,
signals at 5fO and 9fO can cause an unwanted output. If such R
signals are anticipated, they should be attenuated before
567 2 567 2
reaching the 567 input.
C2 R
3. Maximum immunity from noise and out-band signals is afforded C2
LOWERS fO RAISES fO
in the low input level (below 200mVRMS) and reduced bandwidth
operating mode. However, decreased loop damping causes the
worst-case lock-up time to increase, as shown by the Greatest V+
Number of Cycles Before Output vs Bandwidth graph. LOWERS fO
RA
4. Due to the high switching speeds (20ns) associated with 567 567 1 RB
2.5k
operation, care should be taken in lead routing. Lead lengths 50k
C2
should be kept to a minimum. The power supply should be RC RAISES fO
RAISES fO
adequately bypassed close to the 567 with a 0.01µF or greater 1.0k
capacitor; grounding paths should be carefully chosen to avoid SILICON
ground loops and unwanted voltage variations. Another factor DIODES FOR
TEMPERATURE
which must be considered is the effect of load energization on COMPENSATION
(OPTIONAL)
the power supply. For example, an incandescent lamp typically
draws 10 times rated current at turn-on. This can be somewhat
Figure 5. Skew Adjust
greater when the output stage is made less sensitive, rejection of
third harmonics or in-band harmonics (of lower frequency
signals) is also improved.

April 15, 1992 410

Philips Semiconductors Linear Products Product specification

Tone decoder/phase-locked loop NE/SE567

130 SENSITIVITY ADJUSTMENT (Figure 3)

C2 + m F When operated as a very narrow-band detector (less than 8
fO
percent), both C2 and C3 are made quite large in order to improve
noise and out-band signal rejection. This will inevitably slow the
260
C3 + m F response time. If, however, the output stage is biased closer to the
fO
threshold level, the turn-on time can be
In cases where turn-off time can be sacrificed to achieve fast improved. This is accomplished by drawing additional current to
turn-on, the optional sensitivity adjustment circuit can be used to terminal 1. Under this condition, the 567 will also give an output for
move the quiescent C3 voltage lower (closer to the threshold lower-level signals (10mV or lower).
voltage). However, sensitivity to beat frequencies, noise and By adding current to terminal 1, the output stage is biased further
extraneous signals will be increased. away from the threshold voltage. This is most useful when, to obtain
maximum operating speed, C2 and C3 are made very small.
Normally, frequencies just outside the detection band could cause
OPTIONAL CONTROLS (Figure 3) false outputs under this condition. By desensitizing the output stage,
The 567 has been designed so that, for most applications, no the out-band beat notes do not feed through to the output stage.
external adjustments are required. Certain applications, however, Since the input level must
will be greatly facilitated if full advantage is taken of the added
control possibilities available through the use of additional external V+ V+
components. In the diagrams given, typical
values are suggested where applicable. For best results the RL
resistors used, except where noted, should have the same
567 8
temperature coefficient. Ideally, silicon diodes would be
low-resistivity types, such as forward-biased transistor base-emitter 1

junctions. However, ordinary low-voltage diodes should be adequate RA

for most applications. 10k

250 Rf
20k
CA C3
0.5k 0.9k 1.4k 1.9k 2.5k 3.2k 4.0k
200 UNLATCH
INPUT VOLTAGE MV — RMS

10k V+
150

20k V+
RL
100
100k 567 8
UNLATCH
1
50
R
Rf
20k
0 C3
0 2 4 6 8 10 12 14 16

DETECTION BAND — % OF fO

NOTE:
V+ CA prevents latch-up when power supply is turned on.
RA
50k Figure 7. Output Latching
PIN 2 RB
567 R BR
C
R + R )
A RB ) R
C
C2 RC

OPTIONAL SILICON
DIODES FOR
TEMPERATURE
COMPENSATION

NOTE:
130
f
ǒ 10k R) RǓ t C2 t
f
ǒ
1300 10k )
R
R
Ǔ
O O
Adjust control for symmetry of detection band edges
about fO.

Figure 6. BW Reduction

April 15, 1992 411

Philips Semiconductors Linear Products
Tone decoder/phase-locked loop
CHATTER PREVENTION (Figure 4)
Chatter occurs in the output stage when C3 is relatively small, so
that the lock transient and the AC components at the quadrature
phase detector (lock detector) output cause the output stage to
move through its threshold more than once. Many loads, for
example lamps and relays, will not respond to the chatter. However,
logic may recognize the chatter as a series of outputs. By feeding
the output stage output back to its input (Pin 1) the chatter can be
eliminated. Three schemes for doing this are given in Figure 4. All
operate by feeding the first output step (either on or off) back to the
input, pushing the input past the threshold until the transient
conditions are over. It is only necessary to assure that the feedback
time constant is not so large as to prevent operation at the highest
anticipated speed. Although chatter can always be eliminated by
making C3 large, the feedback circuit will enable faster operation of
the 567 by allowing C3 to be kept small. Note that if the feedback
time constant is made quite large, a short burst at the input
frequency can be stretched into a long output pulse. This may be
useful to drive, for example, stepping relays.
DETECTION BAND CENTERING (OR SKEW)
ADJUSTMENT (Figure 5)
When it is desired to alter the location of the detection band
(corresponding to the loop capture range) within the lock range, the
circuits shown above can be used. By moving the detection band to
one edge of the range, for example, input signal variations will
expand the detection band in only one direction. This may prove
useful when a strong but undesirable signal is expected on one side
or the other of the center frequency. Since RB also alters the duty
cycle slightly, this method may be used to obtain a precise duty
cycle when the 567 is used as an oscillator.
April 15, 1992
Product specification
NE/SE567
ALTERNATE METHOD OF BANDWIDTH
REDUCTION (Figure 6)
Although a large value of C2 will reduce the bandwidth, it also
reduces the loop damping so as to slow the circuit response time.
This may be undesirable. Bandwidth can be reduced by reducing
the loop gain. This scheme will improve damping and permit faster
operation under narrow-band conditions. Note that the reduced
impedance level at terminal 2 will require that a larger value of C2 be
used for a given filter cutoff
frequency. If more than three 567s are to be used, the network of RB
and RC can be eliminated and the RA resistors connected together.
A capacitor between this junction and ground may be required to
shunt high frequency components.
OUTPUT LATCHING (Figure 7)
To latch the output on after a signal is received, it is necessary to
provide a feedback resistor around the output stage (between Pins 8
and 1). Pin 1 is pulled up to unlatch the output stage.
REDUCTION OF C1 VALUE
For precision very low-frequency applications, where the value of C1
becomes large, an overall cost savings may be achieved by
inserting a voltage-follower between the R1 C1 junction and Pin 6,
so as to allow a higher value of R1 and a lower value of C1 for a
given frequency.
PROGRAMMING
To change the center frequency, the value of R1 can be changed
with a mechanical or solid state switch, or additional C1 capacitors
may be added by grounding them through saturating NPN
transistors.
412
Philips Semiconductors Linear Products Product specification

Tone decoder/phase-locked loop NE/SE567

TYPICAL APPLICATIONS
+

R3
567 DIGIT
897Hz 1
R2
R1 C3 + 2
C1 C2
3
567
770Hz 4

+ 5

6
567
852Hz 7

8
+

9
567
941Hz 0

+
*

567
1209Hz

NOTES: +
Component values (Typical)
R1 = 26.8 to 15kΩ
567
R2 = 24.7kΩ 1336Hz
R3 = 20kΩ
C1 = 0.10mF
C2 = 1.0mF 5V +
C3 = 2.2mF 6V
C4 = 250µF 6V
567
1477Hz

Touch-Tone Decoder

April 15, 1992 413

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Tone decoder/phase-locked loop NE/SE567

TYPICAL APPLICATIONS (Continued)

+5 TO 15V

60Hz AC LINE 50–200VRMS

LOAD 5
C4
27pF 567
R1
3 567 8 K1 – +
5 6 2 1 6
500pF +

R1 C1 5741
1:1
2.5kΩ
fO ≈ 100kHz
C2
.006
Precision VLF
C1 AUDIO OUT
C3
(IF INPUT IS
0.004mfd .02 FREQUENCY +V
MODULATED)

Carrier-Current Remote Control or Intercom 3 567 8

5 6 2 1

+V
R1
INPUT SIGNAL
(>100mVrms)
20k C2

f1 C1 C3
3 567 8
5 6 2 1
RL

R1
3 567 8
INPUT NOR VO
CHANNEL +V 5 6 2 1
C1 C2 C3
OR RECEIVER

R’1 130
20k CȀ 2 + C 2 + (mfd)
f
O
f2 CȀ 1 + C 1
3 567 8
RȀ 1 + 1.12R 1
5 6 2 1 C’1 C’2

R’1
24% Bandwidth Tone Decoder

OUTPUT
(INTO 1k
OHM MIN.
C’1 C’2 C’3 100mv (pp) LOAD)
SQUARE OR 3 567 5
50mVRMS
SINE INPUT
2 6 f2
Dual-Tone Decoder +90°
R1 PHASE
SHIFT

C2 C1
NOTES:
R2 = R1/5
Adjust R1 so that φ = 90° with control midway.

0° to 180° Phase Shifter

NOTES:
1. Resistor and capacitor values chosen for desired frequencies and bandwidth.
2. If C3 is made large so as to delay turn-on of the top 567, decoding of sequential (f1 f2) tones is possible.

April 15, 1992 414

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Tone decoder/phase-locked loop NE/SE567

TYPICAL APPLICATIONS (Continued)

+
+

RL
RL 567

3 567 8 567 8 2 6 5
80°
2 6 5 2 6 5 3 VCO
TERMINAL
CONNECT PIN 3 fO (±6%)
TO 2.8V TO R1
INVERT OUTPUT RL > 1000Ω

R1 RL > 1000Ω R1
10k
C2 C1

C2 C1
CL

Oscillator With Double Frequency Precision Oscillator With 20ns

Oscillator With Quadrature Output
Output Switching

+
567
RL
6 5
567 8 RL OUTPUT

567 8
3 6 5 1
1kΩ (MIN)
2 6 5 1
10kΩ
VCO
TERMINAL
(±6%) R1
100kΩ
R1

C2 C1
DUTY
C1 C1 CYCLE
ADJUST

Precision Oscillator to Switch 100mA

Pulse Generator With 25% Duty Cycle Pulse Generator
Loads

April 15, 1992 415

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