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Whenever the FET is operated in the current saturated re- when VGS = 0 (6)
gion, its output conductance is very low. This occurs
whenever the drain-source voltage VDS is at least 50%
So as VGS → VGS(off), goss → Zero. For best regulation,
greater than the cut-off voltage VGS(off). The FET may be
ID must be considerably less than IDSS.
biased to operate as a constant-current source at any cur-
rent below its saturation current IDSS.
Cascading for Low goss
Basic Source Biasing
It is possible to achieve much lower goss per unit ID by
For a given device where IDSS and VGS(off) are known, the cascading two FETs, as shown in Figure 2.
approximate VGS required for a given ID is
S D
I
1k D
ID (1)
V GS V GS(off) 1 – Q1 Q2
DSS
S
RL
where k can vary from 1.8 to 2.0, depending on device ge- RS
ometry. If K = 2.0, the series resistor RS required between
source and gate is – +
VDD
V GS V GS(off) ID
RS or RS 1– IDSS (2)
ID ID
Figure 2. Cascade FET Current Source
Updates to this app note may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70596.
Siliconix 1
10-Mar-97
AN103
JFET may have a typical goss = 4 mS at VDS = 20 V and
D
VGS = 0. At VDS –VGS(off) = 2 V, goss 100 mS.
Q2
S
The best FETs for current sources are those having long
D
gates and consequently very low goss. The Siliconix
Q1
S 2N4340, J202, and SST202 exhibit typical goss = 2 mS at
VDS = 20 V. These devices in the circuit of Figure 4 will
provide a current source adjustable from 5 mA to 0.8 mA
(a)
with internal impedance greater than 2 MW at 0.2 mA.
Other Siliconix part types such as the 2N4392, J112, and
IO SST112 can provide 10 mA or higher current.
I2
VGS2gfs2 +
goss2 VDS2 + –
–
+ D
VO Q1 30 V
– S
+
goss1 VDS1 = –VGS2
– = IO/goss1 200 W (Optional)
(b) RS RS = 1 MW
2 Siliconix
10-Mar-97
AN103
CR160
CR180
CR200
IF CR220
CR240
CR270
VF TO-18 2-Lead CR300
Package CR330
CR360
CR390
CR430
Part Type
CR470
J500
J501
SST/J502
SST/J503
SST/J504
SST/J505
SST/J506
SST/J507
SST/J508
J = TO-226AA 2-Lead Package SST/J509
SST = TO-236 (SOT-23) Package SST/J510
SST/J511
Siliconix 3
10-Mar-97
AN103
2.00
TJ = –55C VDS = 4 to 20 V
1.75 2N4339 max
RS = 0.2 k SST/J202 (low
0.75 2k
125C
0.50
5k
0.25
10 k
20 k
0
0 –0.4 –0.8 –1.2 –1.6 –2
VGS – Gate-Source Voltage (V)
1000
VDD = 5 to 30 V
TJ = 25C except as noted
I D – Drain Current ( A)
TJ = –55C
25C
2N/PN4118A 2N/PN4119A
SST4118 Max SST4119 Max
125C
100
2N/PN4117A 2N/PN4118A
SST4117 Max SST4118 Min
2N/PN4119A
SST4119 Min
2N/PN4117A
SST4117 Min
10
0.1 0.5 1 5 10 50 100
RS – Source Resistance (k)
2
TJ = –55C 25C SST/J202 Max
2N4339 Max VDD = 4 to 20 V
1 125C TJ = 25C except as noted
I D – Drain Current (mA)
SST/J201 Max
2N4338 Max
SST/J202 Min
2N4339 Min
SST/J201
2N4338 Min
0.1
VDD
RS
0.01
0.1 0.5 1 5 10 20
RS – Source Resistance (k)
4 Siliconix
10-Mar-97
AN103
Choosing the Correct JFET for Source Table 1: Source Biasing Device Recommendations
Biasing
Each of the Siliconix device data sheets include typical Practical
Current Surface
transfer curves that can be used as illustrated in Figure 7. Range ID Through-Hole Mount Metal Can
(mA) Plastic Device Device Device
Several popular devices are ideal for source biased cur-
rent sources covering a few As to 20 mA. To aid the de- 0.01 – 0.02 PN4117A SST4117 2N4117A
signer, the devices in Table 1 have been plotted to show 0.01 – 0.04 PN4118A SST4118 2N4118A
the drain current, ID, versus the source resistance, RS, in 0.02 – 0.1 PN4119A SST4119 2N4119A
Figures 8, 9, and 10. Most plots include the likely worst 0.01 – 0.1 J201 SST201 2N4338
case ID variations for a particular RS. For tighter current
0.02 – 0.3 J202 SST202 2N4339
control, the JFET production lot can be divided into
0.1 – 2 J113 SST113 2N4393
ranges with an appropriate resistor selection for each
range. 0.2 – 10 J112 SST112 2N4392
20
–55C VDD = 5 to 30 V
10 TJ = 25C TJ = 25C except as noted
I D – Drain Current (mA)
125C Mid
2N4392,
SST/J112
2N4393,
Mid
SST/J113 Max
Min 2N4393 Min 2N4392,
SST/J113
1 SST/J112
VDD
RS
0.1
0.1 0.5 1 5 10
Siliconix 5
10-Mar-97