International Journal of Electronic Engineering Research

ISSN 0975 - 6450 Volume 2 Number 4 (2010) pp. 589–596

© Research India Publications
http://www.ripublication.com/ijeer.htm

Design of Integer N Frequency Divider for High

Performance PLL using 180 nM CMOS Technology

*R.H. Talwekar, S.S. Limaye and Nikahat Parveen Khan

*Department. of Electronics and Telecommunication, DIMAT, Raipur, India

*Department of Electronics and Telecommunication, JIT, Nagpur, India
*E-mail: ur_talwekar@yahoo.com, shyam_limaye@hotmail.com

Abstract

The frequency divider has been implemented in a 180 nm standard CMOS

technology. The divider has the mod value of 240 which is made by
concatenated mod-16 and mod-15 frequency dividers. The circuits are
simulated on Virtuoso Cadence tool with GPDK 180nM CMOS technology.
The frequency divider is an important building block in today’s
telecommunication and microwave circuits because it is an integral part of the
phase-locked loop (PLL) circuit. In a typical PLL loop, the output of the
voltage-controlled oscillator (VCO) is divided by the frequency divider to
generate a frequency which is compatible to the reference frequency.
Integer-N frequency divider is carried out using CMOS technology and
digital techniques. Design of circuits by CMOS technology is done using
Virtuoso Cadence tool. It is a versatile tool that enables the designer to design
on various levels of VLSI. In this work, 180 nM CMOS technology is enabled
using GPDK 180. We proposed a mod-240 frequency divider logic which
adopts D-type positive-edge triggered flip-flop to design the circuit for high
performance PLL. This is suitable for high speed PLL circuits and can work at
a low supply. The integer-N frequency divider is designed in a standard
CMOS 180 nM technology. The Cadence simulation results show the
capability of high-frequency operation at 2.4 GHz with a reference frequency
of 10 MHz at 1.8 V power supply[1]. Here we have tried to achieve for the
better selection of design to speed up operation of frequency divider and tried
to decrease power consumption and supply voltage with high operating
frequency and low power dissipation with wide range of divide ratio .It has
been designed by keeping high divider’s stability and prepared a less
complex design for high modulus value.

Keyword: PLL -Phase Locked Loop, APLL- Analog Phase Locked Loop,D-
ff - D flip-flop, PFD-Phase Frequency Detector, CP -Charge Pump, LF -Loop
590 R.H. Talwekar et al

Filter, AMP –Amplifier, VCO-Voltage Controlled Oscillator, GPDK - Generic

Process Design Kit , CMOS-Complementary Metal Oxide Semiconductor.

Introduction
Phase locked loop (PLL) represents the dominant method in the wireless
communications industry. In most of the wireless communication technologies a PLL
has been using. The ability to execute all PLL functions on a single integrated circuit
(IC) has created an economical, mass production solution to meet the needs of
industry. Current PLL ICs are highly integrated digital and mixed signal circuits that
operate on low supply voltages and consume very low power. A phase-locked loop is
a sort of circuit whose output signal keeps a constant phase difference with a
reference signal through feedback. It can be described using the following diagram:
Now look at the classic PLL block diagram as shown below. In wireless
communication wherever orthogonal frequency division multiplexing (OFDM) has
been used, requires very compact and perfect synchronization of signal frequency.

Figure 1: Basic PLL.

Designing a 2.4 GHz phase locked loop for multi-carrier communication with
high stability using 0.18μM CMOS technology is also a challenge in CMOS
Technology. A PLL mainly consist of phase frequency detector (PFD), charge pump
(CP), low pass filter (LPF), voltage controlled oscillator (VCO) and divider circuit. A
particular part of the PLL that is divider circuit is used to divide the VCO frequency
which has been designed using CMOS 180 nM technology using Cadence tools. The
PLL is a negative feedback system, which makes two input frequencies equal at the
steady state. If two frequencies are different, PLL produces phase error signal Φe
which is used to generate proportional dc voltage at the PFD output, the phase
detector compares this signal with incoming frequency and if the signals are the
same, it puts out very small corrections. If incoming frequency is greater than VCO
frequency, then it sinks current. If , incoming frequency is less than the VCO
frequency then it sources current. The loop filter is a low pass filter that converts these
current corrections into a voltage. The VCO converts this voltage to a frequency. This
output frequency, fo is divided down by the N counter and compared to fvco. The
PLL also provides the very important advantage that the N counter can be changed by
programming it to different values. This allows the PLL to be able to synthesize many
Design of Integer N Frequency Divider for High Performance PLL 591

different frequencies from a fixed frequency[2]. The first component in our PLL is the
phase frequency detector. The output of the PFD depends on both the phase and
frequency of the inputs. This type of phase detector is also termed a sequential phase
detector. There are several characteristic of PFD which can be described as below.
Phase frequency detector is one of the important parts in PLL circuits. PFD (Phase
Frequency Detector) is a circuit that measures the phase and frequency difference
between two signals, i.e. the signal that comes from the VCO and the reference signal.
PFD has two outputs UP and DOWN which are signaled according to the phase and
frequency difference of the input signals. The second component in this PLL is the
loop filter. In this work, we used the charge pump which consists of NMOS and
PMOS are connected serially. The input to the VCO is the output signal of loop
filter. When the voltage of the input signal to VCO is high, the frequency of output
signal in VCO becomes larger and larger. The paper is organized as follows.
Description of phase locked loop is done in section I. In section II PLL with integer-N
frequency divider circuit has described .In section III, diagram of conventional and
proposed D-ff has described. In Section IV proposed MOD-240 frequency divider
logic has given in detail. In section V, simulation result and waveforms have been
shown. Section VI will draw a conclusion.

PLL with Integer-N Frequency Divider

A divider N frequency chip is used in the PLL circuit to produce a fraction of
incoming frequency to the PFD circuit and generates an output signal with a
frequency fout = fin/ N, where N is an integer. In PLL, a very high frequency is obtained
from VCO. The value of input reference frequency of PFD is comparatively very
less than VCO frequency. To attain the locking situation of the PLL, both the signal
from VCO and incoming frequency should be same .Therefore, to match the VCO
frequency with reference frequency, it is necessary to divide the VCO frequency[3].
Generally D flip-flop is used as a binary divider as it divides the clock frequency by 2
at each positive or negative going clock pulse. N number of flip flops are required to
design a divide by N frequency divider when used in ring counter configuration and
in Johnson’s counter N flip flops gives the divide value of 2N. Here we have tried to
achieve for the better selection of design to speed up operation of frequency divider,
to decrease power consumption and supply voltage with high operating frequency and
low power dissipation by wide range divide ratio keeping high divider’s stability and
have prepared a less complex design for high modulus value . The target of our
project is to design a modulo 240 frequency divider using positive edge triggered fast
D-flip flop. For high speed operation, the circuit adopts D-type Positive-Edge-
Triggered flip-flop[4]. It also lowers the power consumption. The main concentration
of the work will be on designing an efficient divider with less number of flip flops
which would result in a very high speed and less power consumption. Generally D
flip-flop is used as a binary divider. N number of flip flops are required to design a
divide by N frequency divider when used in ring counter configuration and in
Johnson’s counter N flip flops gives the divide value of 2N[6]. Our main target in this
work is to design the circuit with minimum number of flip flops whose approach will
592 R.H. Talwekar et al

be based on digital logic. To reduce the complexity, the divide by 240 divider is
designed in two parts. Firstly, mod-16 divider is designed, which is concatenated with
another divider, whose mod value is 15.

Figure 2: Block diagram of PLL with frequency divider.

Proposed work
A unit of proposed divider chip that is D-ff is shown in figure 3. This flip-flop
modifies the TSPC flip-flop to satisfy the required function of D-ff. When input clock
and reset signals are low, node A is connected to VDD through m1, mr1 and charges
the node A to VDD. At the rising edge of the clock signal node B is connected to
ground through m3 and m4. Once the node A is charged to VDD, node B is not
affected by input clock signal because charges at node A turn off m3 and this prevents
the node B from being pulled up. Therefore the node B is disconnected from input
node. When reset signal is applied node A is disconnected from VDD by mr1 and is
connected to ground by mr2. As soon as node A is discharged node B is pulled up
through m2. The mr1 is added to prevent the short circuit that occurs whenever the
reset signal is applied[7].

Figure 3: Single unit of proposed divider chip.

Design of Integer N Frequency Divider for High Performance PLL 593

Proposed MOD-240 frequency divider

The mod-240 divider has designed in two parts. Firstly, mod-16 divider is designed,
which is concatenated with another divider, whose mod value is 15.The realization
of the desired circuit has been done using ‘Karnaugh map’ the truth table of divider
16 and 15 are shown in Table 1 and Table 2 ,which are plotted by observing present
and next states of the flip flops. The D-flip flops in these circuits are used as T flip -
flops by adding a XOR gate at input.

Table 1: Excitation table for mod-16.

Present state Next state T –FF output

Present state Next state T –FF output
Q3 Q2 Q1 Q0 Q3’ Q2’ Q1’ Q0’ T3 T2 T1 T0

0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 1
0 0 1 1 0 1 0 0 0 1 1 1
0 1 0 0 0 1 0 1 0 0 0 1
0 1 0 1 0 1 1 0 0 0 1 1
0 1 1 0 0 1 1 1 0 0 0 1
0 1 1 1 1 0 0 0 1 1 1 1
1 0 0 0 1 0 0 1 0 0 0 1
1 0 0 1 1 0 1 0 0 0 1 1
1 0 1 0 1 0 1 1 0 0 0 1
1 0 1 1 1 1 0 0 0 1 1 1
1 1 0 0 1 1 0 1 0 0 0 1
1 1 0 1 1 1 1 0 0 0 1 1
1 1 1 0 1 1 1 1 0 0 0 1
1 1 1 1 0 0 0 0 1 1 1 1

Table 2: Excitation table for mod-15.

Present state Next state T –FF output

Q3 Q2 Q1 Q0 Q3’ Q2’ Q1’ Q0’ T3 T2 T1 T0

0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 1
0 0 1 1 0 1 0 0 0 1 1 1
0 1 0 0 0 1 0 1 0 0 0 1
0 1 0 1 0 1 1 0 0 0 1 1
0 1 1 0 0 1 1 1 0 0 0 1
0 1 1 1 1 0 0 0 1 1 1 1
594 R.H. Talwekar et al

1 0 0 0 1 0 0 1 0 0 0 1
1 0 0 1 1 0 1 0 0 0 1 1
1 0 1 0 1 0 1 1 0 0 0 1
1 0 1 1 1 1 0 0 0 1 1 1
1 1 0 0 1 1 0 1 0 0 0 1
1 1 0 1 1 1 1 0 0 0 1 1
1 1 1 0 0 0 0 0 1 1 1 0
1 1 1 1 X X X X X X X X

The K-map implementation are shown in the figure 4 for divider 16 and figure for
divider 15 which are found from the Table 1 and Table 2 respectively .The
respective equations are determined and given as follows.
For divider 16 from Table 1:-T3 = Q2Q1Q0 for T2:- T2 = Q1Q0 for T1:- T1 = Q0
for T0:- T0 = 1

Figure 4: Schematic of mod -16 frequency divider.

For divider 15 from Table 2:- T3 = Q2Q1Q0 + Q3Q2Q1 For T2:- T2 = Q1Q0 +
Q3Q2Q For T1:- T1 = Q0 + Q3Q2Q1 For T0:- T0 = Q1’ + Q3’ + Q0 + Q2’

Figure 5: Schematic of mod-15 frequency Divider.

Design of Integer N Frequency Divider for High Performance PLL 595

Results
The simulation results shows that D-FF and Integer N counter operating well at high
frequency of 2.4 GHz with the power supply voltage of 1.8V. High speed of the
circuits has been achieved by use of fast D-FF. Positive edge triggered D-FF also
resulted in high operating frequency, low power consumption and low power
dissipation. An efficient design has been obtained with minimum number of flip flops.
The output waveforms of single stage of N stage divider is shown in figure 6.

Figure 6: Output waveform of single unit of proposed divider chip.

Conclusion
In this paper, an Integer-N frequency divider suitable for high performance PLL has
been presented. The frequency divider has been implemented in a 180 nm standard
CMOS technology. The divider has the mod value of 240 which is made by
concatenated mod-16 and mod-15 frequency dividers. The circuits are simulated on
VIRTUOSO CADENCE TOOL with GPDK 180nM CMOS technology. The
simulation results shows that it operates well at the high frequency of 2.4GHz with
the power supply voltage of 1.8V, which can be applied to high speed and low voltage
PLL circuits and with enhanced features. Thus, the obtained circuit uses
comparatively less number of D-flip flops, resulting in efficient circuit designing used
in industrial or research and development application.

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596 R.H. Talwekar et al

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