VLSI DECODER ARCHITECTURE FOR
EMBEDDED ZEROTREE WAVELET ALGORITHM
Li-minn Ang, Hon Nin Cheung and Kamran Eshraghian
Centre for Very High Speed Microelectronic Systems
Edith Cowan University
Joondalup WA 6027, Australia
ABSTRACT
In this paper, we present a hardware architecture to implement
the decoder for the embedded zerotree wavelet (EZW) algorithm.
The decoder architecture complements an encoder architecture
for the EZW algorithm which has been reported recently.
Similar to the reported encoder architecture, the proposed
decoder architecture is regular and modular and is suitable for
VLSI implementation. The input into the decoder architecture is
the output data stream from the encoder architecture containing
the- significance map symbols and the successive-approximation
quantization symbols of the EZW algorithm. The decoding for
the EZW algorithm is formulated in view of the output data
stream from the encoder and the corresponding VLSI
architecture to implement the formulated requirements is
presented. The proposed EZW decoder architecture together
with th_e encoder architecture forms a basis for a scalable image
or'video coding system which is suitable for ASIC VLSI
implementation.
1. INTRODUCTION
In recent years, image and video coding algorithms have been
researched for their coding efficiency in general [l] and for their
scalability [2] in particular. The scalability of an image or video
coded bit-stream to allow for screen resolution displays of
different sizes and for transmission at different bit-rates is one of
the most desirable features in image and video coding [3].
Amongst the coding algorithms, the embedded zerotree wavelet
(EZW) algorithm [4] and its variants [5][6] have been found to
be promising solutions not only in terms of coding efficiency, but
also in their potential for scalable coding. After performing the
discrete wavelet transform (DWT), the EZW algorithm
establishes an ancestor-descendant relationship between the
wavelet coefficients of the image subbands. The EZW algorithm
uses the ancestor-descendant relationship contained in the tree
.hierarchy to efficiently code the positions and signs of the
significant coefficients as well as their approximate magnitudes
in decreasing order of importance. The positions and signs of the
significant coefficients are encoded in a significance map
(SMAP) and their approximate magnitudes are encoded using
successive-approximationquantization (SAQ). One symbol used
in coding the S M A P is the zerotree root (ZTR) symbol which is
used to inform the decoder that all the descendants of a
coefficient are not significant. To enable real-time applications,
researchers have proposed VLSI architectures to implement the
EZW algorithm [7][8]. The EZW architectures reported in [7]
and [8] are for the EZW encoder. One difficulty in designing the
EZW encoder is in locating the corresponding parent coefficient
for a given child coefficient [8]. The EZW encoder architecture
reported in [7] uses address pointers to specify the addresses of a
0-7803-5471-0/99/$10.0001999IEEE
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child coefficient and its corresponding parent coefficient stored
in memory. The approach taken by the EZW encoder
architecture reported in [8] is based on an efficient scheme to
determine ancestor-descendant relationships in the wavelet
coefficient data stream by rearrangement of the data stream. The
benefits of this approach are that the EZW encoder architecture is
regular and modular and does not require addressing hardware to
locate the parent and children coefficients in memory.
In this paper, we present a VLSI architecture to implement the
decoder to complement the EZW encoder architecture reported in
[8]. The input into the decoder is the output data stream from the
encoder containing the SMAP symbols and the SAQ symbols of
the EZW algorithm. One difficulty in designing the decoder
architecture is due to the removal of redundant ZTR symbols
from the output data stream by the encoder before transmission
to the decoder. For better coding efficiency, the encoder
removes from the output data stream the ZTR. symbols which can
be inferred by the decoder from previous information the decoder
has received from the encoder. The design approach is based on
developing an efficient scheme using FIFO queues to restore the
removed ZTR. symbols into the output data stream before the
decoding process. The decoding for the EZW algorithm is
formulated in view of the output data stream from the encoder
and the corresponding VLSI architecture to implement the
formulated requirements is reported. The proposed EZW
decoder architecturetogether with the encoder architecture forms
a basis for a scalable image or video coding system which is
suitable for ASIC VLSI implementation.
2. EZW ENCODER ARCHITECTURE
The EZW encoder architecture reported in [8] uses four symbols
POS (positive), NEG (negative), ISZ (isolated zero) and ZTR
(zerotree root) to code the SMAP and a futher two symbols
UPPER and LOWER for the SAQ of the wavelet coefficients.
The SMAP is coded based on the significance of the coefficient
and the combined significance of its descendant coefficients. A
coefficient is defined as significant if the magnitude of the
coefficient value is greater than or equal to the current threshold
value. A coefficient is coded as POS if the coefficient is
significant and the value of the coefficient is positive and is
coded as NEG if the coefficient is significant and the value of the
coefficient is negative. A coefficient is coded as ISZ if it is itself
not significant and at least one of its descendants is significant.
A coefficient is only coded as ZTR if it is itself not significant
and all its descendants are not significant. After a coefficient has
been found to be significant, the encoder uses the symbols
UPPER and LOWER to successively-approximatethe coefficient
magnitude at subsequent threshold values. The encoder uses the
symbol LOWER if the coefficient magnitude is less than the
approximated magnitude and the symbol UPPER if the
coefficient magnitude is greater than or equal to the
approximated magnitude. Each of the six symbols are coded
using three binary digits. The six symbols and their binary
representations are shown in Fig. 1 where CO, C1 and C2
represent the first, second and third binary digit respectively.
POS
NEG
IS2
ZTR
I I I I
Figure 1. Symbol binary representations
One difficulty in designing the EZW encoder is in locating the
corresponding parent coefficient for a given child coefficient.
The approach taken by the encoder architecture is based on an
efficient scheme to determine ancestor-descendant relationships
in the wavelet coefficient data stream by rearrangement of the
data stream for simpler VLSI implementation. Fig. 2(a) shows
an-example of an ancestor-descendant tree hierarchy using data
from [4] and Fig. 201) shows the arrangement in sign-magnitude
representation of the coefficient data stream. The m o w in Fig.
2(b) indicates the direction of the data stream. The bit positions
bo to b6 contains the magnitudes of the coefficients where b6 is
the MSB and bo is the LSB. The bit position b7 contains the sign
bits oWle coefficients.
leu12 .3l
M I &
,
IS
(a) Ancestor-descendant tree hierarchy
b,br ... b,
OOMllll
1 am101
I 0 wola,l
0oOax)ll
} level 0
) level 0
I 1 MM011
OowolOl
} level 0
(b) Coefficient data stream arrangement
Figure 2. Ancestor-descendanttree hierarchy
and coefficient data stream arrangement
A single bit-stream is formed from the data stream arrangement
in Fig. 2(b) as the input into the EZW encoder architecture. The
single bit data stream is formed fiom the sign bits, followed by
the MSBs and ending with the LSBs as shown in Fig. 3. The
output of the EZW encoder architecture is a data stream
containing the SMAP symbols and SAQ symbols as represented
by the binary digits CO, C1 and C2 shown in Fig. 1. Although
the input stream contains 168 bits, the output stream only
contains a maximum of 147 symbols. The information in the
sign bits are encoded in the POS and NEG SMAF’ symbols.
Furthermore, for better coding efficiency, the EZW encoder
removes fiom the output data stream ZTR symbols if it descends
from an ancestor coefficient which is also a ZTR symbol. This
removal of ZTR symbols from the output data stream by the
encoder adds a difficulty in designing the decoder architecture.
~ ,, EZW
Cl0..Cl6
1111 ... 0010 ... 0000 ... 0000 1010 ... 0100 encoder
cz, .. cr,
Figure 3. EZW encoder
I
3. PROBLEM FORMULATION
One difficulty in designing the EZW decoder architecture is due
to the removal of redundant ZTR symbols from the output data
stream by the encoder before transmission to the decoder. The
decoder design approach is based on developing an efficient
scheme using FIFO queues to restore the removed ZTR symbols
into the output data stream before the decoding process. A
specific difficulty in the restoration of the ZTR symbols is that
the decoder has to take into account the presence of the LOWER
and UPPER SAQ symbols and insert the necessary ZTR symbols
into their correct locations in the output data stream. For
example, Fig. 4(a)-4(d) shows the four possible interpretations
and their corresponding decoder output data stream for the
encoder input data stream {UPPER, ZTR} where the ZTR
symbol is the first symbol transmitted.
A&&&
UPPER m m m
,mmmU P P E R r n )
Zra UPPER zm m m m UPPm m ZTR m m UPPER
~ITIIIIRUPPuumITIo (zTR.UPpERLTRmm1 ( U P P u V I I L L I R I R r n l
(a) (b) (c) (4
Figure 4. Decoder possible interpretations and their
correspondingoutput data stream
The decoder selects the correct interpretation from information
the decoder has previously received from the encoder.
Specifically, the decoder keeps track of which wavelet
coefficient has already received a POS or NEG SMAP symbol.
Once a POS or NEG SMAP symbol has been received for a
wavelet coefficient, then subsequent symbols for the wavelet
coefficient can only be UPPER or LOWER SAQ symbols. To
formulate the restoration of the ZTR symbols, two additional
binary symbols DELAY-FLAG and SIG-FLAG are defmed.
The symbol DELAY-FLAG is set to ‘1’ if a ZTR symbol is to be
inserted into the output data stream. The symbol SIG-FLAG is
set to ‘1’ for wavelet coefficients which have already received a
POS or NEG S M A P symbol. Whenever the decoder receives a
symbol from the encoder, it inserts the symbol into a FKFO
queue, FIFO-SYMBOL. Fig. 5 shows the algorithm for the
restoration of the ZTR symbols into the output data stream.
i f DELAY-FLAG = 0 or SIG-FLAG = 1
remove SYMBOL from FIFO-SYMBOL queue
output SYMBOL into output data stream
else
output ZTR into output data stream
endif
Figure 5. Algorithm for restoration of ZTR symbols
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One way to implement the operation of the DELAY-FLAG is to
use a counter to keep track of the number of delays before the
decoder has to remove a symbol from the FIFO queue. Delays
are only required if the current symbol is a ZTR symbol and the
number of delays required is equal to the number of descendants
the coefficient has and is given by:
41+1 -1
delay = -- 1
3 magnitude bits are to be decoded. The control input is set to ‘0’
where the label I denotes the level of the coefficient in the
ancestor-descendant tree hierarchy where the leaf coefficients of
the tree are at level 0 and the root coefficient of the tree is at the
highest level. After the necessary ZTR symbols have been
inserted into the output data stream, the decoder carries out the
decoding of the S M A P symbols and the SAQ symbols into the
required coefficient bit-stream. Assuming that at each clock
cycle i, one symbol represented by the binaxy digits CO, C1 and
C2 is input into the architecture, then the decoding of the
symbols into the required bits b can be determined. The
coefficient magnitude bits are decoded by:
b, = C1, if CO,=O
= -Cl, if CO,= 1
where - is the NOT logical operator. The coefficient sign bits are
encoded in the POS and NEG S M A P symbols. The decoder
keeps-track of each POS or NEG symbol received for each
wavelet coefficient and decodes the sign bits by:
b, = 1 ifNEGSMAPsymbo1 received
= 0 if POS S W symbol received
hierarchy as in Fig. 2. The processors are implemented using
FIFO queues (FIFO-CO, FIFO-C1, FXFO-C2) to store the data
stream symbols, counters (COUNT20, COUNT4) to implement
the operation of the DELAY-FLAG, delay elements, logic gates
and multiplexers. The delay elements SRO and SRI can be
implemented using single-bit shift registers with the same size as
the number of coefficients to be decoded. The control input
SIGNMAGNITUDE-SELECTOR selects if sign bits or
to decode sign bits and is set to ‘1’ to decode magnitude bits.
The control input LEVEL-SELECTOR selects 1, the level of the
coefficient in the ancestor-descendanttree hierarchy.
Whenever processor P1 receives a symbol from the encoder, it
inserts the symbol which is represented by the binary digits CO,
C1 and C2 into the FIFO queues FIFO-CO, FIFO-C1 and
FIFO-C2 respectively. The insertion into the FIFO queues and
the removal from the FIFO queues are controlled by the fifo-wr
and fifo-rd control signals respectively. Whenever a symbol is
to be inserted into the queues, the fifo-wr control signal is set to
‘1’ and whenever a symbol is to be removed fiom the queues, the
fifo-rd control signal is set to ‘1’. The counters COUNT4 and
COUNT20 are reset whenever the current symbol is a ZTR
symbol and the DELAY-FLAG is ‘0’. The selection of which of
the counters is to be reset depends on the level of the ZTR
symbol in the ancestor-descendant tree hierarchy. For example,
if the current level is two, then the COUNT20 counter is reset.
The SIG-FLAG is set to ‘1’ for wavelet coefficients which have
already been decoded to be a POS or NEG SMAF’ symbol.
(3)
5. CONCLUSIONS

4. EZW DECODER ARCHITECTURE
Using the algorithm in Fig. 5 and Equations (2)-(3), we can
develop a hardware architecture for the EZW decoder which is
regular and modular and is suitable for VLSI implementation.
Fig. 6 shows the proposed decoder architecture using two
processors P1 and P2. The input into processor P1 is the output
data stream from the encoder containing the SMAP symbols and
the SAQ symbols as in Fig. 3. Processor P1 uses the algorithm
in Fig. 5 to restore the necessary ZTR symbols into the output
data stream. Processor P2 uses Equations (2)-(3) to decode the
restored output data stream into the required wavelet coefficient
bit-stream. Before the decoding process, processor P2 appends
zeros-to &e restored data stream to make the number of input
symbols equal to the number of output bits. The output of
processor P2 are the coefficient magnitude bits followed by the
coefficient sign bits. The coefficient magnitude bits are decoded
from the symbols CO’, C1’ and C2’. The appended zeros are
used to ‘push out’ the coefficient sign bits after the magnitude
bits have been decoded.
b [2] N. D. Wells and P. N. Tudor, “Standardisation of scalable
CI, c1, 0 O,Cl’, c1;
+ P1 w P2
b7,b0
c26
c20
- -
In this paper, we have presented a hardware architecture for the
EZW decoder which is regular and modular and is suitable for
VLSI implementation. The decoder architecture complements an
EZW encoder architecture which has been reported recently.
The input into the decoder architecture is the output data stream
from the encoder architecture containing the S W symbols and
the SAQ symbols of the EZW algorithm. The decoder design
approach is based on developing an efficient scheme using FIFO
queues to restore the ZTR symbols which have been removed by
the encoder before transmission. The decoding for the EZW
algorithm have been formulated in view of the output data stream
from the encoder and the corresponding VLSI architecture to
implement the formulated requirements has been reported. The
proposed EZW decoder architecture together with the encoder
architecture forms a basis for a scalable image or video coding
system which is suitable for ASIC VLSI implementation.
6. REFERENCES
[l] R. J. Clarke, “A survey of low-rate digital image coding
techniques,” 1993 Canadian Conference on Electrical and
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’6
coding schemes,” IEEE Colloquium on Digital Terrestrial
Television,pp. 611-618, Nov. 1993.
131 D. Taubman and A. Zakhor, “Rate- and resolution-scalable
video and image compression with subband coding,”
Twenty-Seventh Asilomar Conference on Signals, Systems
and Computers, Vol. 2 , pp. 1489-1493,Nov. 1993.

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J. M. Shapiro, “Embedded image coding using zerotrees of
wavelet coefficients,” IEEE Trans. Signal Processing, Vol.
41, No. 12, pp. 3445-3462, Dec. 1993.
A. Said and W. A. Pearlman, “A new fast and efficient
image codec based on set partitioning in hierarchical trees,”
IEEE Trans. Circuits and Systems for Video Technology,
Vol. 6, NO. 3, pp. 243-250, Jw. 1996.
S. A. Martucci, I. Sodagar, T. Chiang and Y. Zhang, “A
zerotree wavelet video coder,” IEEE Trans. Circuits and
systems for Video Technology, Vol. 7 , No. 1, pp. 109-118,
Feb. 1997.
[7] J. Bae and V. K. Prasanna, “A fast and area-efficient VLSI
architecture for embedded image coding ” Proceedings
International Conference on Image Processing, Vol. 3, pp.
452-455, Oct. 1995.
[8] L. Ang, €3. N. Cheung and K. Eshr@an, “VLSI
architecture for embedded zerotree wavelet coding,” to be
presented at the International Symposium on DSP for
CommunicationSystems, Feb. 1999.

LEVEL
SELECTOR

01

00

1
527 I

DELAY-FLAG

SIG-FLAG

-
Figure 7. VLSI architecture for processor P1

0 O,C2’, CTk 4.4 43

0 0 , C l k C’k

0 0,co; CV6
Figure 8. VLSI architecture for processor P2

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