South Dakota School of Mines and Technology EE 647 Spring 2005 Page 1 of 20

EE 647 HDL Design

Lab #2 VHDL-Based Design in Xilinx ISE 6.X and ModelSim

Due Thursday 3/24/2005

Dr. Nian Zhang

South Dakota School of Mines and Technology

_______________________________________________________________________________

LAB #2 REQUIREMENTS

1. Turn in the truth table on page 14. (2 points)

2. Turn in the functional simulation waveform before Synthesis. (2 points)
3. Turn in the timing simulation waveform after Place & Route. (2 points)
4. Turn in the CLB slice on page 18. (2 points)
5. Report the difference between the functional simulation waveform (i.e. before
Synthesis) and the timing simulation waveform (i.e. after Place & Route). Explain
it. (2 points)
_____________________________________________________________________

This tutorial is intended to provide you with an introduction to the tools that you will
be using throughout this semester. While this tutorial attempts to expose you to the
most common buttons, icons, menu options, etc. in the software, it will not
demonstrate all of the features. Once completing the tutorial you are encouraged to
explore more capabilities of the tools. The more familiar you are with your design
environment, the more productive you will be. Before we begin looking at VHDL and
its FPGA implementation in the lab, we will introduce the design flow for VHDL
entry.

BACKGROUND - VHDL DESIGN FLOW

STEP 1 – Design Entry

The first step in the design process is to input your design into a machine-readable
format. To do this you will use a Computer Aided Design tool. In this course, we will
use Xilinx ISE software. A typical CAD tool supports many design entry methods,
such as a schematic capture, HDL entry (VHDL/Verilog) or a component net list. In
this course, all digital designs are captured using VHDL.

STEP 2 – Functional Simulation

Once a design has been captured in the CAD tools, the next step is to simulate the

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design. This is done to ensure that the captured design will meet the design
requirement. A functional simulation is used to verify the logical behavior of the
circuit. It is very important to realize that simulations of this type do not contain any
physical implementation details, which implies that they do not include any timing
related information. Designs that pass a functional simulation are on their way to
being realizable in hardware, but will not necessarily work as expected.

STEP 3 – Synthesis

Once you are satisfied that your design will meet all of the required specifications,
you can proceed to preparing the design for hardware implementation. During
synthesis, the CAD tools will interpret your HDL design information and infer
standard building block to implement your design (registers, MUX, look-up tables,
adder, etc.). Subtle differences in your HDL description can result in different
hardware being inferred at this stage. In other words, the same logical design can be
described in a number of ways using VHDL, this leads to different hardware being
used to realize the circuit inferred from the HDL. After synthesis, you can then
perform a post-synthesis simulation. This simulation will include timing information
extracted from the inferred hardware.

STEP 4 – Implementation

The Xilinx implementation process takes your design through the TRANSLATE,
MAP, and PLACE & ROUTE processes. The TRANSLATE process converts the
netlist generated from the synthesis process into a form specific to the target device.
The MAP process translates the standard building blocks into the specific resources
available in the target hardware. The PLACE & ROUTE process picks up where the
MAP process leaves off by allocating specific resources (PLACING) and
interconnecting (ROUTING) the placed design.

STEP 5 – Device Configuration

After the design has been verified at each stage, a binary hardware configuration file
is generated (*.bit). This file is then downloaded into the FPGA via the JTAG
interface.

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INTRODCUTION TO XILINX 6.X AND MODELSIM

STARTING XILINX FOUNDATION 6.X

Double click the Project Navigator shortcut icon on the desktop, or select Start - >
Program -> Xilinx ISE 6 -> Project Navigator

CREATING A NEW PROJECT

All design data in the Xilinx tool is stored in the form of a project. We will begin by
creating a new project. Select File -> New Project to open the new project dialogue
box.

Select a meaningful name for your new project. A directory of the same name will be
created in the path shown in the Project Location field. Select HDL as the
Top-Level Module Type. Click Next.

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In this course, we use a Spartan IIE XC2S200E-PQ208-6. Our synthesis tool will be
XST. We use ModelSim as out simulator and we will use VHDL as our simulation
language. Click on Next.

Click on Next.

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Click on Next.

Click Finish.

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CREATING A NEW SOURCE FILE

Select Project -> New Source will create a blank document in the workspace
window.

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Select a meaningful name. Select VHDL Module. The location should default to your
project directory. Click Next.

We will make a combinational circuit with 4 inputs and 1 output. Create 4 inputs (A
through D) and 1 output, Z.

Click Next.

Confirm the settings for your design and click Finish.

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DEFINE THE ARCHITECTURE

In this lab, we will implement the following logic function using VHDL:
Z <= (A and B and C) or D;

You can enter the above dataflow VHDL code into the body of your architecture
(between the begin and end). Or you can enter the behavioral VHDL code into the
body of your architecture (between the begin and end):

p1: process(A,B,C,D)
begin
if (A = '1' and B = '1' and C = '1') then
Z <= '1';
elsif (D = '1') then
Z <= '1';
else
Z <= '0';
end if;
end process;

Either way will obtain the same functional simulation waveforms.

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Click File -> Save. Now we have modeled the circuit. Next we will create a test
bench to simulate the design.

CREATING TEST BENCH

To perform a functional simulation, you will need a test bench.

Select Project -> New Source to open the new source dialogue box again. Select Test
Bench Waveform. (Note that you could select VHDL Test Bench if you want to
create a test bench manually.) In keeping with a good naming habit, we will name our
test bench with the design name plus the suffix “_tb” (i.e. CombCircuit_tb).

Click Next.

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You are asked to associate your test bench with a source file. You will find only one
source file. Click Next.

Verify your test bench settings, click Finish.

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The above Initialize Timing window will pop up. Keep the default settings, click on
OK.

The above HDL Bencher will show up in the workspace window. This tool is used to
enter input stimulus. Inputs are represented by blue squares, and outputs are
represented by yellow squares. Clicking on any colored square will toggle its value.

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Since there are 4 inputs, so there should be 16 possible input combinations. Generate
the 16 possible input combinations. Note the blue vertical line in the HDL Bencher.
This line specifies the end of the generated vectors. Select File -> Save. Once you
save your test bench, notice that it is automatically added to your project. Xilinx
automatically generates a corresponding VHDL behavioral model for the test bench
waveform. To view this file, double click View Behavioral Testbench from the
processes window with the test bench selected in the source window. We are now
ready to simulate the design.

FUNCTIONAL SIMULATION

With CombCircuit_tb (CombCircuit_tb.tbw) selected in the source window, double

click Simulate Behavioral Model. This will launch ModelSim simulator.

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Structure Window:

The structure window displayed the hierarchy of your design. The top-level module
will always be your test bench.

Signal Window:

The signal window will show all of the ports declared in the entity definition for the
selected module.

Wave Window:

Select View -> Zoom -> Zoom Full. You can customize the display by color coding
or selecting the radix for your signals and then File -> Save Format to save the
display settings. You can File -> Load Format to restore your settings next time you
run a simulation.

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Generate a truth table for the logic function:

Z <= (A and B and C) or D;

A B C D Z
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

Compare the output in the wave window to the truth table you just create. Once you
are satisfied with the functional simulation, print out your waveform by selecting File
-> Print in the wave window, Name field should be the default printer’s name. In the
Time Range field, select Full Range.

Close ModelSim.

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SYNTHESIS

To synthesize your design, select combcircuit-behavioral (CombCircuit.vhdl) in the

sources window and double click Synthesize-XST. This will begin the synthesis
process. If the synthesis was successful, a green check mark will appear beside the
synthesis process.

Next step is to perform pin assignment. Pin assignment is the process of associating
logical ports with physical pins. If you do not specify which pins your logical ports
should be connected to, the tools will randomly assign pin locations.

Pin assignments and other user-defined constraints are contained in a User Constraint
File (*.ucf). To create a UCF file select your design file in the sources window and
expand the User Constraints folder in the processes window. Double-click the
Assign Package Pins process. The following dialogue will pop up.

Click Yes. This will launch the Xilinx PACE editor.

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The PACE editor allows you to associate your logical ports to the physical pins of
your target package. Expanding the I/O Pins folder in the Design Browser window
will reveal the logical ports in your design. The ports are also listed in the Design
Object List –I/O Pins window. You can type the desired pin number into the Loc field
in the Design Object List –I/O Pins window. Ignore the pull-down list in Loc field. A
P must prefix all pin numbers. For example, if you want to assign logical port A to
physical pin 163, you will type P163 in the Loc field. Once you assign a pin number
to a logical port, a corresponding Bank number will be automatically assigned. So you
don’t need to worry about the Bank number.

File -> Save and exit the Xilinx PACE editor. Once you save the settings, all of the
information contained in the GUI interface is written to a combcircuit.ucf file ( the
*.ucf file has the same name as the design entity you are configuring). It is listed in
sources window. You can view the contents of the file by going to your working
directory (i.e. C:\NianZhang\EE647\EE647Labs\Lab2), right click combcircuit.ucf
-> Open With -> Notepad. The combcircuit.ucf file looks as follows.

IMPLEMENTATION

Select your design module (i.e. combcircuit-behavioral (CombCircuit.vhdl)) in the

sources window and double click the Implement Design process. This can take some

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time if you have a large design or slow computer. Confirm that the process completes
successfully.

Now we have completed the implementation process. To view the final

implementation of your design, ensure your design module is still selected in the
sources window. Expand the Implement Design process, and then expand the Place
& Route process. Double click View/Edit Routed Design (FPGA Editor).

This will launch Xilinx FPGA Editor. In the Array 1 window you will see all 1176
Configurable Logic Blocks (CLB) in your Spartan II device. Any utilized resources
will be colored blue and all of the interconnect will be turquoise. Zoom in to get a
better view.

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Double click the blue CLB slice (not the I/O blocks around the outer perimeter) and
you will see the circuit inside. Print the CLB slice.

Select View -> Zoom in. Our design occupied a portion of a CLB, which was
highlighted by the 4-input LUT (Look-Up Tables) and the turquoise interconnections.
By double clicking on the LUT, we can see the function that the LUT performs at the
bottom of the screen: D=(A1+(A4*(A3*A2))). Look at the names of the inputs and
output of the LUT, and notice the correspondence between the logical ports (i.e. A, B,
C, D, Z) and the LUT inputs (i.e. A1, A2, A3, A4, D).

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TIMING SIMULATION

Timing simulation uses the block and routing delay information from a routed design
to give a more accurate assessment of the behavior of the circuit under worst-case
conditions. For this reason, timing simulation is performed after the design has been
placed and routed.

With CombCircuit_tb (CombCircuit_tb.tbw) selected in the source window, double

click Simulate Post-Place & Route VHDL Model. This will launch ModelSim
simulator.

Structure Window:

Signal Window:

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Wave Window:

Once you are satisfied with the timing simulation, print out your waveform by
selecting File -> Print in the wave window, Name field should be the default printer’s
name. In the Time Range field, select Full Range.

Compare this Post-Place & Route simulation waveform to the functional simulation
waveform before Synthesis. Report the difference in the report, and explain it.

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