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Ultraprecision

Operational Amplifier
OP177
FEATURES PIN CONFIGURATION
Ultralow offset voltage
VOS TRIM 1 8 VOS TRIM
TA = 25°C, 25 μV maximum OP177
–IN 2 7 V+
Outstanding offset voltage drift 0.1 μV/°C maximum
+IN 3 6 OUT
Excellent open-loop gain and gain linearity
TOP VIEW
V– 4 5 NC

00289-001
12 V/μV typical (Not to Scale)

CMRR: 130 dB minimum NC = NO CONNECT

PSRR: 115 dB minimum Figure 1. 8-Lead PDIP (P-Suffix),


8-Lead SOIC (S-Suffix)
Low supply current 2.0 mA maximum
Fits industry-standard precision op amp sockets

GENERAL DESCRIPTION operational amplifier. The combination of outstanding


specifications of the OP177 ensures accurate performance in
The OP177 features one of the highest precision performance of
high closed-loop gain applications.
any op amp currently available. Offset voltage of the OP177 is
only 25 μV maximum at room temperature. The ultralow VOS of This low noise, bipolar input op amp is also a cost effective
the OP177 combines with its exceptional offset voltage drift alternative to chopper-stabilized amplifiers. The OP177
(TCVOS) of 0.1 μV/°C maximum to eliminate the need for provides chopper-type performance without the usual problems
external VOS adjustment and increases system accuracy over of high noise, low frequency chopper spikes, large physical size,
temperature. limited common-mode input voltage range, and bulky external
storage capacitors.
The OP177 open-loop gain of 12 V/μV is maintained over the
full ±10 V output range. CMRR of 130 dB minimum, PSRR of The OP177 is offered in the −40°C to +85°C extended industrial
120 dB minimum, and maximum supply current of 2 mA are temperature ranges. This product is available in 8-lead PDIP, as
just a few examples of the excellent performance of this well as the space saving 8-lead SOIC.

FUNCTIONAL BLOCK DIAGRAM


V+
R2A* (OPTIONAL NULL) R2B*
C1 R7
R1A R1B

2B Q19
Q9 Q10

Q11 Q12 R9
Q7 Q8
Q5 Q3 Q6 Q4 OUTPUT
R3 C3 C2 Q17
NONINVERTING Q27 R10
INPUT Q16
Q1 Q26 R5
Q21 Q23 Q20
Q25
R4 Q22 Q24
INVERTING Q15
INPUT Q2
Q18
Q14

Q13 R6 R8
00289-002

V–

*R2A AND R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY.

Figure 2. Simplified Schematic

Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©1995–2009 Analog Devices, Inc. All rights reserved.
OP177

TABLE OF CONTENTS
Features .............................................................................................. 1  Applications Information .................................................................9 

Pin Configuration ............................................................................. 1  Gain Linearity ................................................................................9 

General Description ......................................................................... 1  Thermocouple Amplifier with Cold-Junction


Compensation ........................................................................................ 9 
Functional Block Diagram .............................................................. 1 
Precision High Gain Differential Amplifier ........................... 10 
Revision History ............................................................................... 2 
Isolating Large Capacitive Loads.............................................. 10 
Specifications..................................................................................... 3 
Bilateral Current Source ............................................................ 10 
Electrical Characteristics ............................................................. 3 
Precision Absolute Value Amplifier ......................................... 10 
Test Circuits ................................................................................... 4 
Precision Positive Peak Detector .............................................. 12 
Absolute Maximum Ratings............................................................ 5 
Precision Threshold Detector/Amplifier ................................ 12 
Thermal Resistance ...................................................................... 5 
Outline Dimensions ....................................................................... 13 
ESD Caution .................................................................................. 5 
Ordering Guide .......................................................................... 14 
Typical Performance Characteristics ............................................. 6 

REVISION HISTORY
3/09—Rev. E to Rev. F Changes to Figure 12 through Figure 17 ........................................7
Added Figure 23, Renumbered Sequentially ................................ 8 Changes to Figure 18 through Figure 22 ........................................8
Updated Outline Dimensions ....................................................... 13 Change to Figure 27 ....................................................................... 10
Changes to Figure 30 and Figure 31............................................. 11
5/06—Rev. D to Rev. E Updated Outline Dimensions ....................................................... 13
Changes to Figure 1 .......................................................................... 1 Changes to Ordering Guide .......................................................... 13
Change to Specifications Table 1 .................................................... 3
Changes to Specifications Table 2................................................... 4 1/05—Rev. B to Rev. C
Changes to Table 3 ............................................................................ 5 Edits to Features.................................................................................1
Changes to Figure 23 and Figure 24 ............................................... 9 Edits to General Description ...........................................................1
Changes to Figure 32 ...................................................................... 12 Edits to Pin Connections ..................................................................1
Updated the Ordering Guide ........................................................ 14 Edits to Electrical Characteristics .............................................. 2, 3
Global deletion of references to OP177E ............................ 3, 4, 10
4/06—Rev. C to Rev. D Edits to Absolute Maximum Ratings ..............................................5
Change to Pin Configuration Caption........................................... 1 Edits to Package Type .......................................................................5
Changes to Features.......................................................................... 1 Edits to Ordering Guide ...................................................................5
Change to Table 2 ............................................................................. 4 Edit to Outline Dimensions .......................................................... 11
Change to Figure 2 ........................................................................... 4
Changes to Figure 10 and Figure 11 ............................................... 6 11/95—Rev. 0: Initial Version

Rev. F | Page 2 of 16
OP177

SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
@ VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 1.
OP177F OP177G
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
INPUT OFFSET VOLTAGE VOS 10 25 20 60 μV
LONG-TERM INPUT OFFSET 1
Voltage Stability ΔVOS/time 0.3 0.4 μV/mo
INPUT OFFSET CURRENT IOS 0.3 1.5 0.3 2.8 nA
INPUT BIAS CURRENT IB −0.2 +1.2 +2 −0.2 +1.2 +2.8 nA
2
INPUT NOISE VOLTAGE en fO = 1 Hz to 100 Hz 118 150 118 150 nV rms
INPUT NOISE CURRENT in fO = 1 Hz to 100 Hz2 3 8 3 8 pA rms
INPUT RESISTANCE
Differential Mode 3 RIN 26 45 18.5 45 MΩ
INPUT RESISTANCE COMMON MODE RINCM 200 200 GΩ
INPUT VOLTAGE RANGE 4 IVR ±13 ±14 ±13 ±14 V
COMMON-MODE REJECTION RATIO CMRR VCM = ±13 V 130 140 115 140 dB
POWER SUPPLY REJECTION RATIO PSRR VS = ±3 V to ±18 V 115 125 110 120 dB
LARGE SIGNAL VOLTAGE GAIN AVO RL ≥ 2 kΩ, VO = ±10 V 5 5000 12,000 2000 6000 V/mV
OUTPUT VOLTAGE SWING VO RL ≥ 10 kΩ ±13.5 ±14.0 ±13.5 ±14.0 V
RL ≥ 2 kΩ ±12.5 ±13.0 ±12.5 ±13.0 V
RL ≥ 1 kΩ ±12.0 ±12.5 ±12.0 ±12.5 V
SLEW RATE2 SR RL ≥ 2 kΩ 0.1 0.3 0.1 0.3 V/μs
CLOSED-LOOP BANDWIDTH2 BW AVCL = 1 0.4 0.6 0.4 0.6 MHz
OPEN-LOOP OUTPUT RESISTANCE RO 60 60 Ω
POWER CONSUMPTION PD VS = ±15 V, no load 50 60 50 60 mW
VS = ±3 V, no load 3.5 4.5 3.5 4.5 mW
SUPPLY CURRENT ISY VS = ±15 V, no load 1.6 2 1.6 2 mA
OFFSET ADJUSTMENT RANGE RP = 20 kΩ ±3 ±3 mV
1
Long-term input offset voltage stability refers to the averaged trend line of VOS vs. time over extended periods after the first 30 days of operation. Excluding the initial
hour of operation, changes in VOS during the first 30 operating days are typically less than 2.0 μV.
2
Sample tested.
3
Guaranteed by design.
4
Guaranteed by CMRR test condition.
5
To ensure high open-loop gain throughout the ±10 V output range, AVO is tested at −10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and –10 V ≤ VO ≤ +10 V.

Rev. F | Page 3 of 16
OP177
@ VS = ±15 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 2.
OP177F OP177G
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
INPUT
Input Offset Voltage VOS 15 40 20 100 μV
Average Input Offset Voltage Drift 1 TCVOS 0.1 0.3 0.7 1.2 μV/°C
Input Offset Current IOS 0.5 2.2 0.5 4.5 nA
Average Input Offset Current Drift 2 TCIOS 1.5 40 1.5 85 pA/°C
Input Bias Current IB −0.2 +2.4 +4 +2.4 ±6 nA
Average Input Bias Current Drift2 TCIB 8 40 15 60 pA/°C
Input Voltage Range 3 IVR ±13 ±13.5 ±13 ±13.5 V
COMMON-MODE REJECTION RATIO CMRR VCM = ±13 V 120 140 110 140 dB
POWER SUPPLY REJECTION RATIO PSRR VS = ±3 V to ±18 V 110 120 106 115 dB
LARGE-SIGNAL VOLTAGE GAIN 4 AVO RL ≥ 2 kΩ, VO = ±10 V 2000 6000 1000 4000 V/mV
OUTPUT VOLTAGE SWING VO RL ≥ 2 kΩ ±12 ±13 ±12 ±13 V
POWER CONSUMPTION PD VS = ±15 V, no load 60 75 60 75 mW
SUPPLY CURRENT ISY VS = ±15 V, no load 20 2.5 2 2.5 mA
1
TCVOS is sample tested.
2
Guaranteed by endpoint limits.
3
Guaranteed by CMRR test condition.
4
To ensure high open-loop gain throughout the ±10 V output range, AVO is tested at −10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and −10 V ≤ VO ≤ +10 V.

TEST CIRCUITS
200kΩ

50Ω

OP177 VO
00289-003

+ VO
VOS =
4000

Figure 3. Typical Offset Voltage Test Circuit

20kΩ
V+

– –
INPUT OP177 OUTPUT
+ +
VOS TRIM RANGE IS
00289-004

TYPICALLY ±3.0mV
V–

Figure 4. Optional Offset Nulling Circuit

20kΩ
+20V


OP177
+ PINOUTS SHOWN FOR
P AND Z PACKAGES
00289-005

–20V

Figure 5. Burn-In Circuit

Rev. F | Page 4 of 16
OP177

ABSOLUTE MAXIMUM RATINGS


Table 3. Stresses above those listed under Absolute Maximum Ratings
Parameter Ratings may cause permanent damage to the device. This is a stress
Supply Voltage ±22 V rating only; functional operation of the device at these or any
Internal Power Dissipation1 500 mW other conditions above those indicated in the operational
Differential Input Voltage ±30 V section of this specification is not implied. Exposure to absolute
Input Voltage ±22 V maximum rating conditions for extended periods may affect
Output Short-Circuit Duration Indefinite device reliability.
Storage Temperature Range −65°C to +125°C
THERMAL RESISTANCE
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 60 sec) 300°C θJA is specified for worst-case mounting conditions, that is, θJA
DICE Junction Temperature (TJ) −65°C to +150°C is specified for device in socket for PDIP; θJA is specified for
1
device soldered to printed circuit board for SOIC package.
For supply voltages less than ±22 V, the absolute maximum input voltage is
equal to the supply voltage. Table 4. Thermal Resistance
Package Type θJA θJC Unit
8-Lead PDIP (P-Suffix) 103 43 °C/W
8-Lead SOIC (S-Suffix) 158 43 °C/W

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. F | Page 5 of 16
OP177

TYPICAL PERFORMANCE CHARACTERISTICS


2 20
TA = 25°C VS = ±15V
VS = ±15V
RL = 10kΩ 25
DEVICE IMMERSED IN
(NULLED TO 0mV @ VOUT = 0V)

INPUT OFFSET VOLTAGE (µV)


1 70° OIL BATH (20 UNITS)

ABSOLUTE CHANGE IN
INPUT VOLTAGE (µV)

30

0 35

40
–1
45

00289-009
00289-006
–2 50
–10 –5 0 5 10 0 10 20 30 40 50 60 70
OUTPUT VOLTAGE (V) TIME (Seconds)

Figure 6. Gain Linearity (Input Voltage vs. Output Voltage) Figure 9. Offset Voltage Change Due to Thermal Shock

100 25
TA = 25°C VS = ±15V

20
POWER CONSUMPTION (mW)

OPEN-LOOP GAIN (V/µV)

15

10

10

00289-010
00289-007

1 0
0 10 20 30 40 –55 –35 –15 5 25 45 65 85 105 125
TOTAL SUPPLY VOLTAGE, V+ TO V– (V) TEMPERATURE (°C)

Figure 7. Power Consumption vs. Power Supply Figure 10. Open-Loop Gain vs. Temperature

5 16
TA = 25°C
4 RL = 2kΩ

3
LOT A 12
OPEN-LOOP GAIN (V/µV)

2 LOT B
LOT C
1 LOT D
VOS (µV)

0 8

–1

–2
4
–3
00289-011
00289-008

–4

–5 0
0 20 40 60 80 100 120 140 160 180 0 ±5 ±10 ±15 ±20
TIME (Seconds) POWER SUPPLY VOLTAGE (V)

Figure 8. Warm-Up VOS Drift (Normalized) Z Package Figure 11. Open-Loop Gain vs. Power Supply Voltage

Rev. F | Page 6 of 16
OP177
4 160
VS = ±15V TA = 25°C
140 VS = ±15V

3 120
INPUT BIAS CURRENT (nA)

OPEN-LOOP GAIN (dB)


100

2 80

60

1 40

20

00289-015
00289-012
0 0
–50 0 50 100 0.01 0.1 1 10 100 1k 10k 100k 1M
TEMPERATURE (°C) FREQUENCY (Hz)

Figure 12. Input Bias Current vs. Temperature Figure 15. Open-Loop Frequency Response

2.0 150
VS = ±15V TA = 25°C
140
INPUT OFFSET CURRENT (nA)

1.5
130

CMRR (dB)
120
1.0
110

100
0.5

90
00289-013

00289-016
0 80
–50 0 50 100 1 10 100 1k 10k 100k
TEMPERATURE (°C) FREQUENCY (Hz)

Figure 13. Input Offset Current vs. Temperature Figure 16. CMRR vs. Frequency

100 130
TA = 25°C TA = 25°C
VS = ±15V
120
80
CLOSED-LOOP GAIN (dB)

110
60
PSRR (dB)

100
40
90

20
80

0 70
00289-017
00289-014

–20 60
10 100 1k 10k 100k 1M 10M 0.1 1 10 100 1k 10k
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 14. Closed-Loop Response for Various Gain Configurations Figure 17. PSRR vs. Frequency

Rev. F | Page 7 of 16
OP177
1000 20
TA = 25°C
RS1 = RS2 = 200kΩ
VS = +15V
THERMAL NOISE OF SOURCE
VIN = ±10mV
INPUT NOISE VOLTAGE (nV√Hz)

RESISTORS INCLUDED
15 POSITIVE SWING

MAXIMUM OUTPUT (V)


100
NEGATIVE SWING

10
EXCLUDED
RS = 0
10
5

TA = 25°C

00289-018

00289-021
VS = ±15V
1 0
1 10 100 1k 100 1k 10k
FREQUENCY (Hz) LOAD RESISTANCE TO GROUND (Ω)
Figure 18. Total Input Noise Voltage vs. Frequency Figure 21. Maximum Output Voltage vs. Load Resistance

10 40
TA = 25°C TA = 25°C
VS = ±15V VS = ±15V

OUTPUT SHORT-CIRCUIT CURRENT (mA)


35

+ISC
RMS NOISE (µV)

30

25
–ISC

20

00289-022
00289-019

0.1 15
100 1k 10k 100k 0 1 2 3 4
BANDWIDTH (Hz) TIME FROM OUTPUT BEING SHORTED (Minutes)

Figure 19. Input Wideband Noise vs. Bandwidth Figure 22. Output Short-Circuit Current vs. Time
(0.1 Hz to Frequency Indicated)

32 1.50
TA = 25°C TA = 25°C
VS = ±15V VS = ±15V
28
1.25
PEAK-TO-PEAK AMPLITUDE (V)

24
1.00
20
IB (nA)

16 0.75

12 IB1– (nA)
0.50 IB2– (nA)
IB3– (nA)
8 IB1+ (nA)
0.25 IB2+ (nA)
4 IB3+ (nA)
00289-033
00289-020

0 0
1k 10k 100k 1M –16 –14 –10 –6 –2 2 6 10 14
FREQUENCY (Hz) VCM (V)

Figure 20. Maximum Output Swing vs. Frequency Figure 23. Input Bias (IB) vs. Common-Mode Voltage (VCM)

Rev. F | Page 8 of 16
OP177

APPLICATIONS INFORMATION
GAIN LINEARITY THERMOCOUPLE AMPLIFIER WITH COLD-
JUNCTION COMPENSATION
The actual open-loop gain of most monolithic op amps varies at
different output voltages. This nonlinearity causes errors in high An example of a precision circuit is a thermocouple amplifier
closed-loop gain circuits. that must accurately amplify very low level signals without
introducing linearity and offset errors to the circuit. In this
It is important to know that the manufacturer’s AVO specifica- circuit, an S-type thermocouple with a Seebeck coefficient of
tion is only a part of the solution because all automated testers 10.3 μV/°C produces 10.3 mV of output voltage at a temperature
use endpoint testing and, therefore, show only the average gain. of 1000°C. The amplifier gain is set at 973.16, thus, it produces
For example, Figure 24 shows a typical precision op amp with a an output voltage of 10.024 V. Extended temperature ranges
respectable open-loop gain of 650 V/mV. However, the gain is beyond 1500°C are accomplished by reducing the amplifier
not constant through the output voltage range, causing non- gain. The circuit uses a low cost diode to sense the temperature
linear errors. An ideal op amp shows a horizontal scope trace. at the terminating junctions and, in turn, compensates for any
ambient temperature change. The OP177, with its high open-
Figure 25 shows the OP177 output gain linearity trace with its
loop gain plus low offset voltage and drift, combines to yield a
truly impressive average AVO of 12,000 V/mV. The output trace
precise temperature sensing circuit. Circuit values for other
is virtually horizontal at all points, assuring extremely high gain
thermocouple types are listed in Table 5.
accuracy. Analog Devices also performs additional testing to
ensure consistent high open-loop gain at various output Table 5.
voltages. Figure 26 is a simple open-loop gain test circuit. Thermocouple Seebeck
Type Coefficient R1 R2 R7 R9
K 39.2 μV/°C 110 Ω 5.76 kΩ 102 kΩ 269 kΩ
J 50.2 μV/°C 100 Ω 4.02 kΩ 80.6 kΩ 200 kΩ
VX S 10.3 μV/°C 100 Ω 20.5 kΩ 392 kΩ 1.07 MΩ
–10V 0V +10V

2 6 10.000V
+15V REF01

4 R7 R9
2.2µF R3
00289-023

AVO ≥ 650V/mV 47kΩ 392kΩ 1.07MΩ


+ 1% 0.05%
RL = 2kΩ 1%

Figure 24. Typical Precision Op Amp +15V


10µF
0.1µF
+

VY ISOTHERMAL R2 R8 10µF
COLD- 20.5kΩ 1.0kΩ
JUNCTIONS 1% 0.05%
– –
TYPES COPPER R5
+ COPPER 100Ω
OP177 VOUT
VX (ZERO + 10µF
ISOTHERMAL ADJUST-
–10V 0V +10V BLOCK R1 MENT)
100Ω 10µF 0.1µF
R4
COLD-JUNCTION 1% 50Ω
COMPENSATION
1%
00289-024

AVO ≥ 12000V/mV –15V ANALOG


RL = 2kΩ
GROUND
00289-026

Figure 25. Output Gain Linearity Trace ANALOG


GROUND

Figure 27. Thermocouple Amplifier with Cold Junction Compensation


VY

10kΩ 10kΩ

VIN = ±10V 1MΩ


VX

10Ω OP177
+ RL
00289-025

Figure 26. Open-Loop Gain Linearity Test Circuit

Rev. F | Page 9 of 16
OP177
PRECISION HIGH GAIN DIFFERENTIAL AMPLIFIER ISOLATING LARGE CAPACITIVE LOADS
The high gain, gain linearity, CMRR, and low TCVOS of the The circuit shown in Figure 29 reduces maximum slew rate but
OP177 make it possible to obtain performance not previously allows driving capacitive loads of any size without instability.
available in single stage, very high gain amplifier applications. Because the 100 Ω resistor is inside the feedback loop, its effect
See Figure 28. on output impedance is reduced to insignificance by the high
open loop gain of the OP177.
R1 R3
For best CMR, must equal RF
R2 R4
10pF

In this example, with a 10 mV differential signal, the maximum


+15V
errors are listed in Table 6.
0.1µF
R2
1MΩ RS 2 7
INPUT –
6 100Ω
+15V
OP177 OUTPUT
3
0.1µF + 4 0.1µF CLOAD

R1

00289-028
1kΩ 7
2

R3 6 –15V
1kΩ
OP177
3 Figure 29. Isolating Capacitive Loads
+
4
R4 0.1µF
1MΩ BILATERAL CURRENT SOURCE
00289-027

The current sources shown in Figure 30 supply both positive


–15V
and negative currents into a grounded load.
Figure 28. Precision High Gain Differential Amplifier
Note that
Table 6. High Gain Differential Amp Performance
⎛ R4 ⎞
Type Amount R5⎜ + 1⎟
Common-Mode Voltage 0.1%/V ZO = ⎝ R2 ⎠
Gain Linearity, Worst Case 0.02% R5 + R4 R3

TCVOS 0.0003%/°C R2 R1
TCIOS 0.008%/°C
and that for ZO to be infinite
R5 + R4 R3
must =
R2 R1

PRECISION ABSOLUTE VALUE AMPLIFIER


The high gain and low TCVOS assure accurate operation with
inputs from microvolts to volts. In this circuit, the signal always
appears as a common-mode signal to the op amps (for details,
see Figure 31).

Rev. F | Page 10 of 16
OP177
BASIC CURRENT SOURCE 100mA CURRENT SOURCE
R3
1kΩ R3
+15V
R1
100kΩ 2 R1 2
VIN – VIN – 2N2222
R2 6 6 50Ω
100kΩ
OP177 R2
OP177
3 3
+ R5
+ 2N2907
R5
R4 10Ω
990Ω R4 –15V
IOUT ≤ 15mA IOUT ≤ 100mA

R3
IOUT = VIN

00289-029
R1 × R5
GIVEN R3 = R4 + R5, R1 = R2

Figure 30. Bilateral Current Source

1kΩ 1kΩ

+15V
+15V 0.1µF
0.1µF C1 D1
30pF 1N4148 7
2
7

2 6
– OP177 VOUT
6 3 0 < VOUT < 10V
OP177 +
3 2N4393 4
VIN + 0.1µF
R3
4 0.1µF 2kΩ

00289-030
–15V

–15V

Figure 31. Precision Absolute Value Amplifier

1kΩ

+15V
+15V
0.1µF
1N4148 0.1µF

7 NC
2 2 7
– –
6 6
OP177 2N930
AD820 VOUT
1kΩ 3 1kΩ
VIN + 3
4
+
4
0.1µF CH 0.1µF

–15V –15V

RESET 1kΩ
00289-031

Figure 32. Precision Positive Peak Detector

Rev. F | Page 11 of 16
OP177
CC
PRECISION POSITIVE PEAK DETECTOR
RF
In Figure 32, CH must be polystyrene, Teflon®, or polyethylene 100kΩ
to minimize dielectric absorption and leakage. The droop rate is
+15V
determined by the size of CH and the bias current of the AD820.
0.1µF
RS
PRECISION THRESHOLD DETECTOR/AMPLIFIER VTH
1kΩ 2
– 7 D1
1N4148
R1 6
In Figure 33, when VIN < VTH, amplifier output swings negative, OP177 VOUT
2kΩ 3
reverse biasing diode D1. VOUT = VTH if RL = ∞. When VIN ≥ VIN + 4 0.1µF
VTH, the loop closes.

00289-032
⎛ R ⎞
VOUT = VTH + (VIN − VTH ) ⎜⎜1 + F ⎟⎟
–15V

Figure 33. Precision Threshold Detector/Amplifier


⎝ RS ⎠

CC is selected to smooth the response of the loop.

Rev. F | Page 12 of 16
OP177

OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)

8 5 0.280 (7.11)
0.250 (6.35)
1 0.240 (6.10)
4
0.325 (8.26)
PIN 1 0.310 (7.87)
0.100 (2.54) 0.300 (7.62)
BSC 0.060 (1.52) 0.195 (4.95)
0.210 MAX
(5.33) 0.130 (3.30)
MAX 0.115 (2.92)
0.015
0.150 (3.81) (0.38)0.015 (0.38)
0.130 (3.30) MIN GAUGE
0.115 (2.92) PLANE 0.014 (0.36)
SEATING
PLANE 0.010 (0.25)
0.022 (0.56) 0.008 (0.20)
0.005 (0.13) 0.430 (10.92)
0.018 (0.46) MIN MAX
0.014 (0.36)

0.070 (1.78)
0.060 (1.52)
0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001-BA


CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 34. 8-Lead Plastic Dual In-Line Package (PDIP)


P-Suffix
(N-8)
Dimensions show in inches and (millimeters)

5.00 (0.1968)
4.80 (0.1890)

8 5
4.00 (0.1574) 6.20 (0.2440)
3.80 (0.1497) 1 4 5.80 (0.2284)

1.27 (0.0500) 0.50 (0.0196)


BSC 1.75 (0.0688) × 45°
0.25 (0.0099)
0.25 (0.0098) 1.35 (0.0532)
0.10 (0.0040)
0.51 (0.0201) 8°
COPLANARITY 0.25 (0.0098) 0° 1.27 (0.0500)
0.10 SEATING 0.31 (0.0122) 0.40 (0.0157)
PLANE 0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-AA


CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 35. 8-Lead Standard Small Outline Package (SOIC_N)


S-Suffix
(R-8)
Dimensions shown in millimeters and( inches)

Rev. F | Page 13 of 16
OP177
ORDERING GUIDE
Model Temperature Range Package Description Package Option
OP177FP −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
OP177FPZ1 −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
OP177GP −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
OP177GPZ1 −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
OP177FS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP177FS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP177FS-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP177FSZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP177FSZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP177FSZ-REEL71 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP177GS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP177GS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP177GS-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP177GSZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP177GSZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP177GSZ-REEL71 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
1
Z = RoHS Compliant Part.

Rev. F | Page 14 of 16
OP177

NOTES

Rev. F | Page 15 of 16
OP177

NOTES

©1995–2009 Analog Devices, Inc. All rights reserved. Trademarks and


registered trademarks are the property of their respective owners.
D00289-0-3/09(F)

Rev. F | Page 16 of 16