Name of Student ……………………. Registration No. ………………..

Sant Longowal Institute of Engineering & Technology

Department of Electronics & Communication Engineering

Sub Name: Elements of Electronics Major TIME ALLOWED: 3 Hr

Engineering Examination
Sub Code: ECT-421 MAXIMUM MARKS: 50
Name of Teacher: Rajesh K Pathak Month/Year: 11/7/2019

Note: Question No.1 in PART-A is Compulsory. Attempt any two questions each from PART-B and PART-C
Q. No. PART-A Marks
1. a) Convert the decimal number (562)10 to Octal number. 1x10
b) (i) The Boolean expression (X + Y). (X + Y’) + ((X + Y’) + X)’ simplifies to
(a) X (b) Y (c) XY (d) None
c) The minimum number of 2 -input NOR gates required implementing a 2– input XOR
gate i
(a) 4 (b) 5 (c) 6 (d) 7
d) Draw energy band diagram of n-type semiconductor.
e) Why binary number system is preferred over other number system in digital logic
design?
f) Draw the symbol of n-p-n and p-n-p transistor.
g) Write expression for conductivity of semiconductor.
h) In a p-n junction diode magnitude of electric field is always maximum at the junction.
(T/F)
i) When EBJ is RB and CBJ is RB the BJT is working in active region.(T/F)
j) For a BJT working in active region α=.8 and base current 𝑖𝐵 =6µA. find𝑖𝐶 , 𝑖𝐸 .
PART-B
2 a) A function of Boolean variables X, Y and Z is expressed as F(X, Y, Z) = Σ (1, 2, 5, 6, 7
7). Find simplified SOP expression .Implement the logic function using minimum number
of NAND gates.
b) Compare CE, CB and CC configurations in tabular form on the basis of their input, output 3
impedance, gain and applications.
OR
a) .What do you mean by DC load line and bias point, explain the procedure for drawing 7
the dc load line on transistor CE output characteristics, and also discuss the Q-point for
the transistor bias circuit
b) In a half wave rectifier the peak value of the ac voltage across the secondary of the 3
transformer is 40√2V.If no filter circuit is used then find the maximum dc voltage (in
volt) across the load.
3 a) Explain the working of P-N junction diode in forward and reverse bias. Which type of 5
breakdown occur in lightly doped diodes.
b) .Explain Zener diode circuit as a voltage regulator. 5
Name of Student ……………………. Registration No. ………………..

Sant Longowal Institute of Engineering & Technology

Department of Electronics & Communication Engineering

Sub Name: Elements of Electronics Major TIME ALLOWED: 3 Hr

Engineering Examination
Sub Code: ECT-421 MAXIMUM MARKS: 50
Name of Teacher: Rajesh K Pathak Month/Year: 11/7/2019

PART-C
4 a) What do you mean by MOSFET? Draw and explain basic construction and transfer 8
characteristics of an n-channel enhancement type MOSFET. What is meant by
threshold voltage
b) In a p-type Si sample the hole concentration is 2.25 × 1016 𝑐𝑚−3 the intrinsic carrier 2
concentration is1.5 × 1010 𝑐𝑚−3 , find electron concentration.
OR
a) What do you mean by inverting and non-inverting Op-Amp. Draw the circuit diagram of 5
an inverting summer with ideal Op-Amp and derive the equation of output voltage
b) What do you mean by JFET? Draw and explain basic construction and characteristics 5
of a n-channel JFET. What is meant by pinch-off voltage?
7 a) Explain input and output characteristics of common emitter configuration with the help 5
of circuit diagram
b) What are the properties of ideal operational amplifier? By drawing suitable circuit 5
diagram derive the relation of input and output voltage for an Integrator using op-amp.