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Course outline
• Overview of von Neumann architecture &
Instruction set architecture.
• Pipelining .
• Hierarchical Memory Technology .
• Instruction-level parallelism.
• Multiprocessor Architecture.
• Non von Neumann Architectures.
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• Computer organization is how operational
attributes are linked together and contribute to
realize the architectural specifications.
• Computer architecture is the architectural
attrributes like physical address memory,CPU and
how they should be made and made to coordinate
with each other keeping the future demands and
goals in mind.
• Computer architecture comes before computer
organiation.
Computer
Data
CPU Main
Bus Memory
Control
3
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von Neumann Architecture
• A more complete view of the computer system architecture
that integrates interaction (human or otherwise) consists of:
Computer System
Computer
Input
Data Device
CPU Main
Bus Memory Bus
Control Output
Device
Five Main Components: Bus
1. CPU
2. Main Memory (RAM)
Secondary
Storage
3. I/O Devices
Device
4. Mass Storage
5. Interconnection network (Bus)
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Instruction Set Design
software
instruction
Hardware
5
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The Instruction Cycle - Basic View
Execute
Instruction
(IE)
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The Instruction Cycle - Exceptions
Start
Possible
Exception Decode
? Instruction
Possible
Exception Fetch
? Operand
Possible Execute
Exception? Instruction
Fetch
Operand
Execute
Instruction
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The Instruction Cycle - Exceptions
Start
Fetch
Operand
Execute
Instruction
Execute
Instruction
8
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Instruction Architecture
• Software design
• Hardware circuits
OpCode
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Instruction Architecture - Software Design
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Instruction Architecture - CPU
• The CPU must be designed to accommodate the instructions
and data to be processed
System Bus
CPU RAM
System Bus
ALU Regs
Address Bus
Control Bus
Data Bus
PC
CU
IR
Internal
PSW
CPU Bus
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Instruction Architecture - Hardware Circuits
• Data is represented by various types of “signals”, including
electrical, magnetic, optical and so on. Data “moves” through
the computer along wires that form the various bus networks
(address, data, control) and which interconnect the gates.
Instruction Architecture - CU
12
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Instruction Architecture - ALU
13
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